2022-03-17 19:55:11

by Ian Rogers

Subject: [PATCH 5/8] perf vendor events: Update events for Skylake

The change:
https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
moved certain "other" type of events in to the cache topic. Update the
perf json files for this change.

Signed-off-by: Ian Rogers <[email protected]>
---
.../pmu-events/arch/x86/skylake/cache.json | 36 +++++++++++++++++++
.../pmu-events/arch/x86/skylake/other.json | 36 -------------------
2 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json
index 529c5e6e117f..c5d9a4ed10d7 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json
@@ -2937,5 +2937,41 @@
"PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
"SampleAfterValue": "100003",
"UMask": "0x10"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHNTA instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.NTA",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHW instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT0 instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T0",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T1_T2",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x4"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json
index 5c0e81f76a5b..4f4839024915 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/other.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/other.json
@@ -16,41 +16,5 @@
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"SampleAfterValue": "2000003",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.NTA",
- "SampleAfterValue": "2000003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHW instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "SampleAfterValue": "2000003",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T0",
- "SampleAfterValue": "2000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "SampleAfterValue": "2000003",
- "UMask": "0x4"
}
]
\ No newline at end of file
--
2.35.1.894.gb6a874cedc-goog

2022-03-18 11:32:09

by Xing Zhengjun

Subject: Re: [PATCH 5/8] perf vendor events: Update events for Skylake

On 3/18/2022 2:28 AM, Ian Rogers wrote:
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the cache topic. Update the
> perf json files for this change.
>
> Signed-off-by: Ian Rogers <[email protected]>

Reviewed-by: Zhengjun Xing <[email protected]>

> ---
> .../pmu-events/arch/x86/skylake/cache.json | 36 +++++++++++++++++++
> .../pmu-events/arch/x86/skylake/other.json | 36 -------------------
> 2 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json
> index 529c5e6e117f..c5d9a4ed10d7 100644
> --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json
> @@ -2937,5 +2937,41 @@
> "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
> "SampleAfterValue": "100003",
> "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.NTA",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHW instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T0",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x4"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json
> index 5c0e81f76a5b..4f4839024915 100644
> --- a/tools/perf/pmu-events/arch/x86/skylake/other.json
> +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json
> @@ -16,41 +16,5 @@
> "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
> "SampleAfterValue": "2000003",
> "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.NTA",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHW instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T0",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x4"
> }
> ]
> \ No newline at end of file

--
Zhengjun Xing