Add documentation details for device tree bindings for QDU1000 and QRU1000
TLMM devices.
Signed-off-by: Melody Olvera <[email protected]>
---
.../pinctrl/qcom,qdru1000-pinctrl.yaml | 133 ++++++++++++++++++
1 file changed, 133 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
new file mode 100644
index 000000000000..e8d938303231
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block
+
+maintainers:
+ - Melody Olvera <[email protected]>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,qdu1000-tlmm
+ - const: qcom,qru1000-tlmm
+
+ reg:
+ items:
+ - description: Base address of TLMM register space
+ - description: Size of TLMM register space
+
+ interrupts:
+ minItems: 0
+ maxItems: 1
+ items:
+ - const: TLMM summary IRQ
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ wakeup-parent:
+ maxItems: 1
+ description:
+ Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+ a general description of GPIO and interrupt bindings.
+
+ Please refer to pinctrl-bindings.txt in this directory for details of the
+ common pinctrl bindings used by client devices, including the meaning of the
+ phrase "pin configuration node".
+
+ The pin configuration nodes act as a container for an arbitrary number of
+ subnodes. Each of these subnodes represents some desired configuration for a
+ pin, a group, or a list of pins or groups. This configuration can include the
+ mux function to select on those pin(s)/group(s), and various pin configuration
+ parameters, such as pull-up, drive strength, etc.
+
+
+# PIN CONFIGURATION NODES
+patternPropetries:
+ '^.*$':
+ if:
+ type: object
+ then:
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in
+ this subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
+ - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
+ minItems: 1
+ maxItems: 36
+ function:
+ description:
+ Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ enum: [gpio, aon_cam, atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
+ atest_usb0, atest_usb00, atest_usb01, atest_usb02, atest_usb03, audio_ref, cam_mclk,
+ cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+ cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, coex_uart2, cri_trng, cri_trng0,
+ cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1,
+ gcc_gp2, gcc_gp3, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+ mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s2_data0, mi2s2_data1,
+ mi2s2_sck, mi2s2_ws, mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
+ mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, mss_grfc8, mss_grfc9,
+ nav_0, nav_1, nav_2, pcie0_clkreqn, pcie1_clkreqn, phase_flag0, phase_flag1,
+ phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
+ phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
+ phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
+ phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
+ phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, pll_bist,
+ pll_clk, pri_mi2s, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
+ qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
+ qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
+ qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable,
+ qlink1_request, qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
+ qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15,
+ qup16, qup17, qup18, qup19, qup2, qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8,
+ qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd,
+ sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
+ tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
+ uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0,
+ vfr_1, vsense_trigger]
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ output-high: true
+ output-low: true
+ required:
+ - pins
+ - function
+ additionalProperties: false
+
+examples:
+ - |
+ tlmm: pinctrl@03000000 {
+ compatible = "qcom,qdu10000-tlmm";
+ reg = <0x03000000 0xdc2000>;
+ interrupts = <0 208 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
+ };
--
2.37.3
On 01/10/2022 05:05, Melody Olvera wrote:
> Add documentation details for device tree bindings for QDU1000 and QRU1000
> TLMM devices.
>
> Signed-off-by: Melody Olvera <[email protected]>
> ---
> .../pinctrl/qcom,qdru1000-pinctrl.yaml | 133 ++++++++++++++++++
> 1 file changed, 133 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
> new file mode 100644
> index 000000000000..e8d938303231
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
> @@ -0,0 +1,133 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block
> +
> +maintainers:
> + - Melody Olvera <[email protected]>
> +
> +description: |
> + This binding describes the Top Level Mode Multiplexer block.
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,qdu1000-tlmm
> + - const: qcom,qru1000-tlmm
> +
> + reg:
> + items:
> + - description: Base address of TLMM register space
> + - description: Size of TLMM register space
> +
> + interrupts:
> + minItems: 0
Cannot be 0 of interrupts.
> + maxItems: 1
> + items:
> + - const: TLMM summary IRQ
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 2
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
> +
> + wakeup-parent:
> + maxItems: 1
> + description:
> + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
> + a general description of GPIO and interrupt bindings.
> +
> + Please refer to pinctrl-bindings.txt in this directory for details of the
> + common pinctrl bindings used by client devices, including the meaning of the
> + phrase "pin configuration node".
> +
> + The pin configuration nodes act as a container for an arbitrary number of
> + subnodes. Each of these subnodes represents some desired configuration for a
> + pin, a group, or a list of pins or groups. This configuration can include the
> + mux function to select on those pin(s)/group(s), and various pin configuration
> + parameters, such as pull-up, drive strength, etc.
> +
> +
> +# PIN CONFIGURATION NODES
> +patternPropetries:
> + '^.*$':
> + if:
> + type: object
> + then:
Nope, that's not correct binding. It does not work. It never worked.
Please do it exactly like:
https://lore.kernel.org/linux-devicetree/[email protected]/T/#m08b62ef5d873a52a5cbf3c53b25eff03726e7a16
https://lore.kernel.org/linux-devicetree/[email protected]/T/#t
> + properties:
> + pins:
> + description:
> + List of gpio pins affected by the properties specified in
> + this subnode.
> + items:
> + oneOf:
> + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
> + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
> + minItems: 1
> + maxItems: 36
> + function:
> + description:
> + Specify the alternative function to be configured for the
> + specified pins. Functions are only valid for gpio pins.
> + enum: [gpio, aon_cam, atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
> + atest_usb0, atest_usb00, atest_usb01, atest_usb02, atest_usb03, audio_ref, cam_mclk,
> + cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
> + cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, coex_uart2, cri_trng, cri_trng0,
> + cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1,
> + gcc_gp2, gcc_gp3, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
> + mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s2_data0, mi2s2_data1,
> + mi2s2_sck, mi2s2_ws, mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
> + mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, mss_grfc8, mss_grfc9,
> + nav_0, nav_1, nav_2, pcie0_clkreqn, pcie1_clkreqn, phase_flag0, phase_flag1,
> + phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
> + phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
> + phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
> + phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
> + phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, pll_bist,
> + pll_clk, pri_mi2s, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
> + qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
> + qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
> + qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable,
> + qlink1_request, qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
> + qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15,
> + qup16, qup17, qup18, qup19, qup2, qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8,
> + qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd,
> + sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
> + tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
> + uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0,
> + vfr_1, vsense_trigger]
> + drive-strength:
> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> + default: 2
> + description:
> + Selects the drive strength for the specified pins, in mA.
> + bias-pull-down: true
> + bias-pull-up: true
> + bias-disable: true
> + output-high: true
> + output-low: true
You miss blank lines in several places. Please do it exactly like I
shown for sdm845.
> + required:
> + - pins
> + - function
> + additionalProperties: false
> +
> +examples:
> + - |
> + tlmm: pinctrl@03000000 {
> + compatible = "qcom,qdu10000-tlmm";
> + reg = <0x03000000 0xdc2000>;
> + interrupts = <0 208 0>;
Use defines.
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + wakeup-parent = <&pdc>;
Missing children.
> + };
Best regards,
Krzysztof
On Fri, 30 Sep 2022 20:05:45 -0700, Melody Olvera wrote:
> Add documentation details for device tree bindings for QDU1000 and QRU1000
> TLMM devices.
>
> Signed-off-by: Melody Olvera <[email protected]>
> ---
> .../pinctrl/qcom,qdru1000-pinctrl.yaml | 133 ++++++++++++++++++
> 1 file changed, 133 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:81:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:82:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:83:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:84:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:85:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:86:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:87:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:88:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:89:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:90:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:91:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:92:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:93:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:94:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:95:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:96:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:97:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:98:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:99:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:100:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:101:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:102:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:103:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:104:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:105:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml:106:13: [warning] wrong indentation: expected 17 but found 12 (indentation)
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml: properties:interrupts:minItems: 0 is less than the minimum of 1
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml: properties:interrupts: {'minItems': 0, 'maxItems': 1, 'items': [{'const': 'TLMM summary IRQ'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml: properties:interrupts: 'oneOf' conditional failed, one must be fixed:
[{'const': 'TLMM summary IRQ'}] is too short
False schema does not allow 0
1 was expected
hint: "minItems" is only needed if less than the "items" list length
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml: 'patternPropetries' is not one of ['$id', '$schema', 'title', 'description', 'examples', 'required', 'allOf', 'anyOf', 'oneOf', 'definitions', '$defs', 'additionalProperties', 'dependencies', 'dependentRequired', 'dependentSchemas', 'patternProperties', 'properties', 'if', 'then', 'else', 'unevaluatedProperties', 'deprecated', 'maintainers', 'select', '$ref']
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml: 'oneOf' conditional failed, one must be fixed:
'unevaluatedProperties' is a required property
'additionalProperties' is a required property
hint: Either unevaluatedProperties or additionalProperties must be present
from schema $id: http://devicetree.org/meta-schemas/core.yaml#
./Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml: error checking schema file
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml: ignoring, error in schema: properties: interrupts: minItems
Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.example.dts:21.32-30.11: Warning (unit_address_format): /example-0/pinctrl@03000000: unit name should not have leading 0s
Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.example.dtb:0:0: /example-0/pinctrl@03000000: failed to match any schema with compatible: ['qcom,qdu10000-tlmm']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On 10/1/2022 4:20 AM, Krzysztof Kozlowski wrote:
> On 01/10/2022 05:05, Melody Olvera wrote:
>> Add documentation details for device tree bindings for QDU1000 and QRU1000
>> TLMM devices.
>>
>> Signed-off-by: Melody Olvera <[email protected]>
>> ---
>> .../pinctrl/qcom,qdru1000-pinctrl.yaml | 133 ++++++++++++++++++
>> 1 file changed, 133 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
>> new file mode 100644
>> index 000000000000..e8d938303231
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml
>> @@ -0,0 +1,133 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,qdru1000-pinctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block
>> +
>> +maintainers:
>> + - Melody Olvera <[email protected]>
>> +
>> +description: |
>> + This binding describes the Top Level Mode Multiplexer block.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: qcom,qdu1000-tlmm
>> + - const: qcom,qru1000-tlmm
>> +
>> + reg:
>> + items:
>> + - description: Base address of TLMM register space
>> + - description: Size of TLMM register space
>> +
>> + interrupts:
>> + minItems: 0
> Cannot be 0 of interrupts.
>
>> + maxItems: 1
>> + items:
>> + - const: TLMM summary IRQ
>> +
>> + interrupt-controller: true
>> +
>> + '#interrupt-cells':
>> + const: 2
>> +
>> + gpio-controller: true
>> +
>> + '#gpio-cells':
>> + const: 2
>> +
>> + wakeup-parent:
>> + maxItems: 1
>> + description:
>> + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
>> + a general description of GPIO and interrupt bindings.
>> +
>> + Please refer to pinctrl-bindings.txt in this directory for details of the
>> + common pinctrl bindings used by client devices, including the meaning of the
>> + phrase "pin configuration node".
>> +
>> + The pin configuration nodes act as a container for an arbitrary number of
>> + subnodes. Each of these subnodes represents some desired configuration for a
>> + pin, a group, or a list of pins or groups. This configuration can include the
>> + mux function to select on those pin(s)/group(s), and various pin configuration
>> + parameters, such as pull-up, drive strength, etc.
>> +
>> +
>> +# PIN CONFIGURATION NODES
>> +patternPropetries:
>> + '^.*$':
>> + if:
>> + type: object
>> + then:
> Nope, that's not correct binding. It does not work. It never worked.
>
> Please do it exactly like:
> https://lore.kernel.org/linux-devicetree/[email protected]/T/#m08b62ef5d873a52a5cbf3c53b25eff03726e7a16
> https://lore.kernel.org/linux-devicetree/[email protected]/T/#t
Understood; will correct the binding.
>
>> + properties:
>> + pins:
>> + description:
>> + List of gpio pins affected by the properties specified in
>> + this subnode.
>> + items:
>> + oneOf:
>> + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
>> + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
>> + minItems: 1
>> + maxItems: 36
>> + function:
>> + description:
>> + Specify the alternative function to be configured for the
>> + specified pins. Functions are only valid for gpio pins.
>> + enum: [gpio, aon_cam, atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
>> + atest_usb0, atest_usb00, atest_usb01, atest_usb02, atest_usb03, audio_ref, cam_mclk,
>> + cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
>> + cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, coex_uart2, cri_trng, cri_trng0,
>> + cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1,
>> + gcc_gp2, gcc_gp3, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
>> + mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s2_data0, mi2s2_data1,
>> + mi2s2_sck, mi2s2_ws, mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
>> + mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, mss_grfc8, mss_grfc9,
>> + nav_0, nav_1, nav_2, pcie0_clkreqn, pcie1_clkreqn, phase_flag0, phase_flag1,
>> + phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
>> + phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
>> + phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
>> + phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
>> + phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, pll_bist,
>> + pll_clk, pri_mi2s, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
>> + qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
>> + qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
>> + qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable,
>> + qlink1_request, qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
>> + qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15,
>> + qup16, qup17, qup18, qup19, qup2, qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8,
>> + qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd,
>> + sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
>> + tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
>> + uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0,
>> + vfr_1, vsense_trigger]
>> + drive-strength:
>> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
>> + default: 2
>> + description:
>> + Selects the drive strength for the specified pins, in mA.
>> + bias-pull-down: true
>> + bias-pull-up: true
>> + bias-disable: true
>> + output-high: true
>> + output-low: true
> You miss blank lines in several places. Please do it exactly like I
> shown for sdm845.
Ditto for above.
>
>> + required:
>> + - pins
>> + - function
>> + additionalProperties: false
>> +
>> +examples:
>> + - |
>> + tlmm: pinctrl@03000000 {
>> + compatible = "qcom,qdu10000-tlmm";
>> + reg = <0x03000000 0xdc2000>;
>> + interrupts = <0 208 0>;
> Use defines.
Understood.
>
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + wakeup-parent = <&pdc>;
> Missing children.
Will add.
>
>> + };
> Best regards,
> Krzysztof
Thanks,
Melody