2023-06-23 14:34:05

by Komal Bajaj

Subject: [PATCH v4 2/6] dt-bindings: cache: qcom,llcc: Add LLCC compatible for QDU1000/QRU1000

Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional
nvmem-cells and nvmem-cell-names property.

Signed-off-by: Komal Bajaj <[email protected]>
---
Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 44892aa589fd..580f9a97ddf7 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -20,6 +20,7 @@ description: |
properties:
compatible:
enum:
+ - qcom,qdu1000-llcc
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
@@ -44,6 +45,14 @@ properties:
interrupts:
maxItems: 1

+ nvmem-cells:
+ items:
+ - description: Reference to an nvmem node for multi channel DDR
+
+ nvmem-cell-names:
+ items:
+ - const: multi-chan-ddr
+
required:
- compatible
- reg
@@ -92,6 +101,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,qdu1000-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
then:
--
2.40.1

2023-06-23 17:14:45

by Krzysztof Kozlowski

Subject: Re: [PATCH v4 2/6] dt-bindings: cache: qcom,llcc: Add LLCC compatible for QDU1000/QRU1000

On 23/06/2023 16:18, Komal Bajaj wrote:
> Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional
> nvmem-cells and nvmem-cell-names property.

Your commit should explain why you are doing this. I can easily see from
the diff that you add nvmem-cells. But why?

>
> Signed-off-by: Komal Bajaj <[email protected]>
> ---
> Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>


Best regards,
Krzysztof