Hi Nancy,
On Sa, 2022-04-16 at 10:07 +0800, Nancy.Lin wrote:
> Add vdosys1 ETHDR definition.
>
> Signed-off-by: Nancy.Lin <[email protected]>
> Reviewed-by: Chun-Kuang Hu <[email protected]>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> .../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++
> 1 file changed, 158 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> new file mode 100644
> index 000000000000..e8303c28a361
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Ethdr Device Tree Bindings
> +
> +maintainers:
> + - Chun-Kuang Hu <[email protected]>
> + - Philipp Zabel <[email protected]>
> +
> +description: |
> + ETHDR is designed for HDR video and graphics conversion in the external display path.
> + It handles multiple HDR input types and performs tone mapping, color space/color
> + format conversion, and then combine different layers, output the required HDR or
> + SDR signal to the subsequent display path. This engine is composed of two video
> + frontends, two graphic frontends, one video backend and a mixer. ETHDR has two
> + DMA function blocks, DS and ADL. These two function blocks read the pre-programmed
> + registers from DRAM and set them to HW in the v-blanking period.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt8195-disp-ethdr
> + reg:
> + maxItems: 7
> + reg-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + interrupts:
> + minItems: 1
> + iommus:
> + description: The compatible property is DMA function blocks.
> + Should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> + details.
> + minItems: 1
> + maxItems: 2
> + clocks:
> + items:
> + - description: mixer clock
> + - description: video frontend 0 clock
> + - description: video frontend 1 clock
> + - description: graphic frontend 0 clock
> + - description: graphic frontend 1 clock
> + - description: video backend clock
> + - description: autodownload and menuload clock
> + - description: video frontend 0 async clock
> + - description: video frontend 1 async clock
> + - description: graphic frontend 0 async clock
> + - description: graphic frontend 1 async clock
> + - description: video backend async clock
> + - description: ethdr top clock
> + clock-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + - const: vdo_fe0_async
> + - const: vdo_fe1_async
> + - const: gfx_fe0_async
> + - const: gfx_fe1_async
> + - const: vdo_be_async
> + - const: ethdr_top
> + power-domains:
> + maxItems: 1
> + resets:
> + maxItems: 5
Please add a reset-names property and name these resets.
regards
Philipp