This patch continues support for the imxrt series now adding the imxrt1170
This patch contains:
- Update to imxrt_defconfig
- Devicetree
- Clock driver
- Pinctrl driver
- New pll
This patch also updates some documentation for both imxrt1170 an 1050.
The i.MXRT1170 has a vast array of features including two cores,
2 Ethernet, 2 USB phy, and a 2d gpu.
It also is featured in a new google coral board
https://coral.ai/products/dev-board-micro
Not affiliated unfortunately.
---
V1 -> V2:
- Add 3 new commits in documentation
- Fix spelling
---
Jesse Taube (10):
dt-bindings: arm: imx: Add i.MXRT compatible Documentation
dt-bindings: timer: gpt: Add i.MXRT compatible Documentation
dt-bindings: mmc: fsl-imx-esdhc: add i.MXRT1170 compatible
dt-bindings: serial: fsl-lpuart: add i.MXRT1170 compatible
ARM: mach-imx: Add support for i.MXRT1170
clk: imx: Update pllv3 to support i.MXRT1170
dt-bindings: imx: Add clock binding for i.MXRT1170
clk: imx: Add initial support for i.MXRT1170 clock driver
ARM: dts: imx: Add i.MXRT1170-EVK support
ARM: imxrt_defconfig: Add i.MXRT1170
.../devicetree/bindings/arm/fsl.yaml | 12 +
.../bindings/mmc/fsl-imx-esdhc.yaml | 4 +
.../bindings/serial/fsl-lpuart.yaml | 3 +
.../devicetree/bindings/timer/fsl,imxgpt.yaml | 2 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imxrt1170-evk.dts | 110 +++
arch/arm/boot/dts/imxrt1170.dtsi | 276 +++++++
arch/arm/configs/imxrt_defconfig | 17 +
arch/arm/mach-imx/mach-imxrt.c | 1 +
drivers/clk/imx/Kconfig | 7 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imxrt1170.c | 749 ++++++++++++++++++
drivers/clk/imx/clk-pllv3.c | 57 +-
drivers/clk/imx/clk.h | 11 +-
include/dt-bindings/clock/imxrt1170-clock.h | 282 +++++++
15 files changed, 1526 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/boot/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/boot/dts/imxrt1170.dtsi
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h
--
2.36.1
Add i.MXRT1170 compatible string to Documentation.
Cc: Giulio Benetti <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- New commit to fix dtbs_check
V2 -> V3:
- Fix typo
- Remove unused const
V3 -> V4:
- Nothing done
V4 -> V5:
- Nothing done
V5 -> V6:
- Nothing done
---
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
index 29339d0196ec..0e7833478869 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
@@ -75,6 +75,10 @@ properties:
- const: fsl,imx8qxp-usdhc
- const: fsl,imx7d-usdhc
deprecated: true
+ - items:
+ - enum:
+ - fsl,imxrt1170-usdhc
+ - const: fsl,imxrt1050-usdhc
reg:
maxItems: 1
--
2.36.1
Recently the imxrt1050 was added but the cpu compatible node wasn't
added. Add both i.MXRT1170 and 1050 compatibles to fsl.yaml.
Signed-off-by: Jesse Taube <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
V1 -> V2:
- Swap order of soc's
V2 -> V3:
- Nothing done
V3 -> V4:
- Nothing done
V4 -> V5:
- Nothing done
V5 -> V6:
- Nothing done
---
Documentation/devicetree/bindings/arm/fsl.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 7431579ab0e8..03350dd1fc58 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1053,6 +1053,18 @@ properties:
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- const: fsl,imx93
+ - description: i.MXRT1050 based Boards
+ items:
+ - enum:
+ - fsl,imxrt1050-evk # i.MXRT1050 EVK Board
+ - const: fsl,imxrt1050
+
+ - description: i.MXRT1170 based Boards
+ items:
+ - enum:
+ - fsl,imxrt1170-evk # i.MXRT1170 EVK Board
+ - const: fsl,imxrt1170
+
- description:
Freescale Vybrid Platform Device Tree Bindings
--
2.36.1
The i.MXRT1170 has a pll that has the multiplier bits inverted and
cannot be changed add IMX_PLLV3_GENERICV2.
The i.MXRT1170 also has the lock bit moved as well as the
power bit inverted the power bit also is in different locations on each
pll control register.
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Nothing done
V2 -> V3:
- Nothing done
V3 -> V4:
- Nothing done
V4 -> V5:
- Add __imx_clk_hw_pllv3 to change power bit
- Add BM_PLL_POWER and imx_clk_hw_pllv3 to header
- Remove imx_clk_hw_pll3_powerbit
V5 -> V6:
- Fix __imx_clk_hw_pllv3 deffintion
- Fix imx_clk_hw_pllv3 macro
- Remove imx_clk_hw_pll3_powerbit
---
drivers/clk/imx/clk-pllv3.c | 57 +++++++++++++++++++++++++++++++++----
drivers/clk/imx/clk.h | 11 +++++--
2 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index eea32f87c60a..68b1498cafe1 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -21,8 +21,8 @@
#define PLL_VF610_NUM_OFFSET 0x20
#define PLL_VF610_DENOM_OFFSET 0x30
-#define BM_PLL_POWER (0x1 << 12)
#define BM_PLL_LOCK (0x1 << 31)
+#define BM_PLL_LOCK_V2 (0x1 << 29)
#define IMX7_ENET_PLL_POWER (0x1 << 5)
#define IMX7_DDR_PLL_POWER (0x1 << 20)
@@ -34,6 +34,7 @@
* @base: base address of PLL registers
* @power_bit: pll power bit mask
* @powerup_set: set power_bit to power up the PLL
+ * @lock_bit: pll lock bit mask
* @div_mask: mask of divider bits
* @div_shift: shift of divider bits
* @ref_clock: reference clock rate
@@ -48,6 +49,7 @@ struct clk_pllv3 {
void __iomem *base;
u32 power_bit;
bool powerup_set;
+ u32 lock_bit;
u32 div_mask;
u32 div_shift;
unsigned long ref_clock;
@@ -65,7 +67,7 @@ static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
return 0;
- return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
+ return readl_relaxed_poll_timeout(pll->base, val, val & pll->lock_bit,
500, PLL_LOCK_TIMEOUT);
}
@@ -101,7 +103,7 @@ static int clk_pllv3_is_prepared(struct clk_hw *hw)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
- if (readl_relaxed(pll->base) & BM_PLL_LOCK)
+ if (readl_relaxed(pll->base) & pll->lock_bit)
return 1;
return 0;
@@ -155,6 +157,39 @@ static const struct clk_ops clk_pllv3_ops = {
.set_rate = clk_pllv3_set_rate,
};
+static int clk_pllv3_genericv2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+ u32 val, div;
+
+ div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
+ val = (div == 0) ? parent_rate * 22 : parent_rate * 20;
+
+ if (rate == val)
+ return 0;
+
+ return -EINVAL;
+}
+
+static unsigned long clk_pllv3_genericv2_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+ u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
+
+ return (div == 0) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static const struct clk_ops clk_pllv3_genericv2_ops = {
+ .prepare = clk_pllv3_prepare,
+ .unprepare = clk_pllv3_unprepare,
+ .is_prepared = clk_pllv3_is_prepared,
+ .recalc_rate = clk_pllv3_genericv2_recalc_rate,
+ .round_rate = clk_pllv3_round_rate,
+ .set_rate = clk_pllv3_genericv2_set_rate,
+};
+
static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -407,9 +442,9 @@ static const struct clk_ops clk_pllv3_enet_ops = {
.recalc_rate = clk_pllv3_enet_recalc_rate,
};
-struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
+struct clk_hw *__imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem *base,
- u32 div_mask)
+ u32 div_mask, u8 pwr_bit)
{
struct clk_pllv3 *pll;
const struct clk_ops *ops;
@@ -421,11 +456,21 @@ struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
if (!pll)
return ERR_PTR(-ENOMEM);
- pll->power_bit = BM_PLL_POWER;
+ pll->power_bit = pwr_bit;
+ pll->lock_bit = BM_PLL_LOCK;
pll->num_offset = PLL_NUM_OFFSET;
pll->denom_offset = PLL_DENOM_OFFSET;
switch (type) {
+ case IMX_PLLV3_GENERICV2:
+ pll->lock_bit = BM_PLL_LOCK_V2;
+ pll->powerup_set = true;
+ ops = &clk_pllv3_genericv2_ops;
+ break;
+ case IMX_PLLV3_SYSV2:
+ pll->lock_bit = BM_PLL_LOCK_V2;
+ pll->powerup_set = true;
+ fallthrough;
case IMX_PLLV3_SYS:
ops = &clk_pllv3_sys_ops;
break;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 5061a06468df..124f4a79537f 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -6,6 +6,8 @@
#include <linux/spinlock.h>
#include <linux/clk-provider.h>
+#define BM_PLL_POWER BIT(12)
+
extern spinlock_t imx_ccm_lock;
extern bool mcore_booted;
@@ -102,6 +104,9 @@ extern struct imx_fracn_gppll_clk imx_fracn_gppll;
to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
+#define imx_clk_hw_pllv3(type, name, parent_name, base, div_mask) \
+ __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
+
#define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
@@ -242,6 +247,8 @@ struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
enum imx_pllv3_type {
IMX_PLLV3_GENERIC,
+ IMX_PLLV3_GENERICV2,
+ IMX_PLLV3_SYSV2,
IMX_PLLV3_SYS,
IMX_PLLV3_USB,
IMX_PLLV3_USB_VF610,
@@ -253,8 +260,8 @@ enum imx_pllv3_type {
IMX_PLLV3_AV_IMX7,
};
-struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
- const char *parent_name, void __iomem *base, u32 div_mask);
+struct clk_hw *__imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base, u32 div_mask, u8 pwr_bit);
#define PLL_1416X_RATE(_rate, _m, _p, _s) \
{ \
--
2.36.1
Add the clock binding doc for i.MXRT1170.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
V1 -> V2:
- Change to GPL-2.0-only
V2 -> V3:
- Change to (GPL-2.0-only OR BSD-2-Clause)
V3 -> V4:
- Nothing done
V4 -> V5:
- Nothing done
V5 -> V6:
- Nothing done
---
include/dt-bindings/clock/imxrt1170-clock.h | 282 ++++++++++++++++++++
1 file changed, 282 insertions(+)
create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h
diff --git a/include/dt-bindings/clock/imxrt1170-clock.h b/include/dt-bindings/clock/imxrt1170-clock.h
new file mode 100644
index 000000000000..be0dd6089059
--- /dev/null
+++ b/include/dt-bindings/clock/imxrt1170-clock.h
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright(C) 2022
+ * Author(s): Jesse Taube <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMXRT1170_H
+#define __DT_BINDINGS_CLOCK_IMXRT1170_H
+
+#define IMXRT1170_CLK_DUMMY 0
+#define IMXRT1170_CLK_OSC 1
+#define IMXRT1170_CLK_OSC_32K 2
+#define IMXRT1170_CLK_RCOSC_16M 3
+#define IMXRT1170_CLK_RCOSC_48M 4
+#define IMXRT1170_CLK_RCOSC_48M_DIV2 5
+#define IMXRT1170_CLK_RCOSC_400M 6
+#define IMXRT1170_CLK_PLL_ARM_PRE 7
+#define IMXRT1170_CLK_PLL_ARM_BYPASS 8
+#define IMXRT1170_CLK_PLL_ARM_DIV 9
+#define IMXRT1170_CLK_PLL_ARM 10
+#define IMXRT1170_CLK_PLL_AUDIO 11
+#define IMXRT1170_CLK_PLL_VIDEO 12
+#define IMXRT1170_CLK_PLL1 13
+#define IMXRT1170_CLK_PLL1_DIV2 14
+#define IMXRT1170_CLK_PLL1_DIV5 15
+#define IMXRT1170_CLK_PLL2_PRE 16
+#define IMXRT1170_CLK_PLL2_BYPASS 17
+#define IMXRT1170_CLK_PLL2 18
+#define IMXRT1170_CLK_PLL2_PFD0 19
+#define IMXRT1170_CLK_PLL2_PFD1 20
+#define IMXRT1170_CLK_PLL2_PFD2 21
+#define IMXRT1170_CLK_PLL2_PFD3 22
+#define IMXRT1170_CLK_PLL3_PRE 23
+#define IMXRT1170_CLK_PLL3_BYPASS 24
+#define IMXRT1170_CLK_PLL3 25
+#define IMXRT1170_CLK_PLL3_DIV2_GATE 26
+#define IMXRT1170_CLK_PLL3_DIV2 27
+#define IMXRT1170_CLK_PLL3_PFD0 28
+#define IMXRT1170_CLK_PLL3_PFD1 29
+#define IMXRT1170_CLK_PLL3_PFD2 30
+#define IMXRT1170_CLK_PLL3_PFD3 31
+#define IMXRT1170_CLK_M7_SEL 32
+#define IMXRT1170_CLK_M7_GATE 33
+#define IMXRT1170_CLK_M7 34
+#define IMXRT1170_CLK_M4_SEL 35
+#define IMXRT1170_CLK_M4_GATE 36
+#define IMXRT1170_CLK_M4 37
+#define IMXRT1170_CLK_BUS_SEL 38
+#define IMXRT1170_CLK_BUS_GATE 39
+#define IMXRT1170_CLK_BUS 40
+#define IMXRT1170_CLK_BUS_LPSR_SEL 41
+#define IMXRT1170_CLK_BUS_LPSR_GATE 42
+#define IMXRT1170_CLK_BUS_LPSR 43
+#define IMXRT1170_CLK_SEMC_SEL 44
+#define IMXRT1170_CLK_SEMC_GATE 45
+#define IMXRT1170_CLK_SEMC 46
+#define IMXRT1170_CLK_CSSYS_SEL 47
+#define IMXRT1170_CLK_CSSYS_GATE 48
+#define IMXRT1170_CLK_CSSYS 49
+#define IMXRT1170_CLK_CSTRACE_SEL 50
+#define IMXRT1170_CLK_CSTRACE_GATE 51
+#define IMXRT1170_CLK_CSTRACE 52
+#define IMXRT1170_CLK_M4_SYSTICK_SEL 53
+#define IMXRT1170_CLK_M4_SYSTICK_GATE 54
+#define IMXRT1170_CLK_M4_SYSTICK 55
+#define IMXRT1170_CLK_M7_SYSTICK_SEL 56
+#define IMXRT1170_CLK_M7_SYSTICK_GATE 57
+#define IMXRT1170_CLK_M7_SYSTICK 58
+#define IMXRT1170_CLK_ADC1_SEL 59
+#define IMXRT1170_CLK_ADC1_GATE 60
+#define IMXRT1170_CLK_ADC1 61
+#define IMXRT1170_CLK_ADC2_SEL 62
+#define IMXRT1170_CLK_ADC2_GATE 63
+#define IMXRT1170_CLK_ADC2 64
+#define IMXRT1170_CLK_ACMP_SEL 65
+#define IMXRT1170_CLK_ACMP_GATE 66
+#define IMXRT1170_CLK_ACMP 67
+#define IMXRT1170_CLK_FLEXIO1_SEL 68
+#define IMXRT1170_CLK_FLEXIO1_GATE 69
+#define IMXRT1170_CLK_FLEXIO1 70
+#define IMXRT1170_CLK_FLEXIO2_SEL 71
+#define IMXRT1170_CLK_FLEXIO2_GATE 72
+#define IMXRT1170_CLK_FLEXIO2 73
+#define IMXRT1170_CLK_GPT1_SEL 74
+#define IMXRT1170_CLK_GPT1_GATE 75
+#define IMXRT1170_CLK_GPT1 76
+#define IMXRT1170_CLK_GPT2_SEL 77
+#define IMXRT1170_CLK_GPT2_GATE 78
+#define IMXRT1170_CLK_GPT2 79
+#define IMXRT1170_CLK_GPT3_SEL 80
+#define IMXRT1170_CLK_GPT3_GATE 81
+#define IMXRT1170_CLK_GPT3 82
+#define IMXRT1170_CLK_GPT4_SEL 83
+#define IMXRT1170_CLK_GPT4_GATE 84
+#define IMXRT1170_CLK_GPT4 85
+#define IMXRT1170_CLK_GPT5_SEL 86
+#define IMXRT1170_CLK_GPT5_GATE 87
+#define IMXRT1170_CLK_GPT5 88
+#define IMXRT1170_CLK_GPT6_SEL 89
+#define IMXRT1170_CLK_GPT6_GATE 90
+#define IMXRT1170_CLK_GPT6 91
+#define IMXRT1170_CLK_FLEXSPI1_SEL 92
+#define IMXRT1170_CLK_FLEXSPI1_GATE 93
+#define IMXRT1170_CLK_FLEXSPI1 94
+#define IMXRT1170_CLK_FLEXSPI2_SEL 95
+#define IMXRT1170_CLK_FLEXSPI2_GATE 96
+#define IMXRT1170_CLK_FLEXSPI2 97
+#define IMXRT1170_CLK_CAN1_SEL 98
+#define IMXRT1170_CLK_CAN1_GATE 99
+#define IMXRT1170_CLK_CAN1 100
+#define IMXRT1170_CLK_CAN2_SEL 101
+#define IMXRT1170_CLK_CAN2_GATE 102
+#define IMXRT1170_CLK_CAN2 103
+#define IMXRT1170_CLK_CAN3_SEL 104
+#define IMXRT1170_CLK_CAN3_GATE 105
+#define IMXRT1170_CLK_CAN3 106
+#define IMXRT1170_CLK_LPUART1_SEL 107
+#define IMXRT1170_CLK_LPUART1_GATE 108
+#define IMXRT1170_CLK_LPUART1 109
+#define IMXRT1170_CLK_LPUART2_SEL 110
+#define IMXRT1170_CLK_LPUART2_GATE 111
+#define IMXRT1170_CLK_LPUART2 112
+#define IMXRT1170_CLK_LPUART3_SEL 113
+#define IMXRT1170_CLK_LPUART3_GATE 114
+#define IMXRT1170_CLK_LPUART3 115
+#define IMXRT1170_CLK_LPUART4_SEL 116
+#define IMXRT1170_CLK_LPUART4_GATE 117
+#define IMXRT1170_CLK_LPUART4 118
+#define IMXRT1170_CLK_LPUART5_SEL 119
+#define IMXRT1170_CLK_LPUART5_GATE 120
+#define IMXRT1170_CLK_LPUART5 121
+#define IMXRT1170_CLK_LPUART6_SEL 122
+#define IMXRT1170_CLK_LPUART6_GATE 123
+#define IMXRT1170_CLK_LPUART6 124
+#define IMXRT1170_CLK_LPUART7_SEL 125
+#define IMXRT1170_CLK_LPUART7_GATE 126
+#define IMXRT1170_CLK_LPUART7 127
+#define IMXRT1170_CLK_LPUART8_SEL 128
+#define IMXRT1170_CLK_LPUART8_GATE 129
+#define IMXRT1170_CLK_LPUART8 130
+#define IMXRT1170_CLK_LPUART9_SEL 131
+#define IMXRT1170_CLK_LPUART9_GATE 132
+#define IMXRT1170_CLK_LPUART9 133
+#define IMXRT1170_CLK_LPUART10_SEL 134
+#define IMXRT1170_CLK_LPUART10_GATE 135
+#define IMXRT1170_CLK_LPUART10 136
+#define IMXRT1170_CLK_LPUART11_SEL 137
+#define IMXRT1170_CLK_LPUART11_GATE 138
+#define IMXRT1170_CLK_LPUART11 139
+#define IMXRT1170_CLK_LPUART12_SEL 140
+#define IMXRT1170_CLK_LPUART12_GATE 141
+#define IMXRT1170_CLK_LPUART12 142
+#define IMXRT1170_CLK_LPI2C1_SEL 143
+#define IMXRT1170_CLK_LPI2C1_GATE 144
+#define IMXRT1170_CLK_LPI2C1 145
+#define IMXRT1170_CLK_LPI2C2_SEL 146
+#define IMXRT1170_CLK_LPI2C2_GATE 147
+#define IMXRT1170_CLK_LPI2C2 148
+#define IMXRT1170_CLK_LPI2C3_SEL 149
+#define IMXRT1170_CLK_LPI2C3_GATE 150
+#define IMXRT1170_CLK_LPI2C3 151
+#define IMXRT1170_CLK_LPI2C4_SEL 152
+#define IMXRT1170_CLK_LPI2C4_GATE 153
+#define IMXRT1170_CLK_LPI2C4 154
+#define IMXRT1170_CLK_LPI2C5_SEL 155
+#define IMXRT1170_CLK_LPI2C5_GATE 156
+#define IMXRT1170_CLK_LPI2C5 157
+#define IMXRT1170_CLK_LPI2C6_SEL 158
+#define IMXRT1170_CLK_LPI2C6_GATE 159
+#define IMXRT1170_CLK_LPI2C6 160
+#define IMXRT1170_CLK_LPSPI1_SEL 161
+#define IMXRT1170_CLK_LPSPI1_GATE 162
+#define IMXRT1170_CLK_LPSPI1 163
+#define IMXRT1170_CLK_LPSPI2_SEL 164
+#define IMXRT1170_CLK_LPSPI2_GATE 165
+#define IMXRT1170_CLK_LPSPI2 166
+#define IMXRT1170_CLK_LPSPI3_SEL 167
+#define IMXRT1170_CLK_LPSPI3_GATE 168
+#define IMXRT1170_CLK_LPSPI3 169
+#define IMXRT1170_CLK_LPSPI4_SEL 170
+#define IMXRT1170_CLK_LPSPI4_GATE 171
+#define IMXRT1170_CLK_LPSPI4 172
+#define IMXRT1170_CLK_LPSPI5_SEL 173
+#define IMXRT1170_CLK_LPSPI5_GATE 174
+#define IMXRT1170_CLK_LPSPI5 175
+#define IMXRT1170_CLK_LPSPI6_SEL 176
+#define IMXRT1170_CLK_LPSPI6_GATE 177
+#define IMXRT1170_CLK_LPSPI6 178
+#define IMXRT1170_CLK_EMV1_SEL 179
+#define IMXRT1170_CLK_EMV1_GATE 180
+#define IMXRT1170_CLK_EMV1 181
+#define IMXRT1170_CLK_EMV2_SEL 182
+#define IMXRT1170_CLK_EMV2_GATE 183
+#define IMXRT1170_CLK_EMV2 184
+#define IMXRT1170_CLK_ENET1_SEL 185
+#define IMXRT1170_CLK_ENET1_GATE 186
+#define IMXRT1170_CLK_ENET1 187
+#define IMXRT1170_CLK_ENET2_SEL 188
+#define IMXRT1170_CLK_ENET2_GATE 189
+#define IMXRT1170_CLK_ENET2 190
+#define IMXRT1170_CLK_ENET_QOS_SEL 191
+#define IMXRT1170_CLK_ENET_QOS_GATE 192
+#define IMXRT1170_CLK_ENET_QOS 193
+#define IMXRT1170_CLK_ENET_25M_SEL 194
+#define IMXRT1170_CLK_ENET_25M_GATE 195
+#define IMXRT1170_CLK_ENET_25M 196
+#define IMXRT1170_CLK_ENET_TIMER1_SEL 197
+#define IMXRT1170_CLK_ENET_TIMER1_GATE 198
+#define IMXRT1170_CLK_ENET_TIMER1 199
+#define IMXRT1170_CLK_ENET_TIMER2_SEL 200
+#define IMXRT1170_CLK_ENET_TIMER2_GATE 201
+#define IMXRT1170_CLK_ENET_TIMER2 202
+#define IMXRT1170_CLK_ENET_TIMER3_SEL 203
+#define IMXRT1170_CLK_ENET_TIMER3_GATE 204
+#define IMXRT1170_CLK_ENET_TIMER3 205
+#define IMXRT1170_CLK_USDHC1_SEL 206
+#define IMXRT1170_CLK_USDHC1_GATE 207
+#define IMXRT1170_CLK_USDHC1 208
+#define IMXRT1170_CLK_USDHC2_SEL 209
+#define IMXRT1170_CLK_USDHC2_GATE 210
+#define IMXRT1170_CLK_USDHC2 211
+#define IMXRT1170_CLK_ASRC_SEL 212
+#define IMXRT1170_CLK_ASRC_GATE 213
+#define IMXRT1170_CLK_ASRC 214
+#define IMXRT1170_CLK_MQS_SEL 215
+#define IMXRT1170_CLK_MQS_GATE 216
+#define IMXRT1170_CLK_MQS 217
+#define IMXRT1170_CLK_MIC_SEL 218
+#define IMXRT1170_CLK_MIC_GATE 219
+#define IMXRT1170_CLK_MIC 220
+#define IMXRT1170_CLK_SPDIF_SEL 221
+#define IMXRT1170_CLK_SPDIF_GATE 222
+#define IMXRT1170_CLK_SPDIF 223
+#define IMXRT1170_CLK_SAI1_SEL 224
+#define IMXRT1170_CLK_SAI1_GATE 225
+#define IMXRT1170_CLK_SAI1 226
+#define IMXRT1170_CLK_SAI2_SEL 227
+#define IMXRT1170_CLK_SAI2_GATE 228
+#define IMXRT1170_CLK_SAI2 229
+#define IMXRT1170_CLK_SAI3_SEL 230
+#define IMXRT1170_CLK_SAI3_GATE 231
+#define IMXRT1170_CLK_SAI3 232
+#define IMXRT1170_CLK_SAI4_SEL 233
+#define IMXRT1170_CLK_SAI4_GATE 234
+#define IMXRT1170_CLK_SAI4 235
+#define IMXRT1170_CLK_GC355_SEL 236
+#define IMXRT1170_CLK_GC355_GATE 237
+#define IMXRT1170_CLK_GC355 238
+#define IMXRT1170_CLK_LCDIF_SEL 239
+#define IMXRT1170_CLK_LCDIF_GATE 240
+#define IMXRT1170_CLK_LCDIF 241
+#define IMXRT1170_CLK_LCDIFV2_SEL 242
+#define IMXRT1170_CLK_LCDIFV2_GATE 243
+#define IMXRT1170_CLK_LCDIFV2 244
+#define IMXRT1170_CLK_MIPI_REF_SEL 245
+#define IMXRT1170_CLK_MIPI_REF_GATE 246
+#define IMXRT1170_CLK_MIPI_REF 247
+#define IMXRT1170_CLK_MIPI_ESC_SEL 248
+#define IMXRT1170_CLK_MIPI_ESC_GATE 249
+#define IMXRT1170_CLK_MIPI_ESC 250
+#define IMXRT1170_CLK_CSI2_SEL 251
+#define IMXRT1170_CLK_CSI2_GATE 252
+#define IMXRT1170_CLK_CSI2 253
+#define IMXRT1170_CLK_CSI2_ESC_SEL 254
+#define IMXRT1170_CLK_CSI2_ESC_GATE 255
+#define IMXRT1170_CLK_CSI2_ESC 256
+#define IMXRT1170_CLK_CSI2_UI_SEL 257
+#define IMXRT1170_CLK_CSI2_UI_GATE 258
+#define IMXRT1170_CLK_CSI2_UI 259
+#define IMXRT1170_CLK_CSI_SEL 260
+#define IMXRT1170_CLK_CSI_GATE 261
+#define IMXRT1170_CLK_CSI 262
+#define IMXRT1170_CLK_CKO1_SEL 263
+#define IMXRT1170_CLK_CKO1_GATE 264
+#define IMXRT1170_CLK_CKO1 265
+#define IMXRT1170_CLK_CKO2_SEL 266
+#define IMXRT1170_CLK_CKO2_GATE 267
+#define IMXRT1170_CLK_CKO2 268
+#define IMXRT1170_CLK_USB 269
+#define IMXRT1170_CLK_END 270
+
+#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */
--
2.36.1
Add i.MXRT1170 pinctrl, clocks imxrt_defconfig.
Add support for CHIPIDEA usb host and usb gadget and other usb drives.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Remove USB_CONFIGFS*
V2 -> V3:
- Nothing done
V3 -> V4:
- Nothing done
V4 -> V5:
- Nothing done
V5 -> V6:
- Nothing done
---
arch/arm/configs/imxrt_defconfig | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/configs/imxrt_defconfig b/arch/arm/configs/imxrt_defconfig
index 52dba3762996..b3a013686255 100644
--- a/arch/arm/configs/imxrt_defconfig
+++ b/arch/arm/configs/imxrt_defconfig
@@ -17,7 +17,23 @@ CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_PINCTRL_IMXRT1050=y
+CONFIG_PINCTRL_IMXRT1170=y
CONFIG_GPIO_MXC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_MASS_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
@@ -25,6 +41,7 @@ CONFIG_MMC_SDHCI_ESDHC_IMX=y
CONFIG_DMADEVICES=y
CONFIG_FSL_EDMA=y
CONFIG_CLK_IMXRT1050=y
+CONFIG_CLK_IMXRT1170=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
--
2.36.1
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and M4 core.
The EVK provides 64 MB SDRAM, 128 MB Quad SPI flash, Micro SD card socket,
two USB 2.0 OTG, and two Ethernet ports.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Add ipg clock for gpt
- Change mmc, uart and gpt compatibles
- Group fsl,pins for dtbs_check
- Remove underscore from pinctrl_usbotg1_id
- Remove unused fsl,mux_mask
- Rename ccm to clock-controller
V2 -> V3:
- Nothing done
V3 -> V4:
- Nothing done
V4 -> V5:
- Nothing done
V5 -> V6:
- Nothing done
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imxrt1170-evk.dts | 110 +++++++++++
arch/arm/boot/dts/imxrt1170.dtsi | 276 ++++++++++++++++++++++++++++
3 files changed, 388 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/boot/dts/imxrt1170.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 05d8aef6e5d2..97dc0b53408f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -784,7 +784,8 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_IMXRT) += \
- imxrt1050-evk.dtb
+ imxrt1050-evk.dtb \
+ imxrt1170-evk.dtb
dtb-$(CONFIG_SOC_LAN966) += \
lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
lan966x-kontron-kswitch-d10-mmt-8g.dtb \
diff --git a/arch/arm/boot/dts/imxrt1170-evk.dts b/arch/arm/boot/dts/imxrt1170-evk.dts
new file mode 100644
index 000000000000..cac74d86168f
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1170-evk.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <[email protected]>
+ */
+
+/dts-v1/;
+#include "imxrt1170.dtsi"
+#include "imxrt1170-pinfunc.h"
+
+/ {
+ model = "NXP imxrt1170-evk board";
+ compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
+ gpio7 = &gpio8;
+ gpio8 = &gpio9;
+ gpio9 = &gpio10;
+ gpio10 = &gpio11;
+ gpio11 = &gpio12;
+ gpio12 = &gpio13;
+ mmc0 = &usdhc1;
+ serial0 = &lpuart1;
+ usbphy0 = &usbphy1;
+ };
+
+ memory@20240000 {
+ device_type = "memory";
+ reg = <0x20240000 0xf0000>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x4000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio9 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <IOMUXC_GPIO_AD_24_LPUART1_TXD 0xf1>,
+ <IOMUXC_GPIO_AD_25_LPUART1_RXD 0xf1>;
+ };
+
+ pinctrl_pwm0: pwm0grp {
+ fsl,pins = <IOMUXC_GPIO_AD_11_USB_OTG1_OC 0xf1>;
+ };
+
+ pinctrl_usbotg1_id: usbotg1idgrp {
+ fsl,pins = <IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0xf1>;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x1B000>,
+ <IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0xB069>,
+ <IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x17061>,
+ <IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x17061>,
+ <IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x17061>,
+ <IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x17061>,
+ <IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x17061>,
+ <IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x17061>;
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
+ status = "okay";
+ broken-cd;
+};
diff --git a/arch/arm/boot/dts/imxrt1170.dtsi b/arch/arm/boot/dts/imxrt1170.dtsi
new file mode 100644
index 000000000000..64c130933ee8
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1170.dtsi
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <[email protected]>
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1170-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x40000>;
+ no-map;
+ linux,dma-default;
+ };
+ };
+
+ clocks {
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ rcosc16M: rcosc16M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ };
+
+ osc32k: osc32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ osc3M: osc3M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3000000>;
+ };
+ };
+
+ soc {
+ anatop: anatop@40c84000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x40c84000 0x4000>;
+ };
+
+ clks: clock-controller@40cc0000 {
+ compatible = "fsl,imxrt1170-ccm";
+ reg = <0x40cc0000 0x4000>;
+ clocks = <&osc>, <&rcosc16M>, <&osc32k>;
+ clock-names = "osc", "rcosc16M", "osc32k";
+ #clock-cells = <1>;
+ };
+
+ edma1: dma-controller@40070000 {
+ #dma-cells = <2>;
+ compatible = "fsl,imx7ulp-edma";
+ reg = <0x40070000 0x4000>,
+ <0x40074000 0x4000>;
+ dma-channels = <32>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
+ clock-names = "dma", "dmamux0";
+ clocks = <&clks IMXRT1170_CLK_BUS>,
+ <&clks IMXRT1170_CLK_M4>;
+ };
+
+ gpio1: gpio@4012c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x4012c000 0x4000>;
+ interrupts = <100>, <101>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@40130000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40130000 0x4000>;
+ interrupts = <102>, <103>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@40134000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40134000 0x4000>;
+ interrupts = <104>, <105>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@40138000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40138000 0x4000>;
+ interrupts = <106>, <107>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@4013c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x4013c000 0x4000>;
+ interrupts = <108>, <109>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@40140000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40140000 0x4000>;
+ interrupts = <61>, <62>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio7: gpio@40c5c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c5c000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio8: gpio@40c60000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c60000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio9: gpio@40c64000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c64000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio10: gpio@40c68000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c68000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio11: gpio@40c6c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c6c000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio12: gpio@40c70000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c70000 0x4000>;
+ interrupts = <61>, <62>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio13: gpio@40ca0000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40ca0000 0x4000>;
+ interrupts = <93>, <93>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpt: timer@400ec000 {
+ compatible = "fsl,imxrt1170-gpt", "fsl,imx6dl-gpt";
+ reg = <0x400ec000 0x4000>;
+ interrupts = <119>;
+ clocks = <&osc3M>, <&osc3M>;
+ clock-names = "ipg", "per";
+ };
+
+ iomuxc: iomuxc@400e8000 {
+ compatible = "fsl,imxrt1170-iomuxc";
+ reg = <0x400e8000 0x4000>;
+ };
+
+ lpuart1: serial@4007c000 {
+ compatible = "fsl,imxrt1170-lpuart", "fsl,imxrt1050-lpuart";
+ reg = <0x4007c000 0x4000>;
+ interrupts = <20>;
+ clocks = <&clks IMXRT1170_CLK_LPUART1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ usdhc1: mmc@40418000 {
+ compatible = "fsl,imxrt1170-usdhc", "fsl,imxrt1050-usdhc";
+ reg = <0x40418000 0x10000>;
+ interrupts = <133>;
+ clocks = <&clks IMXRT1170_CLK_BUS>,
+ <&clks IMXRT1170_CLK_BUS>,
+ <&clks IMXRT1170_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,wp-controller;
+ no-1-8-v;
+ max-frequency = <4000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@40430200 {
+ compatible = "fsl,imx7ulp-usbmisc";
+ #index-cells = <1>;
+ reg = <0x40430200 0x200>;
+ };
+
+ usbotg1: usb@40430000 {
+ compatible = "fsl,imx7ulp-usb";
+ reg = <0x40430000 0x200>;
+ interrupts = <136>;
+ clocks = <&clks IMXRT1170_CLK_USB>;
+ phys = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ status = "disabled";
+ };
+
+ usbphy1: usb-phy@40434000 {
+ compatible = "fsl,imx7ulp-usbphy";
+ reg = <0x40434000 0x1000>;
+ interrupts = <90>;
+ clocks = <&clks IMXRT1170_CLK_USB>;
+ #phy-cells = <0>;
+ };
+
+ };
+};
--
2.36.1
Add clock driver support for i.MXRT1170.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Add slab.h and clock-provider.h
- Add spaces in `root_clocks`
- Expand and sort macro
- Move `clk_hw` structs to `clocks_probe`
- Remove of_irq.h
- Remove unused code/comments
V2 -> V3:
- Expand root_clocks names array
- Remove root_clock_names enum
V3 -> V4:
- Nothing done
V4 -> V5:
- Use __imx_clk_hw_pllv3 to change power bit
V5 -> V6:
- Nothing done
---
drivers/clk/imx/Kconfig | 7 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imxrt1170.c | 749 ++++++++++++++++++++++++++++++++
3 files changed, 757 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 25785ec9c276..704a7777af4f 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -119,3 +119,10 @@ config CLK_IMXRT1050
select MXC_CLK
help
Build the driver for i.MXRT1050 CCM Clock Driver
+
+config CLK_IMXRT1170
+ tristate "IMXRT1170 CCM Clock Driver"
+ depends on SOC_IMXRT
+ select MXC_CLK
+ help
+ Build the driver for i.MXRT1170 CCM Clock Driver
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 88b9b9285d22..d607a6d8138a 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -52,4 +52,5 @@ obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o
obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o
obj-$(CONFIG_CLK_IMXRT1050) += clk-imxrt1050.o
+obj-$(CONFIG_CLK_IMXRT1170) += clk-imxrt1170.o
obj-$(CONFIG_CLK_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
new file mode 100644
index 000000000000..71d9aacf9751
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -0,0 +1,749 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s):
+ * Jesse Taube <[email protected]>
+ */
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/imxrt1170-clock.h>
+
+#include "clk.h"
+
+#define CLOCK_MUX_DEFAULT "rcosc48M_div2", "osc", "rcosc400M", "rcosc16M"
+
+#define LPCG_GATE(gate) (0x6000 + (gate * 0x20))
+
+static const char * const m7_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll_arm", "pll1_sys", "pll3_sys", "pll_video" };
+static const char * const m4_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll2_sys", "pll1_div5" };
+static const char * const bus_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_sys", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const bus_lpsr_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll2_sys", "pll1_div5" };
+static const char * const semc_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div5", "pll2_sys", "pll2_pfd1", "pll3_pfd0" };
+static const char * const cssys_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const cstrace_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_pfd1", "pll2_sys" };
+static const char * const m4_systick_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll2_pfd0", "pll1_div5" };
+static const char * const m7_systick_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_sys", "pll3_div2", "pll1_div5", "pll2_pfd0" };
+static const char * const adc1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const adc2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const acmp_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_sys", "pll1_div5", "pll_audio", "pll2_pfd3" };
+static const char * const flexio1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const flexio2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const gpt1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" };
+static const char * const gpt2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll_audio", "pll_video" };
+static const char * const gpt3_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll_audio", "pll_video" };
+static const char * const gpt4_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" };
+static const char * const gpt5_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" };
+static const char * const gpt6_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" };
+static const char * const flexspi1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd0", "pll2_sys", "pll2_pfd2", "pll3_sys" };
+static const char * const flexspi2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd0", "pll2_sys", "pll2_pfd2", "pll3_sys" };
+static const char * const can1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const can2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const can3_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" };
+static const char * const lpuart1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart3_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart4_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart5_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart6_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart7_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart8_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart9_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart10_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpuart11_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" };
+static const char * const lpuart12_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" };
+static const char * const lpi2c1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpi2c2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpi2c3_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpi2c4_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpi2c5_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" };
+static const char * const lpi2c6_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" };
+static const char * const lpspi1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpspi2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpspi3_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpspi4_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const lpspi5_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll3_pfd2", "pll1_div5" };
+static const char * const lpspi6_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll3_pfd2", "pll1_div5" };
+static const char * const emv1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const emv2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" };
+static const char * const enet1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" };
+static const char * const enet2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" };
+static const char * const enet_qos_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" };
+static const char * const enet_25m_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" };
+static const char * const enet_timer1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" };
+static const char * const enet_timer2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" };
+static const char * const enet_timer3_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" };
+static const char * const usdhc1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm" };
+static const char * const usdhc2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm" };
+static const char * const asrc_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div5", "pll3_div2", "pll_audio", "pll2_pfd3" };
+static const char * const mqs_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll1_div5", "pll3_div2", "pll_audio", "pll2_pfd3" };
+static const char * const mic_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll_audio", "pll1_div5" };
+static const char * const spdif_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll_audio", "pll3_sys", "pll3_pfd2", "pll2_pfd3" };
+static const char * const sai1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll_audio", "pll3_pfd2", "pll1_div5", "pll2_pfd3" };
+static const char * const sai2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll_audio", "pll3_pfd2", "pll1_div5", "pll2_pfd3" };
+static const char * const sai3_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll_audio", "pll3_pfd2", "pll1_div5", "pll2_pfd3" };
+static const char * const sai4_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll3_pfd3", "pll3_sys", "pll_audio", "pll1_div5" };
+static const char * const gc355_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_sys", "pll2_pfd1", "pll3_sys", "pll_video" };
+static const char * const lcdif_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_sys", "pll2_pfd2", "pll3_pfd0", "pll_video" };
+static const char * const lcdifv2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_sys", "pll2_pfd2", "pll3_pfd0", "pll_video" };
+static const char * const mipi_ref_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_sys", "pll2_pfd0", "pll3_pfd0", "pll_video" };
+static const char * const mipi_esc_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_sys", "pll2_pfd0", "pll3_pfd0", "pll_video" };
+static const char * const csi2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_pfd2", "pll3_sys", "pll2_pfd0", "pll_video" };
+static const char * const csi2_esc_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_pfd2", "pll3_sys", "pll2_pfd0", "pll_video" };
+static const char * const csi2_ui_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_pfd2", "pll3_sys", "pll2_pfd0", "pll_video" };
+static const char * const csi_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_pfd2", "pll3_sys", "pll3_pfd1", "pll_video" };
+static const char * const cko1_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_pfd2", "pll2_sys", "pll3_pfd1", "pll1_div5" };
+static const char * const cko2_sels[] = { CLOCK_MUX_DEFAULT,
+ "pll2_pfd3", "rcosc48M", "pll3_pfd1", "pll_audio"};
+
+static const char * const pll_arm_mux[] = {"pll_arm_pre", "osc"};
+static const char * const pll3_mux[] = {"pll3_pre", "osc"};
+static const char * const pll2_mux[] = {"pll2_pre", "osc"};
+
+static const struct clk_div_table post_div_table[] = {
+ { .val = 3, .div = 1, },
+ { .val = 2, .div = 8, },
+ { .val = 1, .div = 4, },
+ { .val = 0, .div = 2, },
+ { }
+};
+
+static int imxrt1170_clocks_probe(struct platform_device *pdev)
+{
+ void __iomem *ccm_base;
+ void __iomem *pll_base;
+ struct clk_hw **hws;
+ struct clk_hw_onecell_data *clk_hw_data;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *anp;
+ int ret;
+
+ clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
+ IMXRT1170_CLK_END), GFP_KERNEL);
+ if (WARN_ON(!clk_hw_data))
+ return -ENOMEM;
+
+ clk_hw_data->num = IMXRT1170_CLK_END;
+ hws = clk_hw_data->hws;
+
+ hws[IMXRT1170_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc");
+ hws[IMXRT1170_CLK_RCOSC_16M] = imx_obtain_fixed_clk_hw(np, "rcosc16M");
+ hws[IMXRT1170_CLK_OSC_32K] = imx_obtain_fixed_clk_hw(np, "osc32k");
+
+ hws[IMXRT1170_CLK_RCOSC_48M] = imx_clk_hw_fixed_factor("rcosc48M", "rcosc16M", 3, 1);
+ hws[IMXRT1170_CLK_RCOSC_400M] = imx_clk_hw_fixed_factor("rcosc400M", "rcosc16M", 25, 1);
+ hws[IMXRT1170_CLK_RCOSC_48M_DIV2] = imx_clk_hw_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2);
+
+ anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop");
+ pll_base = of_iomap(anp, 0);
+ of_node_put(anp);
+ if (WARN_ON(!pll_base))
+ return -ENOMEM;
+
+ /* Anatop clocks */
+ hws[IMXRT1170_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL);
+
+ hws[IMXRT1170_CLK_PLL_ARM_PRE] = __imx_clk_hw_pllv3(IMX_PLLV3_SYSV2, "pll_arm_pre", "osc",
+ pll_base + 0x200, 0xff, 13);
+ hws[IMXRT1170_CLK_PLL_ARM_BYPASS] = imx_clk_hw_mux("pll_arm_bypass", pll_base + 0x200, 17,
+ 1, pll_arm_mux, 2);
+ hws[IMXRT1170_CLK_PLL_ARM_DIV] = clk_hw_register_divider_table(NULL, "pll_arm_div",
+ "pll_arm_bypass", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ pll_base + 0x200, 15, 2, 0, post_div_table, &imx_ccm_lock);
+ hws[IMXRT1170_CLK_PLL_ARM] = imx_clk_hw_gate("pll_arm", "pll_arm_div", pll_base + 0x200, 14);
+
+ hws[IMXRT1170_CLK_PLL3_PRE] = __imx_clk_hw_pllv3(IMX_PLLV3_GENERICV2, "pll3_pre", "osc",
+ pll_base + 0x210, 0x1, 21);
+ hws[IMXRT1170_CLK_PLL3_BYPASS] = imx_clk_hw_mux("pll3_bypass",
+ pll_base + 0x210, 16, 1, pll3_mux, 2);
+ hws[IMXRT1170_CLK_PLL3] = imx_clk_hw_gate("pll3_sys", "pll3_bypass", pll_base + 0x210, 13);
+
+ hws[IMXRT1170_CLK_PLL2_PRE] = __imx_clk_hw_pllv3(IMX_PLLV3_GENERICV2, "pll2_pre", "osc",
+ pll_base + 0x240, 0x1, 23);
+ hws[IMXRT1170_CLK_PLL2_BYPASS] = imx_clk_hw_mux("pll2_bypass",
+ pll_base + 0x240, 16, 1, pll2_mux, 2);
+ hws[IMXRT1170_CLK_PLL2] = imx_clk_hw_gate("pll2_sys", "pll2_bypass", pll_base + 0x240, 13);
+
+ hws[IMXRT1170_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0", "pll3_sys", pll_base + 0x230, 0);
+ hws[IMXRT1170_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1", "pll3_sys", pll_base + 0x230, 1);
+ hws[IMXRT1170_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2", "pll3_sys", pll_base + 0x230, 2);
+ hws[IMXRT1170_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3", "pll3_sys", pll_base + 0x230, 3);
+ hws[IMXRT1170_CLK_PLL3_DIV2_GATE] = imx_clk_hw_fixed_factor("pll3_div2_gate", "pll3_sys", 1, 2);
+ hws[IMXRT1170_CLK_PLL3_DIV2] = imx_clk_hw_gate("pll3_div2", "pll3_sys", pll_base + 0x210, 3);
+
+ hws[IMXRT1170_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0", "pll2_sys", pll_base + 0x270, 0);
+ hws[IMXRT1170_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1", "pll2_sys", pll_base + 0x270, 1);
+ hws[IMXRT1170_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2", "pll2_sys", pll_base + 0x270, 2);
+ hws[IMXRT1170_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3", "pll2_sys", pll_base + 0x270, 3);
+
+ /* CCM clocks */
+ ccm_base = devm_platform_ioremap_resource(pdev, 0);
+ if (WARN_ON(IS_ERR(ccm_base)))
+ return PTR_ERR(ccm_base);
+
+ hws[IMXRT1170_CLK_M7_SEL] = imx_clk_hw_mux("m7_sel", ccm_base + (1 * 0x80),
+ 8, 3, m7_sels, 8);
+ hws[IMXRT1170_CLK_M4_SEL] = imx_clk_hw_mux("m4_sel", ccm_base + (2 * 0x80),
+ 8, 3, m4_sels, 8);
+ hws[IMXRT1170_CLK_BUS_SEL] = imx_clk_hw_mux("bus_sel", ccm_base + (3 * 0x80),
+ 8, 3, bus_sels, 8);
+ hws[IMXRT1170_CLK_BUS_LPSR_SEL] = imx_clk_hw_mux("bus_lpsr_sel", ccm_base + (4 * 0x80),
+ 8, 3, bus_lpsr_sels, 8);
+ hws[IMXRT1170_CLK_SEMC_SEL] = imx_clk_hw_mux("semc_sel", ccm_base + (5 * 0x80),
+ 8, 3, semc_sels, 8);
+ hws[IMXRT1170_CLK_CSSYS_SEL] = imx_clk_hw_mux("cssys_sel", ccm_base + (6 * 0x80),
+ 8, 3, cssys_sels, 8);
+ hws[IMXRT1170_CLK_CSTRACE_SEL] = imx_clk_hw_mux("cstrace_sel", ccm_base + (7 * 0x80),
+ 8, 3, cstrace_sels, 8);
+ hws[IMXRT1170_CLK_M4_SYSTICK_SEL] = imx_clk_hw_mux("m4_systick_sel", ccm_base + (8 * 0x80),
+ 8, 3, m4_systick_sels, 8);
+ hws[IMXRT1170_CLK_M7_SYSTICK_SEL] = imx_clk_hw_mux("m7_systick_sel", ccm_base + (9 * 0x80),
+ 8, 3, m7_systick_sels, 8);
+ hws[IMXRT1170_CLK_ADC1_SEL] = imx_clk_hw_mux("adc1_sel", ccm_base + (10 * 0x80),
+ 8, 3, adc1_sels, 8);
+ hws[IMXRT1170_CLK_ADC2_SEL] = imx_clk_hw_mux("adc2_sel", ccm_base + (11 * 0x80),
+ 8, 3, adc2_sels, 8);
+ hws[IMXRT1170_CLK_ACMP_SEL] = imx_clk_hw_mux("acmp_sel", ccm_base + (12 * 0x80),
+ 8, 3, acmp_sels, 8);
+ hws[IMXRT1170_CLK_FLEXIO1_SEL] = imx_clk_hw_mux("flexio1_sel", ccm_base + (13 * 0x80),
+ 8, 3, flexio1_sels, 8);
+ hws[IMXRT1170_CLK_FLEXIO2_SEL] = imx_clk_hw_mux("flexio2_sel", ccm_base + (14 * 0x80),
+ 8, 3, flexio2_sels, 8);
+ hws[IMXRT1170_CLK_GPT1_SEL] = imx_clk_hw_mux("gpt1_sel", ccm_base + (15 * 0x80),
+ 8, 3, gpt1_sels, 8);
+ hws[IMXRT1170_CLK_GPT2_SEL] = imx_clk_hw_mux("gpt2_sel", ccm_base + (16 * 0x80),
+ 8, 3, gpt2_sels, 8);
+ hws[IMXRT1170_CLK_GPT3_SEL] = imx_clk_hw_mux("gpt3_sel", ccm_base + (17 * 0x80),
+ 8, 3, gpt3_sels, 8);
+ hws[IMXRT1170_CLK_GPT4_SEL] = imx_clk_hw_mux("gpt4_sel", ccm_base + (18 * 0x80),
+ 8, 3, gpt4_sels, 8);
+ hws[IMXRT1170_CLK_GPT5_SEL] = imx_clk_hw_mux("gpt5_sel", ccm_base + (19 * 0x80),
+ 8, 3, gpt5_sels, 8);
+ hws[IMXRT1170_CLK_GPT6_SEL] = imx_clk_hw_mux("gpt6_sel", ccm_base + (20 * 0x80),
+ 8, 3, gpt6_sels, 8);
+ hws[IMXRT1170_CLK_FLEXSPI1_SEL] = imx_clk_hw_mux("flexspi1_sel", ccm_base + (21 * 0x80),
+ 8, 3, flexspi1_sels, 8);
+ hws[IMXRT1170_CLK_FLEXSPI2_SEL] = imx_clk_hw_mux("flexspi2_sel", ccm_base + (22 * 0x80),
+ 8, 3, flexspi2_sels, 8);
+ hws[IMXRT1170_CLK_CAN1_SEL] = imx_clk_hw_mux("can1_sel", ccm_base + (23 * 0x80),
+ 8, 3, can1_sels, 8);
+ hws[IMXRT1170_CLK_CAN2_SEL] = imx_clk_hw_mux("can2_sel", ccm_base + (24 * 0x80),
+ 8, 3, can2_sels, 8);
+ hws[IMXRT1170_CLK_CAN3_SEL] = imx_clk_hw_mux("can3_sel", ccm_base + (25 * 0x80),
+ 8, 3, can3_sels, 8);
+ hws[IMXRT1170_CLK_LPUART1_SEL] = imx_clk_hw_mux("lpuart1_sel", ccm_base + (26 * 0x80),
+ 8, 3, lpuart1_sels, 8);
+ hws[IMXRT1170_CLK_LPUART2_SEL] = imx_clk_hw_mux("lpuart2_sel", ccm_base + (27 * 0x80),
+ 8, 3, lpuart2_sels, 8);
+ hws[IMXRT1170_CLK_LPUART3_SEL] = imx_clk_hw_mux("lpuart3_sel", ccm_base + (28 * 0x80),
+ 8, 3, lpuart3_sels, 8);
+ hws[IMXRT1170_CLK_LPUART4_SEL] = imx_clk_hw_mux("lpuart4_sel", ccm_base + (29 * 0x80),
+ 8, 3, lpuart4_sels, 8);
+ hws[IMXRT1170_CLK_LPUART5_SEL] = imx_clk_hw_mux("lpuart5_sel", ccm_base + (30 * 0x80),
+ 8, 3, lpuart5_sels, 8);
+ hws[IMXRT1170_CLK_LPUART6_SEL] = imx_clk_hw_mux("lpuart6_sel", ccm_base + (31 * 0x80),
+ 8, 3, lpuart6_sels, 8);
+ hws[IMXRT1170_CLK_LPUART7_SEL] = imx_clk_hw_mux("lpuart7_sel", ccm_base + (32 * 0x80),
+ 8, 3, lpuart7_sels, 8);
+ hws[IMXRT1170_CLK_LPUART8_SEL] = imx_clk_hw_mux("lpuart8_sel", ccm_base + (33 * 0x80),
+ 8, 3, lpuart8_sels, 8);
+ hws[IMXRT1170_CLK_LPUART9_SEL] = imx_clk_hw_mux("lpuart9_sel", ccm_base + (34 * 0x80),
+ 8, 3, lpuart9_sels, 8);
+ hws[IMXRT1170_CLK_LPUART10_SEL] = imx_clk_hw_mux("lpuart10_sel", ccm_base + (35 * 0x80),
+ 8, 3, lpuart10_sels, 8);
+ hws[IMXRT1170_CLK_LPUART11_SEL] = imx_clk_hw_mux("lpuart11_sel", ccm_base + (36 * 0x80),
+ 8, 3, lpuart11_sels, 8);
+ hws[IMXRT1170_CLK_LPUART12_SEL] = imx_clk_hw_mux("lpuart12_sel", ccm_base + (37 * 0x80),
+ 8, 3, lpuart12_sels, 8);
+ hws[IMXRT1170_CLK_LPI2C1_SEL] = imx_clk_hw_mux("lpi2c1_sel", ccm_base + (38 * 0x80),
+ 8, 3, lpi2c1_sels, 8);
+ hws[IMXRT1170_CLK_LPI2C2_SEL] = imx_clk_hw_mux("lpi2c2_sel", ccm_base + (39 * 0x80),
+ 8, 3, lpi2c2_sels, 8);
+ hws[IMXRT1170_CLK_LPI2C3_SEL] = imx_clk_hw_mux("lpi2c3_sel", ccm_base + (40 * 0x80),
+ 8, 3, lpi2c3_sels, 8);
+ hws[IMXRT1170_CLK_LPI2C4_SEL] = imx_clk_hw_mux("lpi2c4_sel", ccm_base + (41 * 0x80),
+ 8, 3, lpi2c4_sels, 8);
+ hws[IMXRT1170_CLK_LPI2C5_SEL] = imx_clk_hw_mux("lpi2c5_sel", ccm_base + (42 * 0x80),
+ 8, 3, lpi2c5_sels, 8);
+ hws[IMXRT1170_CLK_LPI2C6_SEL] = imx_clk_hw_mux("lpi2c6_sel", ccm_base + (43 * 0x80),
+ 8, 3, lpi2c6_sels, 8);
+ hws[IMXRT1170_CLK_LPSPI1_SEL] = imx_clk_hw_mux("lpspi1_sel", ccm_base + (44 * 0x80),
+ 8, 3, lpspi1_sels, 8);
+ hws[IMXRT1170_CLK_LPSPI2_SEL] = imx_clk_hw_mux("lpspi2_sel", ccm_base + (45 * 0x80),
+ 8, 3, lpspi2_sels, 8);
+ hws[IMXRT1170_CLK_LPSPI3_SEL] = imx_clk_hw_mux("lpspi3_sel", ccm_base + (46 * 0x80),
+ 8, 3, lpspi3_sels, 8);
+ hws[IMXRT1170_CLK_LPSPI4_SEL] = imx_clk_hw_mux("lpspi4_sel", ccm_base + (47 * 0x80),
+ 8, 3, lpspi4_sels, 8);
+ hws[IMXRT1170_CLK_LPSPI5_SEL] = imx_clk_hw_mux("lpspi5_sel", ccm_base + (48 * 0x80),
+ 8, 3, lpspi5_sels, 8);
+ hws[IMXRT1170_CLK_LPSPI6_SEL] = imx_clk_hw_mux("lpspi6_sel", ccm_base + (49 * 0x80),
+ 8, 3, lpspi6_sels, 8);
+ hws[IMXRT1170_CLK_EMV1_SEL] = imx_clk_hw_mux("emv1_sel", ccm_base + (50 * 0x80),
+ 8, 3, emv1_sels, 8);
+ hws[IMXRT1170_CLK_EMV2_SEL] = imx_clk_hw_mux("emv2_sel", ccm_base + (51 * 0x80),
+ 8, 3, emv2_sels, 8);
+ hws[IMXRT1170_CLK_ENET1_SEL] = imx_clk_hw_mux("enet1_sel", ccm_base + (52 * 0x80),
+ 8, 3, enet1_sels, 8);
+ hws[IMXRT1170_CLK_ENET2_SEL] = imx_clk_hw_mux("enet2_sel", ccm_base + (53 * 0x80),
+ 8, 3, enet2_sels, 8);
+ hws[IMXRT1170_CLK_ENET_QOS_SEL] = imx_clk_hw_mux("enet_qos_sel", ccm_base + (54 * 0x80),
+ 8, 3, enet_qos_sels, 8);
+ hws[IMXRT1170_CLK_ENET_25M_SEL] = imx_clk_hw_mux("enet_25m_sel", ccm_base + (55 * 0x80),
+ 8, 3, enet_25m_sels, 8);
+ hws[IMXRT1170_CLK_ENET_TIMER1_SEL] = imx_clk_hw_mux("enet_timer1_sel",
+ ccm_base + (56 * 0x80), 8, 3,
+ enet_timer1_sels, 8);
+ hws[IMXRT1170_CLK_ENET_TIMER2_SEL] = imx_clk_hw_mux("enet_timer2_sel",
+ ccm_base + (57 * 0x80), 8, 3,
+ enet_timer2_sels, 8);
+ hws[IMXRT1170_CLK_ENET_TIMER3_SEL] = imx_clk_hw_mux("enet_timer3_sel",
+ ccm_base + (58 * 0x80), 8, 3,
+ enet_timer3_sels, 8);
+ hws[IMXRT1170_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + (59 * 0x80),
+ 8, 3, usdhc1_sels, 8);
+ hws[IMXRT1170_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + (60 * 0x80),
+ 8, 3, usdhc2_sels, 8);
+ hws[IMXRT1170_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", ccm_base + (61 * 0x80),
+ 8, 3, asrc_sels, 8);
+ hws[IMXRT1170_CLK_MQS_SEL] = imx_clk_hw_mux("mqs_sel", ccm_base + (62 * 0x80),
+ 8, 3, mqs_sels, 8);
+ hws[IMXRT1170_CLK_MIC_SEL] = imx_clk_hw_mux("mic_sel", ccm_base + (63 * 0x80),
+ 8, 3, mic_sels, 8);
+ hws[IMXRT1170_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", ccm_base + (64 * 0x80),
+ 8, 3, spdif_sels, 8);
+ hws[IMXRT1170_CLK_SAI1_SEL] = imx_clk_hw_mux("sai1_sel", ccm_base + (65 * 0x80),
+ 8, 3, sai1_sels, 8);
+ hws[IMXRT1170_CLK_SAI2_SEL] = imx_clk_hw_mux("sai2_sel", ccm_base + (66 * 0x80),
+ 8, 3, sai2_sels, 8);
+ hws[IMXRT1170_CLK_SAI3_SEL] = imx_clk_hw_mux("sai3_sel", ccm_base + (67 * 0x80),
+ 8, 3, sai3_sels, 8);
+ hws[IMXRT1170_CLK_SAI4_SEL] = imx_clk_hw_mux("sai4_sel", ccm_base + (68 * 0x80),
+ 8, 3, sai4_sels, 8);
+ hws[IMXRT1170_CLK_GC355_SEL] = imx_clk_hw_mux("gc355_sel", ccm_base + (69 * 0x80),
+ 8, 3, gc355_sels, 8);
+ hws[IMXRT1170_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + (70 * 0x80),
+ 8, 3, lcdif_sels, 8);
+ hws[IMXRT1170_CLK_LCDIFV2_SEL] = imx_clk_hw_mux("lcdifv2_sel", ccm_base + (71 * 0x80),
+ 8, 3, lcdifv2_sels, 8);
+ hws[IMXRT1170_CLK_MIPI_REF_SEL] = imx_clk_hw_mux("mipi_ref_sel", ccm_base + (72 * 0x80),
+ 8, 3, mipi_ref_sels, 8);
+ hws[IMXRT1170_CLK_MIPI_ESC_SEL] = imx_clk_hw_mux("mipi_esc_sel", ccm_base + (73 * 0x80),
+ 8, 3, mipi_esc_sels, 8);
+ hws[IMXRT1170_CLK_CSI2_SEL] = imx_clk_hw_mux("csi2_sel", ccm_base + (74 * 0x80),
+ 8, 3, csi2_sels, 8);
+ hws[IMXRT1170_CLK_CSI2_ESC_SEL] = imx_clk_hw_mux("csi2_esc_sel", ccm_base + (75 * 0x80),
+ 8, 3, csi2_esc_sels, 8);
+ hws[IMXRT1170_CLK_CSI2_UI_SEL] = imx_clk_hw_mux("csi2_ui_sel", ccm_base + (76 * 0x80),
+ 8, 3, csi2_ui_sels, 8);
+ hws[IMXRT1170_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", ccm_base + (77 * 0x80),
+ 8, 3, csi_sels, 8);
+ hws[IMXRT1170_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", ccm_base + (78 * 0x80),
+ 8, 3, cko1_sels, 8);
+ hws[IMXRT1170_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", ccm_base + (79 * 0x80),
+ 8, 3, cko2_sels, 8);
+
+ hws[IMXRT1170_CLK_M7_GATE] = imx_clk_hw_gate_dis_flags("m7_gate", "m7_sel", ccm_base +
+ (1 * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_M4_GATE] = imx_clk_hw_gate_dis_flags("m4_gate", "m4_sel", ccm_base +
+ (2 * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_BUS_GATE] = imx_clk_hw_gate_dis_flags("bus_gate", "bus_sel", ccm_base +
+ (3 * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_BUS_LPSR_GATE] = imx_clk_hw_gate_dis_flags("bus_lpsr_gate",
+ "bus_lpsr_sel", ccm_base + (4 * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_SEMC_GATE] = imx_clk_hw_gate_dis_flags("semc_gate", "semc_sel",
+ ccm_base + (5 * 0x80), 24,
+ CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_CSSYS_GATE] = imx_clk_hw_gate_dis_flags("cssys_gate", "cssys_sel",
+ ccm_base + (6 * 0x80), 24,
+ CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_CSTRACE_GATE] = imx_clk_hw_gate_dis_flags("cstrace_gate", "cstrace_sel",
+ ccm_base + (7 * 0x80), 24,
+ CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_M4_SYSTICK_GATE] = imx_clk_hw_gate_dis_flags("m4_systick_gate",
+ "m4_systick_sel", ccm_base +
+ (8 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_M7_SYSTICK_GATE] = imx_clk_hw_gate_dis_flags("m7_systick_gate",
+ "m7_systick_sel", ccm_base +
+ (9 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ADC1_GATE] = imx_clk_hw_gate_dis_flags("adc1_gate", "adc1_sel",
+ ccm_base + (10 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ADC2_GATE] = imx_clk_hw_gate_dis_flags("adc2_gate", "adc2_sel",
+ ccm_base + (11 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ACMP_GATE] = imx_clk_hw_gate_dis_flags("acmp_gate", "acmp_sel",
+ ccm_base + (12 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_FLEXIO1_GATE] = imx_clk_hw_gate_dis_flags("flexio1_gate", "flexio1_sel",
+ ccm_base + (13 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_FLEXIO2_GATE] = imx_clk_hw_gate_dis_flags("flexio2_gate", "flexio2_sel",
+ ccm_base + (14 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT1_GATE] = imx_clk_hw_gate_dis_flags("gpt1_gate", "gpt1_sel",
+ ccm_base + (15 * 0x80), 24,
+ CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_GPT2_GATE] = imx_clk_hw_gate_dis_flags("gpt2_gate", "gpt2_sel",
+ ccm_base + (16 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT3_GATE] = imx_clk_hw_gate_dis_flags("gpt3_gate", "gpt3_sel",
+ ccm_base + (17 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT4_GATE] = imx_clk_hw_gate_dis_flags("gpt4_gate", "gpt4_sel",
+ ccm_base + (18 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT5_GATE] = imx_clk_hw_gate_dis_flags("gpt5_gate", "gpt5_sel",
+ ccm_base + (19 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT6_GATE] = imx_clk_hw_gate_dis_flags("gpt6_gate", "gpt6_sel",
+ ccm_base + (20 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_FLEXSPI1_GATE] = imx_clk_hw_gate_dis_flags("flexspi1_gate",
+ "flexspi1_sel", ccm_base +
+ (21 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_FLEXSPI2_GATE] = imx_clk_hw_gate_dis_flags("flexspi2_gate",
+ "flexspi2_sel", ccm_base +
+ (22 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CAN1_GATE] = imx_clk_hw_gate_dis_flags("can1_gate", "can1_sel",
+ ccm_base + (23 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CAN2_GATE] = imx_clk_hw_gate_dis_flags("can2_gate", "can2_sel",
+ ccm_base + (24 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CAN3_GATE] = imx_clk_hw_gate_dis_flags("can3_gate", "can3_sel",
+ ccm_base + (25 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART1_GATE] = imx_clk_hw_gate_dis_flags("lpuart1_gate", "lpuart1_sel",
+ ccm_base + (26 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART2_GATE] = imx_clk_hw_gate_dis_flags("lpuart2_gate", "lpuart2_sel",
+ ccm_base + (27 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART3_GATE] = imx_clk_hw_gate_dis_flags("lpuart3_gate", "lpuart3_sel",
+ ccm_base + (28 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART4_GATE] = imx_clk_hw_gate_dis_flags("lpuart4_gate", "lpuart4_sel",
+ ccm_base + (29 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART5_GATE] = imx_clk_hw_gate_dis_flags("lpuart5_gate", "lpuart5_sel",
+ ccm_base + (30 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART6_GATE] = imx_clk_hw_gate_dis_flags("lpuart6_gate", "lpuart6_sel",
+ ccm_base + (31 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART7_GATE] = imx_clk_hw_gate_dis_flags("lpuart7_gate", "lpuart7_sel",
+ ccm_base + (32 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART8_GATE] = imx_clk_hw_gate_dis_flags("lpuart8_gate", "lpuart8_sel",
+ ccm_base + (33 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART9_GATE] = imx_clk_hw_gate_dis_flags("lpuart9_gate", "lpuart9_sel",
+ ccm_base + (34 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART10_GATE] = imx_clk_hw_gate_dis_flags("lpuart10_gate",
+ "lpuart10_sel", ccm_base +
+ (35 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART11_GATE] = imx_clk_hw_gate_dis_flags("lpuart11_gate",
+ "lpuart11_sel", ccm_base +
+ (36 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART12_GATE] = imx_clk_hw_gate_dis_flags("lpuart12_gate",
+ "lpuart12_sel", ccm_base +
+ (37 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C1_GATE] = imx_clk_hw_gate_dis_flags("lpi2c1_gate", "lpi2c1_sel",
+ ccm_base + (38 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C2_GATE] = imx_clk_hw_gate_dis_flags("lpi2c2_gate", "lpi2c2_sel",
+ ccm_base + (39 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C3_GATE] = imx_clk_hw_gate_dis_flags("lpi2c3_gate", "lpi2c3_sel",
+ ccm_base + (40 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C4_GATE] = imx_clk_hw_gate_dis_flags("lpi2c4_gate", "lpi2c4_sel",
+ ccm_base + (41 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C5_GATE] = imx_clk_hw_gate_dis_flags("lpi2c5_gate", "lpi2c5_sel",
+ ccm_base + (42 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C6_GATE] = imx_clk_hw_gate_dis_flags("lpi2c6_gate", "lpi2c6_sel",
+ ccm_base + (43 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI1_GATE] = imx_clk_hw_gate_dis_flags("lpspi1_gate", "lpspi1_sel",
+ ccm_base + (44 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI2_GATE] = imx_clk_hw_gate_dis_flags("lpspi2_gate", "lpspi2_sel",
+ ccm_base + (45 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI3_GATE] = imx_clk_hw_gate_dis_flags("lpspi3_gate", "lpspi3_sel",
+ ccm_base + (46 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI4_GATE] = imx_clk_hw_gate_dis_flags("lpspi4_gate", "lpspi4_sel",
+ ccm_base + (47 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI5_GATE] = imx_clk_hw_gate_dis_flags("lpspi5_gate", "lpspi5_sel",
+ ccm_base + (48 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI6_GATE] = imx_clk_hw_gate_dis_flags("lpspi6_gate", "lpspi6_sel",
+ ccm_base + (49 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_EMV1_GATE] = imx_clk_hw_gate_dis_flags("emv1_gate", "emv1_sel",
+ ccm_base + (50 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_EMV2_GATE] = imx_clk_hw_gate_dis_flags("emv2_gate", "emv2_sel",
+ ccm_base + (51 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET1_GATE] = imx_clk_hw_gate_dis_flags("enet1_gate", "enet1_sel",
+ ccm_base + (52 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET2_GATE] = imx_clk_hw_gate_dis_flags("enet2_gate", "enet2_sel",
+ ccm_base + (53 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_QOS_GATE] = imx_clk_hw_gate_dis_flags("enet_qos_gate",
+ "enet_qos_sel", ccm_base + (54 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_25M_GATE] = imx_clk_hw_gate_dis_flags("enet_25m_gate",
+ "enet_25m_sel", ccm_base + (55 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_TIMER1_GATE] = imx_clk_hw_gate_dis_flags("enet_timer1_gate",
+ "enet_timer1_sel", ccm_base + (56 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_TIMER2_GATE] = imx_clk_hw_gate_dis_flags("enet_timer2_gate",
+ "enet_timer2_sel", ccm_base + (57 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_TIMER3_GATE] = imx_clk_hw_gate_dis_flags("enet_timer3_gate",
+ "enet_timer3_sel", ccm_base + (58 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_USDHC1_GATE] = imx_clk_hw_gate_dis_flags("usdhc1_gate", "usdhc1_sel",
+ ccm_base + (59 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_USDHC2_GATE] = imx_clk_hw_gate_dis_flags("usdhc2_gate", "usdhc2_sel",
+ ccm_base + (60 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ASRC_GATE] = imx_clk_hw_gate_dis_flags("asrc_gate", "asrc_sel",
+ ccm_base + (61 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_MQS_GATE] = imx_clk_hw_gate_dis_flags("mqs_gate", "mqs_sel",
+ ccm_base + (62 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_MIC_GATE] = imx_clk_hw_gate_dis_flags("mic_gate", "mic_sel",
+ ccm_base + (63 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SPDIF_GATE] = imx_clk_hw_gate_dis_flags("spdif_gate", "spdif_sel",
+ ccm_base + (64 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SAI1_GATE] = imx_clk_hw_gate_dis_flags("sai1_gate", "sai1_sel",
+ ccm_base + (65 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SAI2_GATE] = imx_clk_hw_gate_dis_flags("sai2_gate", "sai2_sel",
+ ccm_base + (66 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SAI3_GATE] = imx_clk_hw_gate_dis_flags("sai3_gate", "sai3_sel",
+ ccm_base + (67 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SAI4_GATE] = imx_clk_hw_gate_dis_flags("sai4_gate", "sai4_sel",
+ ccm_base + (68 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GC355_GATE] = imx_clk_hw_gate_dis_flags("gc355_gate", "gc355_sel",
+ ccm_base + (69 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LCDIF_GATE] = imx_clk_hw_gate_dis_flags("lcdif_gate", "lcdif_sel",
+ ccm_base + (70 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LCDIFV2_GATE] = imx_clk_hw_gate_dis_flags("lcdifv2_gate", "lcdifv2_sel",
+ ccm_base + (71 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_MIPI_REF_GATE] = imx_clk_hw_gate_dis_flags("mipi_ref_gate",
+ "mipi_ref_sel", ccm_base +
+ (72 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_MIPI_ESC_GATE] = imx_clk_hw_gate_dis_flags("mipi_esc_gate",
+ "mipi_esc_sel", ccm_base +
+ (73 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CSI2_GATE] = imx_clk_hw_gate_dis_flags("csi2_gate", "csi2_sel",
+ ccm_base + (74 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CSI2_ESC_GATE] = imx_clk_hw_gate_dis_flags("csi2_esc_gate",
+ "csi2_esc_sel", ccm_base +
+ (75 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CSI2_UI_GATE] = imx_clk_hw_gate_dis_flags("csi2_ui_gate", "csi2_ui_sel",
+ ccm_base + (76 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CSI_GATE] = imx_clk_hw_gate_dis_flags("csi_gate", "csi_sel",
+ ccm_base + (77 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CKO1_GATE] = imx_clk_hw_gate_dis_flags("cko1_gate", "cko1_sel",
+ ccm_base + (78 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CKO2_GATE] = imx_clk_hw_gate_dis_flags("cko2_gate", "cko2_sel",
+ ccm_base + (79 * 0x80), 24, 0);
+
+ hws[IMXRT1170_CLK_M7] = imx_clk_hw_divider("m7", "m7_gate", ccm_base + (1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_M4] = imx_clk_hw_divider("m4", "m4_gate", ccm_base + (2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_BUS] = imx_clk_hw_divider("bus", "bus_gate", ccm_base + (3 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_BUS_LPSR] = imx_clk_hw_divider("bus_lpsr", "bus_lpsr_gate", ccm_base +
+ (4 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SEMC] = imx_clk_hw_divider("semc", "semc_gate", ccm_base + (5 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSSYS] = imx_clk_hw_divider("cssys", "cssys_gate", ccm_base + (6 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSTRACE] = imx_clk_hw_divider("cstrace", "cstrace_gate", ccm_base +
+ (7 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_M4_SYSTICK] = imx_clk_hw_divider("m4_systick", "m4_systick_gate",
+ ccm_base + (8 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_M7_SYSTICK] = imx_clk_hw_divider("m7_systick", "m7_systick_gate",
+ ccm_base + (9 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ADC1] = imx_clk_hw_divider("adc1", "adc1_gate", ccm_base + (10 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ADC2] = imx_clk_hw_divider("adc2", "adc2_gate", ccm_base + (11 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ACMP] = imx_clk_hw_divider("acmp", "acmp_gate", ccm_base + (12 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_FLEXIO1] = imx_clk_hw_divider("flexio1", "flexio1_gate", ccm_base +
+ (13 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_FLEXIO2] = imx_clk_hw_divider("flexio2", "flexio2_gate", ccm_base +
+ (14 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT1] = imx_clk_hw_divider("gpt1", "gpt1_gate", ccm_base + (15 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT2] = imx_clk_hw_divider("gpt2", "gpt2_gate", ccm_base + (16 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT3] = imx_clk_hw_divider("gpt3", "gpt3_gate", ccm_base + (17 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT4] = imx_clk_hw_divider("gpt4", "gpt4_gate", ccm_base + (18 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT5] = imx_clk_hw_divider("gpt5", "gpt5_gate", ccm_base + (19 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT6] = imx_clk_hw_divider("gpt6", "gpt6_gate", ccm_base + (20 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_FLEXSPI1] = imx_clk_hw_divider("flexspi1", "flexspi1_gate", ccm_base +
+ (21 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_FLEXSPI2] = imx_clk_hw_divider("flexspi2", "flexspi2_gate", ccm_base +
+ (22 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CAN1] = imx_clk_hw_divider("can1", "can1_gate", ccm_base + (23 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CAN2] = imx_clk_hw_divider("can2", "can2_gate", ccm_base + (24 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CAN3] = imx_clk_hw_divider("can3", "can3_gate", ccm_base + (25 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART1] = imx_clk_hw_divider("lpuart1", "lpuart1_gate", ccm_base +
+ (26 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART2] = imx_clk_hw_divider("lpuart2", "lpuart2_gate", ccm_base +
+ (27 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART3] = imx_clk_hw_divider("lpuart3", "lpuart3_gate", ccm_base +
+ (28 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART4] = imx_clk_hw_divider("lpuart4", "lpuart4_gate", ccm_base +
+ (29 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART5] = imx_clk_hw_divider("lpuart5", "lpuart5_gate", ccm_base +
+ (30 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART6] = imx_clk_hw_divider("lpuart6", "lpuart6_gate", ccm_base +
+ (31 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART7] = imx_clk_hw_divider("lpuart7", "lpuart7_gate", ccm_base +
+ (32 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART8] = imx_clk_hw_divider("lpuart8", "lpuart8_gate", ccm_base +
+ (33 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART9] = imx_clk_hw_divider("lpuart9", "lpuart9_gate", ccm_base +
+ (34 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART10] = imx_clk_hw_divider("lpuart10", "lpuart10_gate", ccm_base +
+ (35 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART11] = imx_clk_hw_divider("lpuart11", "lpuart11_gate", ccm_base +
+ (36 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART12] = imx_clk_hw_divider("lpuart12", "lpuart12_gate", ccm_base +
+ (37 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C1] = imx_clk_hw_divider("lpi2c1", "lpi2c1_gate", ccm_base +
+ (38 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C2] = imx_clk_hw_divider("lpi2c2", "lpi2c2_gate", ccm_base +
+ (39 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C3] = imx_clk_hw_divider("lpi2c3", "lpi2c3_gate", ccm_base +
+ (40 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C4] = imx_clk_hw_divider("lpi2c4", "lpi2c4_gate", ccm_base +
+ (41 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C5] = imx_clk_hw_divider("lpi2c5", "lpi2c5_gate", ccm_base +
+ (42 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C6] = imx_clk_hw_divider("lpi2c6", "lpi2c6_gate", ccm_base +
+ (43 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI1] = imx_clk_hw_divider("lpspi1", "lpspi1_gate", ccm_base +
+ (44 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI2] = imx_clk_hw_divider("lpspi2", "lpspi2_gate", ccm_base +
+ (45 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI3] = imx_clk_hw_divider("lpspi3", "lpspi3_gate", ccm_base +
+ (46 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI4] = imx_clk_hw_divider("lpspi4", "lpspi4_gate", ccm_base +
+ (47 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI5] = imx_clk_hw_divider("lpspi5", "lpspi5_gate", ccm_base +
+ (48 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI6] = imx_clk_hw_divider("lpspi6", "lpspi6_gate", ccm_base +
+ (49 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_EMV1] = imx_clk_hw_divider("emv1", "emv1_gate", ccm_base + (50 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_EMV2] = imx_clk_hw_divider("emv2", "emv2_gate", ccm_base + (51 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET1] = imx_clk_hw_divider("enet1", "enet1_gate", ccm_base + (52 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET2] = imx_clk_hw_divider("enet2", "enet2_gate", ccm_base + (53 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_QOS] = imx_clk_hw_divider("enet_qos", "enet_qos_gate", ccm_base +
+ (54 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_25M] = imx_clk_hw_divider("enet_25m", "enet_25m_gate", ccm_base +
+ (55 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_TIMER1] = imx_clk_hw_divider("enet_timer1", "enet_timer1_gate",
+ ccm_base + (56 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_TIMER2] = imx_clk_hw_divider("enet_timer2", "enet_timer2_gate",
+ ccm_base + (57 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_TIMER3] = imx_clk_hw_divider("enet_timer3", "enet_timer3_gate",
+ ccm_base + (58 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_USDHC1] = imx_clk_hw_divider("usdhc1", "usdhc1_gate", ccm_base +
+ (59 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_USDHC2] = imx_clk_hw_divider("usdhc2", "usdhc2_gate", ccm_base +
+ (60 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ASRC] = imx_clk_hw_divider("asrc", "asrc_gate", ccm_base + (61 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_MQS] = imx_clk_hw_divider("mqs", "mqs_gate", ccm_base + (62 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_MIC] = imx_clk_hw_divider("mic", "mic_gate", ccm_base + (63 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SPDIF] = imx_clk_hw_divider("spdif", "spdif_gate", ccm_base + (64 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SAI1] = imx_clk_hw_divider("sai1", "sai1_gate", ccm_base + (65 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SAI2] = imx_clk_hw_divider("sai2", "sai2_gate", ccm_base + (66 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SAI3] = imx_clk_hw_divider("sai3", "sai3_gate", ccm_base + (67 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SAI4] = imx_clk_hw_divider("sai4", "sai4_gate", ccm_base + (68 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GC355] = imx_clk_hw_divider("gc355", "gc355_gate", ccm_base + (69 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LCDIF] = imx_clk_hw_divider("lcdif", "lcdif_gate", ccm_base + (70 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LCDIFV2] = imx_clk_hw_divider("lcdifv2", "lcdifv2_gate", ccm_base +
+ (71 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_MIPI_REF] = imx_clk_hw_divider("mipi_ref", "mipi_ref_gate", ccm_base +
+ (72 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_MIPI_ESC] = imx_clk_hw_divider("mipi_esc", "mipi_esc_gate", ccm_base +
+ (73 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSI2] = imx_clk_hw_divider("csi2", "csi2_gate", ccm_base + (74 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSI2_ESC] = imx_clk_hw_divider("csi2_esc", "csi2_esc_gate", ccm_base +
+ (75 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSI2_UI] = imx_clk_hw_divider("csi2_ui", "csi2_ui_gate", ccm_base +
+ (76 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSI] = imx_clk_hw_divider("csi", "csi_gate", ccm_base + (77 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CKO1] = imx_clk_hw_divider("cko1", "cko1_gate", ccm_base + (78 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CKO2] = imx_clk_hw_divider("cko2", "cko2_gate", ccm_base + (79 * 0x80), 0, 8);
+
+ hws[IMXRT1170_CLK_USB] = imx_clk_hw_gate("usb", "bus", ccm_base + LPCG_GATE(115), 0);
+
+ imx_check_clk_hws(hws, IMXRT1170_CLK_END);
+
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
+ if (ret < 0) {
+ dev_err(dev, "Failed to register clks for i.MXRT1170.\n");
+ imx_unregister_hw_clocks(hws, IMXRT1170_CLK_END);
+ }
+ return ret;
+}
+
+static const struct of_device_id imxrt1170_clk_of_match[] = {
+ { .compatible = "fsl,imxrt1170-ccm" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imxrt1170_clk_of_match);
+
+static struct platform_driver imxrt1170_clk_driver = {
+ .probe = imxrt1170_clocks_probe,
+ .driver = {
+ .name = "imxrt1170-ccm",
+ .of_match_table = imxrt1170_clk_of_match,
+ },
+};
+module_platform_driver(imxrt1170_clk_driver);
--
2.36.1
Add i.MXRT1170 compatible string to Documentation.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
V1 -> V2:
- New commit to fix dtbs_check
V2 -> V3:
- Nothing done
V3 -> V4:
- Fix rebase artifact
V4 -> V5:
- Nothing done
V5 -> V6:
- Nothing done
---
Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
index 30eaa62e1aed..2c2f3c97a125 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
@@ -32,6 +32,9 @@ properties:
- fsl,imx8qm-lpuart
- fsl,imx8dxl-lpuart
- const: fsl,imx8qxp-lpuart
+ - items:
+ - const: fsl,imxrt1170-lpuart
+ - const: fsl,imxrt1050-lpuart
reg:
maxItems: 1
--
2.36.1
Add "fsl,imxrt1170" to imxrt_compat
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Nothing done
V2 -> V3:
- Nothing done
V3 -> V4:
- Nothing done
V4 -> V5:
- Nothing done
V5 -> V6:
- Nothing done
---
arch/arm/mach-imx/mach-imxrt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/mach-imxrt.c b/arch/arm/mach-imx/mach-imxrt.c
index 2063a3059c84..0070214feb42 100644
--- a/arch/arm/mach-imx/mach-imxrt.c
+++ b/arch/arm/mach-imx/mach-imxrt.c
@@ -10,6 +10,7 @@
static const char *const imxrt_compat[] __initconst = {
"fsl,imxrt1050",
+ "fsl,imxrt1170",
NULL
};
--
2.36.1
Both the i.MXRT1170 and 1050 have the same GPT timer as "fsl,imx6dl-gpt"
Add i.MXRT to the compatible list.
Signed-off-by: Jesse Taube <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
V1 -> V2:
- Nothing done
V2 -> V3:
- Nothing done
V3 -> V4:
- Nothing done
V4 -> V5:
- Nothing done
V5 -> V6:
- Nothing done
---
Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
index a4f51f46b7a1..716c6afcca1f 100644
--- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
+++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
@@ -31,6 +31,8 @@ properties:
- enum:
- fsl,imx6sl-gpt
- fsl,imx6sx-gpt
+ - fsl,imxrt1050-gpt
+ - fsl,imxrt1170-gpt
- const: fsl,imx6dl-gpt
reg:
--
2.36.1
Hi Jesse,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on soc/for-next linus/master v6.0-rc3 next-20220901]
[cannot apply to tip/timers/core]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jesse-Taube/Add-support-for-i-MXRT1170-evk/20220902-023651
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-defconfig
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/4949a69928402161dfceafc7c6efc708433f5fec
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jesse-Taube/Add-support-for-i-MXRT1170-evk/20220902-023651
git checkout 4949a69928402161dfceafc7c6efc708433f5fec
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/clk/imx/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
In file included from include/linux/bits.h:6,
from drivers/clk/imx/clk-imx6q.c:9:
drivers/clk/imx/clk-imx6q.c: In function 'imx6q_clocks_init':
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6q.c:477:33: note: in expansion of macro 'imx_clk_hw_pllv3'
477 | hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6q.c:478:33: note: in expansion of macro 'imx_clk_hw_pllv3'
478 | hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6q.c:479:33: note: in expansion of macro 'imx_clk_hw_pllv3'
479 | hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6q.c:480:33: note: in expansion of macro 'imx_clk_hw_pllv3'
480 | hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6q.c:481:33: note: in expansion of macro 'imx_clk_hw_pllv3'
481 | hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6q.c:482:33: note: in expansion of macro 'imx_clk_hw_pllv3'
482 | hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6q.c:483:33: note: in expansion of macro 'imx_clk_hw_pllv3'
483 | hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
| ^~~~~~~~~~~~~~~~
--
In file included from include/linux/bits.h:6,
from drivers/clk/imx/clk-imx6sl.c:6:
drivers/clk/imx/clk-imx6sl.c: In function 'imx6sl_clocks_init':
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sl.c:217:32: note: in expansion of macro 'imx_clk_hw_pllv3'
217 | hws[IMX6SL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sl.c:218:32: note: in expansion of macro 'imx_clk_hw_pllv3'
218 | hws[IMX6SL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sl.c:219:32: note: in expansion of macro 'imx_clk_hw_pllv3'
219 | hws[IMX6SL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sl.c:220:32: note: in expansion of macro 'imx_clk_hw_pllv3'
220 | hws[IMX6SL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sl.c:221:32: note: in expansion of macro 'imx_clk_hw_pllv3'
221 | hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sl.c:222:32: note: in expansion of macro 'imx_clk_hw_pllv3'
222 | hws[IMX6SL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sl.c:223:32: note: in expansion of macro 'imx_clk_hw_pllv3'
223 | hws[IMX6SL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
| ^~~~~~~~~~~~~~~~
--
In file included from include/linux/bits.h:6,
from include/linux/bitops.h:6,
from include/linux/kernel.h:22,
from include/linux/clk.h:13,
from drivers/clk/imx/clk-imx6sll.c:8:
drivers/clk/imx/clk-imx6sll.c: In function 'imx6sll_clocks_init':
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sll.c:123:33: note: in expansion of macro 'imx_clk_hw_pllv3'
123 | hws[IMX6SLL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sll.c:124:33: note: in expansion of macro 'imx_clk_hw_pllv3'
124 | hws[IMX6SLL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sll.c:125:33: note: in expansion of macro 'imx_clk_hw_pllv3'
125 | hws[IMX6SLL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sll.c:126:33: note: in expansion of macro 'imx_clk_hw_pllv3'
126 | hws[IMX6SLL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sll.c:127:33: note: in expansion of macro 'imx_clk_hw_pllv3'
127 | hws[IMX6SLL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sll.c:128:33: note: in expansion of macro 'imx_clk_hw_pllv3'
128 | hws[IMX6SLL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sll.c:129:33: note: in expansion of macro 'imx_clk_hw_pllv3'
129 | hws[IMX6SLL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
| ^~~~~~~~~~~~~~~~
--
In file included from include/linux/bits.h:6,
from drivers/clk/imx/clk-imx6sx.c:7:
drivers/clk/imx/clk-imx6sx.c: In function 'imx6sx_clocks_init':
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sx.c:160:32: note: in expansion of macro 'imx_clk_hw_pllv3'
160 | hws[IMX6SX_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sx.c:161:32: note: in expansion of macro 'imx_clk_hw_pllv3'
161 | hws[IMX6SX_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sx.c:162:32: note: in expansion of macro 'imx_clk_hw_pllv3'
162 | hws[IMX6SX_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sx.c:163:32: note: in expansion of macro 'imx_clk_hw_pllv3'
163 | hws[IMX6SX_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sx.c:164:32: note: in expansion of macro 'imx_clk_hw_pllv3'
164 | hws[IMX6SX_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sx.c:165:32: note: in expansion of macro 'imx_clk_hw_pllv3'
165 | hws[IMX6SX_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
| ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
7 | #define BIT(nr) (UL(1) << (nr))
| ^~~~~~~~~~~~~~~
drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
9 | #define BM_PLL_POWER BIT(12)
| ^~~
drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
108 | __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
| ^~~~~~~~~~~~
drivers/clk/imx/clk-imx6sx.c:166:32: note: in expansion of macro 'imx_clk_hw_pllv3'
166 | hws[IMX6SX_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
| ^~~~~~~~~~~~~~~~
..
vim +7 include/vdso/bits.h
3945ff37d2f48d Vincenzo Frascino 2020-03-20 6
3945ff37d2f48d Vincenzo Frascino 2020-03-20 @7 #define BIT(nr) (UL(1) << (nr))
3945ff37d2f48d Vincenzo Frascino 2020-03-20 8
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On Thu, Sep 1, 2022 at 8:33 PM Jesse Taube <[email protected]> wrote:
> This patch contains:
> - Update to imxrt_defconfig
> - Devicetree
> - Clock driver
> - Pinctrl driver
No it does not, I already merged that.
I think you should probably split up your series per-subsystem so the
clock bindings and changes can be merged separately etc.
Then the DTS files can be added to the ARM SoC tree as a final step.
When you send everything in one bundle like this subsystem maintainers
don't know if they can merge e.g. just the clock patches separately
and be done with their part (like what I did with pinctrl).
Yours.
Linus Walleij
On 9/2/22 04:06, Linus Walleij wrote:
> On Thu, Sep 1, 2022 at 8:33 PM Jesse Taube <[email protected]> wrote:
>
>> This patch contains:
>> - Update to imxrt_defconfig
>> - Devicetree
>> - Clock driver
>> - Pinctrl driver
>
> No it does not, I already merged that.
>
> I think you should probably split up your series per-subsystem so the
> clock bindings and changes can be merged separately etc.
>
> Then the DTS files can be added to the ARM SoC tree as a final step.
>
> When you send everything in one bundle like this subsystem maintainers
> don't know if they can merge e.g. just the clock patches separately
> and be done with their part (like what I did with pinctrl).
Do you think its possible to add Docs for Device tree compatibles that
aren't added yet?
Thanks,
Jesse Taube
>
> Yours.
> Linus Walleij
On Fri, Sep 2, 2022 at 2:57 PM Jesse Taube <[email protected]> wrote:
> On 9/2/22 04:06, Linus Walleij wrote:
> > On Thu, Sep 1, 2022 at 8:33 PM Jesse Taube <[email protected]> wrote:
> >
> >> This patch contains:
> >> - Update to imxrt_defconfig
> >> - Devicetree
> >> - Clock driver
> >> - Pinctrl driver
> >
> > No it does not, I already merged that.
> >
> > I think you should probably split up your series per-subsystem so the
> > clock bindings and changes can be merged separately etc.
> >
> > Then the DTS files can be added to the ARM SoC tree as a final step.
> >
> > When you send everything in one bundle like this subsystem maintainers
> > don't know if they can merge e.g. just the clock patches separately
> > and be done with their part (like what I did with pinctrl).
>
> Do you think its possible to add Docs for Device tree compatibles that
> aren't added yet?
Bindings and drivers are orthogonal, we only submit them together
to provide context for reviewers.
It is also possible to submit device trees with compatibles and entire
nodes without bindings because there essentially is no real police for
this. Of course it is not recommended.
If you are confident that bindings and device trees will come in the
same merge window it is fine to merge them separately through different
trees.
Yours,
Linus Walleij
On 9/30/22 16:28, Stephen Boyd wrote:
> Quoting Jesse Taube (2022-09-01 11:33:41)
>> Add clock driver support for i.MXRT1170.
>>
>> Cc: Giulio Benetti <[email protected]>
>> Signed-off-by: Jesse Taube <[email protected]>
>> ---
>> V1 -> V2:
>> - Add slab.h and clock-provider.h
>> - Add spaces in `root_clocks`
>> - Expand and sort macro
>> - Move `clk_hw` structs to `clocks_probe`
>> - Remove of_irq.h
>> - Remove unused code/comments
>> V2 -> V3:
>> - Expand root_clocks names array
>> - Remove root_clock_names enum
>> V3 -> V4:
>> - Nothing done
>> V4 -> V5:
>> - Use __imx_clk_hw_pllv3 to change power bit
>> V5 -> V6:
>> - Nothing done
>> ---
>> drivers/clk/imx/Kconfig | 7 +
>> drivers/clk/imx/Makefile | 1 +
>> drivers/clk/imx/clk-imxrt1170.c | 749 ++++++++++++++++++++++++++++++++
>> 3 files changed, 757 insertions(+)
>> create mode 100644 drivers/clk/imx/clk-imxrt1170.c
>>
>> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
>> index 25785ec9c276..704a7777af4f 100644
>> --- a/drivers/clk/imx/Kconfig
>> +++ b/drivers/clk/imx/Kconfig
>> @@ -119,3 +119,10 @@ config CLK_IMXRT1050
>> select MXC_CLK
>> help
>> Build the driver for i.MXRT1050 CCM Clock Driver
>> +
>> +config CLK_IMXRT1170
>> + tristate "IMXRT1170 CCM Clock Driver"
>> + depends on SOC_IMXRT
>> + select MXC_CLK
>> + help
>> + Build the driver for i.MXRT1170 CCM Clock Driver
>> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
>> index 88b9b9285d22..d607a6d8138a 100644
>> --- a/drivers/clk/imx/Makefile
>> +++ b/drivers/clk/imx/Makefile
>> @@ -52,4 +52,5 @@ obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o
>> obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o
>> obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o
>> obj-$(CONFIG_CLK_IMXRT1050) += clk-imxrt1050.o
>> +obj-$(CONFIG_CLK_IMXRT1170) += clk-imxrt1170.o
>> obj-$(CONFIG_CLK_VF610) += clk-vf610.o
>> diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
>> new file mode 100644
>> index 000000000000..71d9aacf9751
>> --- /dev/null
>> +++ b/drivers/clk/imx/clk-imxrt1170.c
>> @@ -0,0 +1,749 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * Copyright (C) 2022
>> + * Author(s):
>> + * Jesse Taube <[email protected]>
>> + */
>> +#include <linux/clk.h>
>
> Please don't include clk.h unless you use consumer clk APIs. Doesn't
> look like it is used here?
>
>> +#include <linux/of_address.h>
>> +#include <linux/slab.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/platform_device.h>
>
> Sorting alphabetically is nice.
Oh my bad, will fix.
>> +#include <dt-bindings/clock/imxrt1170-clock.h>
>> +
>> +#include "clk.h"
>> +
>> +#define CLOCK_MUX_DEFAULT "rcosc48M_div2", "osc", "rcosc400M", "rcosc16M"
> [...]
>> +
>> +static int imxrt1170_clocks_probe(struct platform_device *pdev)
>> +{
>> + void __iomem *ccm_base;
>> + void __iomem *pll_base;
>> + struct clk_hw **hws;
>> + struct clk_hw_onecell_data *clk_hw_data;
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> + struct device_node *anp;
>> + int ret;
>> +
>> + clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
>> + IMXRT1170_CLK_END), GFP_KERNEL);
>> + if (WARN_ON(!clk_hw_data))
>> + return -ENOMEM;
>> +
>> + clk_hw_data->num = IMXRT1170_CLK_END;
>> + hws = clk_hw_data->hws;
>> +
>> + hws[IMXRT1170_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc");
>> + hws[IMXRT1170_CLK_RCOSC_16M] = imx_obtain_fixed_clk_hw(np, "rcosc16M");
>> + hws[IMXRT1170_CLK_OSC_32K] = imx_obtain_fixed_clk_hw(np, "osc32k");
>> +
>> + hws[IMXRT1170_CLK_RCOSC_48M] = imx_clk_hw_fixed_factor("rcosc48M", "rcosc16M", 3, 1);
>> + hws[IMXRT1170_CLK_RCOSC_400M] = imx_clk_hw_fixed_factor("rcosc400M", "rcosc16M", 25, 1);
>> + hws[IMXRT1170_CLK_RCOSC_48M_DIV2] = imx_clk_hw_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2);
>> +
>> + anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop");
>> + pll_base = of_iomap(anp, 0);
>> + of_node_put(anp);
>> + if (WARN_ON(!pll_base))
>> + return -ENOMEM;
>
> The kzalloc() leaked.
LOL `grep -r of_find_compatible_node drivers/clk/imx`...
Shall I send patches for the rest of IMX.
>
>> +
>> + /* Anatop clocks */
>> + hws[IMXRT1170_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL);
>> +
>> + hws[IMXRT1170_CLK_PLL_ARM_PRE] = __imx_clk_hw_pllv3(IMX_PLLV3_SYSV2, "pll_arm_pre", "osc",
>> + pll_base + 0x200, 0xff, 13);
>> + hws[IMXRT1170_CLK_PLL_ARM_BYPASS] = imx_clk_hw_mux("pll_arm_bypass", pll_base + 0x200, 17,
>> + 1, pll_arm_mux, 2);
>> + hws[IMXRT1170_CLK_PLL_ARM_DIV] = clk_hw_register_divider_table(NULL, "pll_arm_div",
>> + "pll_arm_bypass", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
>> + pll_base + 0x200, 15, 2, 0, post_div_table, &imx_ccm_lock);
>> + hws[IMXRT1170_CLK_PLL_ARM] = imx_clk_hw_gate("pll_arm", "pll_arm_div", pll_base + 0x200, 14);
>> +
>> + hws[IMXRT1170_CLK_PLL3_PRE] = __imx_clk_hw_pllv3(IMX_PLLV3_GENERICV2, "pll3_pre", "osc",
>> + pll_base + 0x210, 0x1, 21);
>> + hws[IMXRT1170_CLK_PLL3_BYPASS] = imx_clk_hw_mux("pll3_bypass",
>> + pll_base + 0x210, 16, 1, pll3_mux, 2);
>> + hws[IMXRT1170_CLK_PLL3] = imx_clk_hw_gate("pll3_sys", "pll3_bypass", pll_base + 0x210, 13);
>> +
>> + hws[IMXRT1170_CLK_PLL2_PRE] = __imx_clk_hw_pllv3(IMX_PLLV3_GENERICV2, "pll2_pre", "osc",
>> + pll_base + 0x240, 0x1, 23);
>> + hws[IMXRT1170_CLK_PLL2_BYPASS] = imx_clk_hw_mux("pll2_bypass",
>> + pll_base + 0x240, 16, 1, pll2_mux, 2);
>> + hws[IMXRT1170_CLK_PLL2] = imx_clk_hw_gate("pll2_sys", "pll2_bypass", pll_base + 0x240, 13);
>> +
>> + hws[IMXRT1170_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0", "pll3_sys", pll_base + 0x230, 0);
>> + hws[IMXRT1170_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1", "pll3_sys", pll_base + 0x230, 1);
>> + hws[IMXRT1170_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2", "pll3_sys", pll_base + 0x230, 2);
>> + hws[IMXRT1170_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3", "pll3_sys", pll_base + 0x230, 3);
>> + hws[IMXRT1170_CLK_PLL3_DIV2_GATE] = imx_clk_hw_fixed_factor("pll3_div2_gate", "pll3_sys", 1, 2);
>> + hws[IMXRT1170_CLK_PLL3_DIV2] = imx_clk_hw_gate("pll3_div2", "pll3_sys", pll_base + 0x210, 3);
>> +
>> + hws[IMXRT1170_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0", "pll2_sys", pll_base + 0x270, 0);
>> + hws[IMXRT1170_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1", "pll2_sys", pll_base + 0x270, 1);
>> + hws[IMXRT1170_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2", "pll2_sys", pll_base + 0x270, 2);
>> + hws[IMXRT1170_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3", "pll2_sys", pll_base + 0x270, 3);
>> +
>> + /* CCM clocks */
>> + ccm_base = devm_platform_ioremap_resource(pdev, 0);
>> + if (WARN_ON(IS_ERR(ccm_base)))
>> + return PTR_ERR(ccm_base);
>> +
>> + hws[IMXRT1170_CLK_M7_SEL] = imx_clk_hw_mux("m7_sel", ccm_base + (1 * 0x80),
> [....]
>> + hws[IMXRT1170_CLK_CSI2_UI] = imx_clk_hw_divider("csi2_ui", "csi2_ui_gate", ccm_base +
>> + (76 * 0x80), 0, 8);
>> + hws[IMXRT1170_CLK_CSI] = imx_clk_hw_divider("csi", "csi_gate", ccm_base + (77 * 0x80), 0, 8);
>> + hws[IMXRT1170_CLK_CKO1] = imx_clk_hw_divider("cko1", "cko1_gate", ccm_base + (78 * 0x80), 0, 8);
>> + hws[IMXRT1170_CLK_CKO2] = imx_clk_hw_divider("cko2", "cko2_gate", ccm_base + (79 * 0x80), 0, 8);
>> +
>> + hws[IMXRT1170_CLK_USB] = imx_clk_hw_gate("usb", "bus", ccm_base + LPCG_GATE(115), 0);
>> +
>> + imx_check_clk_hws(hws, IMXRT1170_CLK_END);
>> +
>> + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
>
> Use devm? Or implement a driver remove function?
Uh this is the same in the rest of imx could you explain a bit more?
Very sorry for the low quality code :(
Thanks,
Jesse Taube
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to register clks for i.MXRT1170.\n");
>> + imx_unregister_hw_clocks(hws, IMXRT1170_CLK_END);
>> + }
>> + return ret;
>> +}
>> +
>> +static const struct of_device_id imxrt1170_clk_of_match[] = {
>> + { .compatible = "fsl,imxrt1170-ccm" },
>> + { /* Sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, imxrt1170_clk_of_match);
>> +
>> +static struct platform_driver imxrt1170_clk_driver = {
>> + .probe = imxrt1170_clocks_probe,
>> + .driver = {
>> + .name = "imxrt1170-ccm",
>> + .of_match_table = imxrt1170_clk_of_match,
>> + },