This series adds support for:
- SERDES, WIZ DT nodes, Serdes lane control mux
- DSS and DisplayPort-0 nodes
This support DEPENDS upon another series which was introduced as part
of discussion in v5. That series[1] moves the ti-serdes headers file
from bindings to "arch/arm64/boot/dts/ti". (That series is merged in
linux-next tree)
Changelog v6->v7:
- change compatible for scm_conf to 'simple-bus'
- drop main_cpsw node due to driver dependency on [2]
Changelog v5->v6:
- Change header file according to [1].
- Add idle-state property in serdes_ln_ctrl node.
- Fix dtbs_check warning due to clock-frequency property in serdes_refclk
node by disabling the node in main.dtsi and enabling it in board file
when the clock-frequency node is actually added.
Changelog v4->v5:
- rebased the patches on linux-next tip.
Changelog v3->v4:
- add reg property to serdes_ln_ctrl and fix the node name again to
get rid of dtbs_check error.
- reorder reg, reg-names and ranges property for main_cpsw1.
- correct the order for clocks in serdes_wiz nodes to fix dtbs_check
warnings.
- fix indentation in reg, reg-names and clock property for dss node.
- add comments for the reg type in dss registers.
Changelog v3->v2:
- fix dtc warnings for 'scm_conf' and 'serdes_ln_ctrl' nodes
(Checked all the changes of the series with W=12 option during build)
- added clock-frequency for serdes_refclk along with other EVM changes
This refclk is being used by all the instances of serdes_wiz which
are disabled by default. So configuring refclk when the serdes nodes
are used for the first time is okay.
Changelog v1->v2:
- Moved J784S4 EVM changes together to the last patch
(Suggested by Andrew)
v5 patch link:
<https://lore.kernel.org/all/[email protected]/>
[1]: <https://lore.kernel.org/all/[email protected]/>
[2]: <https://lore.kernel.org/all/[email protected]/>
Rahul T R (2):
arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
Siddharth Vadapalli (2):
arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane
mux
arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 117 +++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 285 +++++++++++++++++++++
2 files changed, 402 insertions(+)
--
2.25.1
From: Rahul T R <[email protected]>
Enable display for J784S4 EVM.
Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for
DP HPD. Add the clock frequency for serdes_refclk.
Add the endpoint nodes to describe connection from:
DSS => MHDP => DisplayPort connector.
Also add the GPIO expander-4 node and pinmux for main_i2c4 which is
required for controlling DP power. Set status for all required nodes
for DP-0 as "okay".
Signed-off-by: Rahul T R <[email protected]>
[[email protected]: move all the changes together to enable DP-0 in EVM]
Signed-off-by: Jayesh Choudhary <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 117 +++++++++++++++++++++++
1 file changed, 117 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 7ad152a1b90f..1145a7f046e2 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 {
states = <1800000 0x0>,
<3300000 0x1>;
};
+
+ dp0_pwr_3v3: regulator-dp0-prw {
+ compatible = "regulator-fixed";
+ regulator-name = "dp0-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ dp0: dp0-connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp0_pwr_3v3>;
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
};
&main_pmx0 {
@@ -286,6 +308,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
>;
};
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
+ >;
+ };
+
+ main_i2c4_pins_default: main-i2c4-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
+ J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
+ >;
+ };
};
&wkup_pmx2 {
@@ -827,3 +862,85 @@ adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
+
+&serdes_refclk {
+ status = "okay";
+ clock-frequency = <100000000>;
+};
+
+&dss {
+ status = "okay";
+ assigned-clocks = <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ assigned-clock-parents = <&k3_clks 218 3>,
+ <&k3_clks 218 7>,
+ <&k3_clks 218 16>,
+ <&k3_clks 218 22>;
+};
+
+&serdes_wiz4 {
+ status = "okay";
+};
+
+&serdes4 {
+ status = "okay";
+ serdes4_dp_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
+ <&serdes_wiz4 3>, <&serdes_wiz4 4>;
+ };
+};
+
+&mhdp {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+ phys = <&serdes4_dp_link>;
+ phy-names = "dpphy";
+};
+
+&dss_ports {
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&main_i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
+
+ exp4: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp0_connector_in>;
+ };
+ };
+};
--
2.25.1
From: Siddharth Vadapalli <[email protected]>
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
Signed-off-by: Siddharth Vadapalli <[email protected]>
[[email protected]: Fix serdes_ln_ctrl node]
Signed-off-by: Jayesh Choudhary <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 11f163e5cadf..8a816563706b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -5,6 +5,10 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/mux/mux.h>
+
+#include "k3-serdes.h"
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -26,6 +30,42 @@ l3cache-sram@200000 {
};
};
+ scm_conf: bus@100000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x00100000 0x00 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "mmio-mux";
+ reg = <0x00004080 0x30>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
+ <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>,
+ <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
+ <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
+ <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
+ <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
+ <J784S4_SERDES4_LANE0_EDP_LANE0>,
+ <J784S4_SERDES4_LANE1_EDP_LANE1>,
+ <J784S4_SERDES4_LANE2_EDP_LANE2>,
+ <J784S4_SERDES4_LANE3_EDP_LANE3>;
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
2.25.1
On 10:38-20230728, Jayesh Choudhary wrote:
> This series adds support for:
> - SERDES, WIZ DT nodes, Serdes lane control mux
> - DSS and DisplayPort-0 nodes
>
> This support DEPENDS upon another series which was introduced as part
> of discussion in v5. That series[1] moves the ti-serdes headers file
> from bindings to "arch/arm64/boot/dts/ti". (That series is merged in
> linux-next tree)
>
> Changelog v6->v7:
> - change compatible for scm_conf to 'simple-bus'
> - drop main_cpsw node due to driver dependency on [2]
>
> Changelog v5->v6:
> - Change header file according to [1].
> - Add idle-state property in serdes_ln_ctrl node.
> - Fix dtbs_check warning due to clock-frequency property in serdes_refclk
> node by disabling the node in main.dtsi and enabling it in board file
> when the clock-frequency node is actually added.
>
> Changelog v4->v5:
> - rebased the patches on linux-next tip.
>
> Changelog v3->v4:
> - add reg property to serdes_ln_ctrl and fix the node name again to
> get rid of dtbs_check error.
> - reorder reg, reg-names and ranges property for main_cpsw1.
> - correct the order for clocks in serdes_wiz nodes to fix dtbs_check
> warnings.
> - fix indentation in reg, reg-names and clock property for dss node.
> - add comments for the reg type in dss registers.
>
> Changelog v3->v2:
> - fix dtc warnings for 'scm_conf' and 'serdes_ln_ctrl' nodes
> (Checked all the changes of the series with W=12 option during build)
> - added clock-frequency for serdes_refclk along with other EVM changes
> This refclk is being used by all the instances of serdes_wiz which
> are disabled by default. So configuring refclk when the serdes nodes
> are used for the first time is okay.
>
> Changelog v1->v2:
> - Moved J784S4 EVM changes together to the last patch
> (Suggested by Andrew)
>
> v5 patch link:
> <https://lore.kernel.org/all/[email protected]/>
>
> [1]: <https://lore.kernel.org/all/[email protected]/>
> [2]: <https://lore.kernel.org/all/[email protected]/>
>
> Rahul T R (2):
> arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
> arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
>
Could you enable AM69-SK as well? is there anything stopping it being part of the series?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Hello Nishanth,
On 29/07/23 02:42, Nishanth Menon wrote:
> On 10:38-20230728, Jayesh Choudhary wrote:
>> This series adds support for:
>> - SERDES, WIZ DT nodes, Serdes lane control mux
>> - DSS and DisplayPort-0 nodes
>>
>> This support DEPENDS upon another series which was introduced as part
>> of discussion in v5. That series[1] moves the ti-serdes headers file
>> from bindings to "arch/arm64/boot/dts/ti". (That series is merged in
>> linux-next tree)
>>
>> Changelog v6->v7:
>> - change compatible for scm_conf to 'simple-bus'
>> - drop main_cpsw node due to driver dependency on [2]
>>
[...]
>>
>> v5 patch link:
>> <https://lore.kernel.org/all/[email protected]/>
>>
>> [1]: <https://lore.kernel.org/all/[email protected]/>
>> [2]: <https://lore.kernel.org/all/[email protected]/>
>>
>> Rahul T R (2):
>> arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
>> arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
>>
>
> Could you enable AM69-SK as well? is there anything stopping it being part of the series?
>
Okay I will add support for AM69-SK too.
Thanks,
-Jayesh