2022-08-24 17:12:04

by Kuogee Hsieh

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Subject: [PATCH] drm/msm/dp: correct 1.62G link rate at dp_catalog_ctrl_config_msa()

At current implementation there is an extra 0 at 1.62G link rate which cause
no correct pixel_div selected for 1.62G link rate to calculate mvid and nvid.
This patch delete the extra 0 to have mvid and nvid be calculated correctly.

Fixes: 937f941ca06f "drm/msm/dp: Use qmp phy for DP PLL and PHY"
Signed-off-by: Kuogee Hsieh <[email protected]>
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 7257515..676279d 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -431,7 +431,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,

if (rate == link_rate_hbr3)
pixel_div = 6;
- else if (rate == 1620000 || rate == 270000)
+ else if (rate == 162000 || rate == 270000)
pixel_div = 2;
else if (rate == link_rate_hbr2)
pixel_div = 4;
--
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a Linux Foundation Collaborative Project


2022-08-24 17:48:21

by Abhinav Kumar

[permalink] [raw]
Subject: Re: [PATCH] drm/msm/dp: correct 1.62G link rate at dp_catalog_ctrl_config_msa()



On 8/24/2022 9:59 AM, Kuogee Hsieh wrote:
> At current implementation there is an extra 0 at 1.62G link rate which cause
> no correct pixel_div selected for 1.62G link rate to calculate mvid and nvid.
> This patch delete the extra 0 to have mvid and nvid be calculated correctly.
>
> Fixes: 937f941ca06f "drm/msm/dp: Use qmp phy for DP PLL and PHY"
> Signed-off-by: Kuogee Hsieh <[email protected]>
Reviewed-by: Abhinav Kumar <[email protected]>
> ---
> drivers/gpu/drm/msm/dp/dp_catalog.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
> index 7257515..676279d 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> @@ -431,7 +431,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
>
> if (rate == link_rate_hbr3)
> pixel_div = 6;
> - else if (rate == 1620000 || rate == 270000)
> + else if (rate == 162000 || rate == 270000)
> pixel_div = 2;
> else if (rate == link_rate_hbr2)
> pixel_div = 4;

2022-08-24 17:52:31

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH] drm/msm/dp: correct 1.62G link rate at dp_catalog_ctrl_config_msa()

Quoting Kuogee Hsieh (2022-08-24 09:59:16)
> At current implementation there is an extra 0 at 1.62G link rate which cause
> no correct pixel_div selected for 1.62G link rate to calculate mvid and nvid.
> This patch delete the extra 0 to have mvid and nvid be calculated correctly.
>
> Fixes: 937f941ca06f "drm/msm/dp: Use qmp phy for DP PLL and PHY"

Should be

Fixes: 937f941ca06f ("drm/msm/dp: Use qmp phy for DP PLL and PHY")

> Signed-off-by: Kuogee Hsieh <[email protected]>
> ---

Good catch! Thanks for fixing it.

Reviewed-by: Stephen Boyd <[email protected]>