2023-10-11 07:51:09

by Moudy Ho (何宗原)

[permalink] [raw]
Subject: [PATCH v7 0/3] Add support for MT8195 MDP3

Changes since v6:
- Rebase on v6.6-rc5.
- Add SoC-specific compatible string to the nodes inherited from
MT8183, such as RSZ and WROT.
- Add required property to PAD (padding) for its integration into
the existing binding under display folder.
- Add patch to standardiized DMA related node names, such as VDOSYS RDMA.

Changes since v5:
- Rebase on v6.6-rc2
- Add the required property - interrupts in components
AAL, COLOR and OVL.

Hi,

The purpose of this patch is to separate the MDP3-related dtsi from
the original mailing list mentioned below:
https://lore.kernel.org/all/[email protected]/
Introducing more components for MDP3 in MT8195.

Moudy Ho (3):
arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes
arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name
arm64: dts: mediatek: mt8195: add MDP3 nodes

arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 +-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 416 ++++++++++++++++++++++-
2 files changed, 412 insertions(+), 10 deletions(-)

--
2.18.0


2023-10-11 07:51:12

by Moudy Ho (何宗原)

[permalink] [raw]
Subject: [PATCH v7 1/3] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes

In order to generalize the node names, the DMA-related nodes
corresponding to MT8183 MDP3 need to be corrected.

Fixes: 60a2fb8d202a ("arm64: dts: mt8183: add MediaTek MDP3 nodes")
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5169779d01df..bab68c233792 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1781,7 +1781,7 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};

- mdp3-rdma0@14001000 {
+ dma-controller0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0 0x14001000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
@@ -1793,6 +1793,7 @@
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
<&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
+ #dma-cells = <1>;
};

mdp3-rsz0@14003000 {
@@ -1813,7 +1814,7 @@
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
};

- mdp3-wrot0@14005000 {
+ dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0 0x14005000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
@@ -1822,6 +1823,7 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ #dma-cells = <1>;
};

mdp3-wdma@14006000 {
--
2.18.0

2023-10-11 07:51:13

by Moudy Ho (何宗原)

[permalink] [raw]
Subject: [PATCH v7 3/3] arm64: dts: mediatek: mt8195: add MDP3 nodes

Add device nodes for Media Data Path 3 (MDP3) modules.

Signed-off-by: Moudy Ho <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 392 +++++++++++++++++++++++
1 file changed, 392 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 0bfaa6db59de..f75ed1d36343 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1960,6 +1960,115 @@
#clock-cells = <1>;
};

+ dma-controller@14001000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
+ mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
+ <&gce1 13 CMDQ_THR_PRIO_1>,
+ <&gce1 14 CMDQ_THR_PRIO_1>,
+ <&gce1 21 CMDQ_THR_PRIO_1>,
+ <&gce1 22 CMDQ_THR_PRIO_1>;
+ #dma-cells = <1>;
+ };
+
+ display@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ };
+
+ display@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ };
+
+ display@14004000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ };
+
+ display@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ display@14006000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
+ };
+
+ display@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ };
+
+ display@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ display@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>;
+ };
+
+ display@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ display@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ };
+
+ dma-controller@1400c000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x1400c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ #dma-cells = <1>;
+ };
+
mutex@1400f000 {
compatible = "mediatek,mt8195-vpp-mutex";
reg = <0 0x1400f000 0 0x1000>;
@@ -2107,6 +2216,289 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};

+ display@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f07000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ reg = <0 0x14f07000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
+ };
+
+ dma-controller@14f08000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14f08000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f09000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14f09000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f0a000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14f0a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ display@14f0b000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
+ };
+
+ display@14f0c000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
+ };
+
+ display@14f0d000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
+ };
+
+ display@14f0e000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f0e000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
+ };
+
+ display@14f0f000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f0f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
+ };
+
+ display@14f10000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f10000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
+ };
+
+ display@14f11000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f11000 0 0x1000>;
+ interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f12000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f12000 0 0x1000>;
+ interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f13000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f13000 0 0x1000>;
+ interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f14000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f14000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
+ };
+
+ display@14f15000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f15000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
+ };
+
+ display@14f16000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f16000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
+ };
+
+ display@14f17000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f17000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
+ };
+
+ display@14f18000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f18000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
+ };
+
+ display@14f19000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f19000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
+ };
+
+ display@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1b000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ reg = <0 0x14f1b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1c000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1c000 0 0x1000>;
+ interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1d000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
+ interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1e000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1e000 0 0x1000>;
+ interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1f000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ reg = <0 0x14f1f000 0 0x1000>;
+ interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>;
+ };
+
+ display@14f20000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ reg = <0 0x14f20000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f21000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ reg = <0 0x14f21000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f22000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ reg = <0 0x14f22000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ dma-controller@14f23000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f23000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f24000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f24000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f25000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f25000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
--
2.18.0

2023-10-11 07:51:31

by Moudy Ho (何宗原)

[permalink] [raw]
Subject: [PATCH v7 2/3] arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name

DMA-related nodes have their own standardized naming. Therefore,
the MT8195 VDOSYS RDMA has been unified and corrected.
Additionally, these modifications will facilitate the further
integration of bindings.

Fixes: 92d2c23dc269 ("arm64: dts: mt8195: add display node for vdosys1")
Signed-off-by: Moudy Ho <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index a9e52b50c8c4..0bfaa6db59de 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2868,7 +2868,7 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};

- vdo1_rdma0: rdma@1c104000 {
+ vdo1_rdma0: dma-controller@1c104000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c104000 0 0x1000>;
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2876,9 +2876,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ #dma-cells = <1>;
};

- vdo1_rdma1: rdma@1c105000 {
+ vdo1_rdma1: dma-controller@1c105000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c105000 0 0x1000>;
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2886,9 +2887,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ #dma-cells = <1>;
};

- vdo1_rdma2: rdma@1c106000 {
+ vdo1_rdma2: dma-controller@1c106000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c106000 0 0x1000>;
interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2896,9 +2898,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ #dma-cells = <1>;
};

- vdo1_rdma3: rdma@1c107000 {
+ vdo1_rdma3: dma-controller@1c107000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c107000 0 0x1000>;
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2906,9 +2909,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ #dma-cells = <1>;
};

- vdo1_rdma4: rdma@1c108000 {
+ vdo1_rdma4: dma-controller@1c108000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c108000 0 0x1000>;
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2916,9 +2920,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ #dma-cells = <1>;
};

- vdo1_rdma5: rdma@1c109000 {
+ vdo1_rdma5: dma-controller@1c109000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c109000 0 0x1000>;
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2926,9 +2931,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ #dma-cells = <1>;
};

- vdo1_rdma6: rdma@1c10a000 {
+ vdo1_rdma6: dma-controller@1c10a000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c10a000 0 0x1000>;
interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2936,9 +2942,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ #dma-cells = <1>;
};

- vdo1_rdma7: rdma@1c10b000 {
+ vdo1_rdma7: dma-controller@1c10b000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c10b000 0 0x1000>;
interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2946,6 +2953,7 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ #dma-cells = <1>;
};

merge1: vpp-merge@1c10c000 {
--
2.18.0

Subject: Re: [PATCH v7 2/3] arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name

Il 11/10/23 09:50, Moudy Ho ha scritto:
> DMA-related nodes have their own standardized naming. Therefore,
> the MT8195 VDOSYS RDMA has been unified and corrected.
> Additionally, these modifications will facilitate the further
> integration of bindings.
>
> Fixes: 92d2c23dc269 ("arm64: dts: mt8195: add display node for vdosys1")
> Signed-off-by: Moudy Ho <[email protected]>

Reviewed-by: AngeloGioacchino Del Regno <[email protected]>


Subject: Re: [PATCH v7 3/3] arm64: dts: mediatek: mt8195: add MDP3 nodes

Il 11/10/23 09:50, Moudy Ho ha scritto:
> Add device nodes for Media Data Path 3 (MDP3) modules.
>
> Signed-off-by: Moudy Ho <[email protected]>

On a first glance, this looks good to me, but I need the dt-bindings to
be accepted to actually be able to review this patch.

Cheers,
Angelo

> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 392 +++++++++++++++++++++++
> 1 file changed, 392 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 0bfaa6db59de..f75ed1d36343 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1960,6 +1960,115 @@
> #clock-cells = <1>;
> };
>
> + dma-controller@14001000 {
> + compatible = "mediatek,mt8195-mdp3-rdma";
> + reg = <0 0x14001000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
> + <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
> + iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
> + mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
> + <&gce1 13 CMDQ_THR_PRIO_1>,
> + <&gce1 14 CMDQ_THR_PRIO_1>,
> + <&gce1 21 CMDQ_THR_PRIO_1>,
> + <&gce1 22 CMDQ_THR_PRIO_1>;
> + #dma-cells = <1>;
> + };
> +
> + display@14002000 {
> + compatible = "mediatek,mt8195-mdp3-fg";
> + reg = <0 0x14002000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
> + };
> +
> + display@14003000 {
> + compatible = "mediatek,mt8195-mdp3-stitch";
> + reg = <0 0x14003000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_STITCH>;
> + };
> +
> + display@14004000 {
> + compatible = "mediatek,mt8195-mdp3-hdr";
> + reg = <0 0x14004000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
> + };
> +
> + display@14005000 {
> + compatible = "mediatek,mt8195-mdp3-aal";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
> + };
> +
> + display@14006000 {
> + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14006000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
> + <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
> + };
> +
> + display@14007000 {
> + compatible = "mediatek,mt8195-mdp3-tdshp";
> + reg = <0 0x14007000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
> + };
> +
> + display@14008000 {
> + compatible = "mediatek,mt8195-mdp3-color";
> + reg = <0 0x14008000 0 0x1000>;
> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
> + };
> +
> + display@14009000 {
> + compatible = "mediatek,mt8195-mdp3-ovl";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
> + iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>;
> + };
> +
> + display@1400a000 {
> + compatible = "mediatek,mt8195-mdp3-pad";
> + reg = <0 0x1400a000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_PADDING>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
> + };
> +
> + display@1400b000 {
> + compatible = "mediatek,mt8195-mdp3-tcc";
> + reg = <0 0x1400b000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
> + };
> +
> + dma-controller@1400c000 {
> + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x1400c000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
> + iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
> + #dma-cells = <1>;
> + };
> +
> mutex@1400f000 {
> compatible = "mediatek,mt8195-vpp-mutex";
> reg = <0 0x1400f000 0 0x1000>;
> @@ -2107,6 +2216,289 @@
> power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> };
>
> + display@14f06000 {
> + compatible = "mediatek,mt8195-mdp3-split";
> + reg = <0 0x14f06000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
> + <&vppsys1 CLK_VPP1_HDMI_META>,
> + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f07000 {
> + compatible = "mediatek,mt8195-mdp3-tcc";
> + reg = <0 0x14f07000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
> + };
> +
> + dma-controller@14f08000 {
> + compatible = "mediatek,mt8195-mdp3-rdma";
> + reg = <0 0x14f08000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
> + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + #dma-cells = <1>;
> + };
> +
> + dma-controller@14f09000 {
> + compatible = "mediatek,mt8195-mdp3-rdma";
> + reg = <0 0x14f09000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
> + iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + #dma-cells = <1>;
> + };
> +
> + dma-controller@14f0a000 {
> + compatible = "mediatek,mt8195-mdp3-rdma";
> + reg = <0 0x14f0a000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
> + iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + #dma-cells = <1>;
> + };
> +
> + display@14f0b000 {
> + compatible = "mediatek,mt8195-mdp3-fg";
> + reg = <0 0x14f0b000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
> + };
> +
> + display@14f0c000 {
> + compatible = "mediatek,mt8195-mdp3-fg";
> + reg = <0 0x14f0c000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
> + };
> +
> + display@14f0d000 {
> + compatible = "mediatek,mt8195-mdp3-fg";
> + reg = <0 0x14f0d000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
> + };
> +
> + display@14f0e000 {
> + compatible = "mediatek,mt8195-mdp3-hdr";
> + reg = <0 0x14f0e000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
> + };
> +
> + display@14f0f000 {
> + compatible = "mediatek,mt8195-mdp3-hdr";
> + reg = <0 0x14f0f000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
> + };
> +
> + display@14f10000 {
> + compatible = "mediatek,mt8195-mdp3-hdr";
> + reg = <0 0x14f10000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
> + };
> +
> + display@14f11000 {
> + compatible = "mediatek,mt8195-mdp3-aal";
> + reg = <0 0x14f11000 0 0x1000>;
> + interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f12000 {
> + compatible = "mediatek,mt8195-mdp3-aal";
> + reg = <0 0x14f12000 0 0x1000>;
> + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f13000 {
> + compatible = "mediatek,mt8195-mdp3-aal";
> + reg = <0 0x14f13000 0 0x1000>;
> + interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f14000 {
> + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14f14000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
> + };
> +
> + display@14f15000 {
> + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14f15000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
> + };
> +
> + display@14f16000 {
> + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14f16000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
> + };
> +
> + display@14f17000 {
> + compatible = "mediatek,mt8195-mdp3-tdshp";
> + reg = <0 0x14f17000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
> + };
> +
> + display@14f18000 {
> + compatible = "mediatek,mt8195-mdp3-tdshp";
> + reg = <0 0x14f18000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
> + };
> +
> + display@14f19000 {
> + compatible = "mediatek,mt8195-mdp3-tdshp";
> + reg = <0 0x14f19000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
> + };
> +
> + display@14f1a000 {
> + compatible = "mediatek,mt8195-mdp3-merge";
> + reg = <0 0x14f1a000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f1b000 {
> + compatible = "mediatek,mt8195-mdp3-merge";
> + reg = <0 0x14f1b000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f1c000 {
> + compatible = "mediatek,mt8195-mdp3-color";
> + reg = <0 0x14f1c000 0 0x1000>;
> + interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f1d000 {
> + compatible = "mediatek,mt8195-mdp3-color";
> + reg = <0 0x14f1d000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
> + interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f1e000 {
> + compatible = "mediatek,mt8195-mdp3-color";
> + reg = <0 0x14f1e000 0 0x1000>;
> + interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f1f000 {
> + compatible = "mediatek,mt8195-mdp3-ovl";
> + reg = <0 0x14f1f000 0 0x1000>;
> + interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>;
> + };
> +
> + display@14f20000 {
> + compatible = "mediatek,mt8195-mdp3-pad";
> + reg = <0 0x14f20000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f21000 {
> + compatible = "mediatek,mt8195-mdp3-pad";
> + reg = <0 0x14f21000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + display@14f22000 {
> + compatible = "mediatek,mt8195-mdp3-pad";
> + reg = <0 0x14f22000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + };
> +
> + dma-controller@14f23000 {
> + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x14f23000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
> + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + #dma-cells = <1>;
> + };
> +
> + dma-controller@14f24000 {
> + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x14f24000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
> + iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + #dma-cells = <1>;
> + };
> +
> + dma-controller@14f25000 {
> + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x14f25000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
> + iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + #dma-cells = <1>;
> + };
> +
> imgsys: clock-controller@15000000 {
> compatible = "mediatek,mt8195-imgsys";
> reg = <0 0x15000000 0 0x1000>;