Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
include/dt-bindings/reset/mt8195-resets.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index c87ba621e72e..5471468c43b7 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -31,6 +31,8 @@
#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
+#define MT8195_INFRA_RST2_PCIE_P0_SWRST 3
+#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4
/* VDOSYS1 */
#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0
--
2.35.1
On 29/06/2022 12:52, AngeloGioacchino Del Regno wrote:
> Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> include/dt-bindings/reset/mt8195-resets.h | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Quoting AngeloGioacchino Del Regno (2022-06-29 03:52:04)
> Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
Applied to clk-next