This series add supports for the timer block on ARTPEC-8. The block itself is
fully compatible with the existing exynos4210-mct driver. The ARTPEC-8 SoC
uses this block from two separate processors running Linux (AMP) so it needs
some extra code to allow this sharing.
v4:
- Rebase on v5.19-rc1 where all pre-requisites are merged
- Minor rework of patch 4 as requested, see patch for details
v3:
- Split and rename devicetree properties
- Add vendor prefix to devicetree properties
- Change descriptions of properties to hopefully describe hardware
- Remove addition of more global variables to the driver
v2:
- The series is now rebased on top of Krzysztof's patch "dt-bindings: timer:
exynos4210-mct: describe known hardware and its interrupts".
- Combine the Kconfig change and the local timer change into one series
- Use devicetree property rather than module parameter for the local timer handling
- Add specific compatible with the correct number of interrupts.
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Vincent Whitchurch (4):
dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support
clocksource/drivers/exynos_mct: Support frc-shared property
clocksource/drivers/exynos_mct: Support local-timers property
clocksource/drivers/exynos_mct: Enable building on ARTPEC
.../timer/samsung,exynos4210-mct.yaml | 26 ++++++
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/exynos_mct.c | 83 +++++++++++++++++--
3 files changed, 101 insertions(+), 10 deletions(-)
base-commit: f2906aa863381afb0015a9eb7fefad885d4e5a56
--
2.34.1
The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts.
The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which
share one MCT with one global and eight local timers. The Cortex-A53
and Cortex-A5 do not have cache-coherency between them, and therefore
run two separate kernels.
The Cortex-A53 boots first and starts the global free-running counter
and also registers a clock events device using the global timer. (This
global timer clock events is usually replaced by arch timer clock events
for each of the cores.)
When the A5 boots (via the A53), it should not use the global timer
interrupts or write to the global timer registers. This is because even
if there are four global comparators, the control bits for all four are
in the same registers, and we would need to synchronize between the
cpus. Instead, the global timer FRC (already started by the A53) should
be used as the clock source, and one of the local timers which are not
used by the A53 can be used for clock events on the A5.
To support this hardware, add a compatible for the MCT as well as two
new properties to describe the hardware-mandated sharing of the FRC and
dedicating local timers to specific processors.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Vincent Whitchurch <[email protected]>
---
Notes:
v4:
- Add Krzysztof's Reviewed-by.
v3:
- Add all required bindings for ARTPEC-8 in one patch
- Rename and split local-timer-only to samsung,local-timers and
samsung,frc-shared
- Restrict above properties to the ARTPEC-8 compatible.
- Rewrite descriptions of properties to hopefully describe hardware.
v2:
- Use devicetree property instead of module parameter.
.../timer/samsung,exynos4210-mct.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
index 9c81d00b12e0..829bd2227f7c 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
@@ -25,6 +25,7 @@ properties:
- samsung,exynos4412-mct
- items:
- enum:
+ - axis,artpec8-mct
- samsung,exynos3250-mct
- samsung,exynos5250-mct
- samsung,exynos5260-mct
@@ -45,6 +46,19 @@ properties:
reg:
maxItems: 1
+ samsung,frc-shared:
+ type: boolean
+ description: |
+ Indicates that the hardware requires that this processor share the
+ free-running counter with a different (main) processor.
+
+ samsung,local-timers:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 16
+ description: |
+ List of indices of local timers usable from this processor.
+
interrupts:
description: |
Interrupts should be put in specific order. This is, the local timer
@@ -74,6 +88,17 @@ required:
- reg
allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - axis,artpec8-mct
+ then:
+ properties:
+ samsung,local-timers: false
+ samsung,frc-shared: false
- if:
properties:
compatible:
@@ -101,6 +126,7 @@ allOf:
compatible:
contains:
enum:
+ - axis,artpec8-mct
- samsung,exynos5260-mct
- samsung,exynos5420-mct
- samsung,exynos5433-mct
--
2.34.1
On 09/06/2022 13:27, Vincent Whitchurch wrote:
> This series add supports for the timer block on ARTPEC-8. The block itself is
> fully compatible with the existing exynos4210-mct driver. The ARTPEC-8 SoC
> uses this block from two separate processors running Linux (AMP) so it needs
> some extra code to allow this sharing.
Applied, thanks
--
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The following commit has been merged into the timers/core branch of tip:
Commit-ID: 99b701fd2758d046d9e6ecdef1a3320d29b8b1d9
Gitweb: https://git.kernel.org/tip/99b701fd2758d046d9e6ecdef1a3320d29b8b1d9
Author: Vincent Whitchurch <[email protected]>
AuthorDate: Thu, 09 Jun 2022 13:27:35 +02:00
Committer: Daniel Lezcano <[email protected]>
CommitterDate: Tue, 20 Sep 2022 10:49:45 +02:00
dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support
The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts.
The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which
share one MCT with one global and eight local timers. The Cortex-A53
and Cortex-A5 do not have cache-coherency between them, and therefore
run two separate kernels.
The Cortex-A53 boots first and starts the global free-running counter
and also registers a clock events device using the global timer. (This
global timer clock events is usually replaced by arch timer clock events
for each of the cores.)
When the A5 boots (via the A53), it should not use the global timer
interrupts or write to the global timer registers. This is because even
if there are four global comparators, the control bits for all four are
in the same registers, and we would need to synchronize between the
cpus. Instead, the global timer FRC (already started by the A53) should
be used as the clock source, and one of the local timers which are not
used by the A53 can be used for clock events on the A5.
To support this hardware, add a compatible for the MCT as well as two
new properties to describe the hardware-mandated sharing of the FRC and
dedicating local timers to specific processors.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Vincent Whitchurch <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Daniel Lezcano <[email protected]>
---
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
index 9c81d00..829bd22 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
@@ -25,6 +25,7 @@ properties:
- samsung,exynos4412-mct
- items:
- enum:
+ - axis,artpec8-mct
- samsung,exynos3250-mct
- samsung,exynos5250-mct
- samsung,exynos5260-mct
@@ -45,6 +46,19 @@ properties:
reg:
maxItems: 1
+ samsung,frc-shared:
+ type: boolean
+ description: |
+ Indicates that the hardware requires that this processor share the
+ free-running counter with a different (main) processor.
+
+ samsung,local-timers:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 16
+ description: |
+ List of indices of local timers usable from this processor.
+
interrupts:
description: |
Interrupts should be put in specific order. This is, the local timer
@@ -75,6 +89,17 @@ required:
allOf:
- if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - axis,artpec8-mct
+ then:
+ properties:
+ samsung,local-timers: false
+ samsung,frc-shared: false
+ - if:
properties:
compatible:
contains:
@@ -101,6 +126,7 @@ allOf:
compatible:
contains:
enum:
+ - axis,artpec8-mct
- samsung,exynos5260-mct
- samsung,exynos5420-mct
- samsung,exynos5433-mct