Update the hardcoded masks with the GENMASK macro. Also update some of
the hardcoded bits with the BIT macro
Signed-off-by: Dan Murphy <[email protected]>
---
sound/soc/codecs/tas2770.h | 37 +++++++++++++++++++------------------
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/sound/soc/codecs/tas2770.h b/sound/soc/codecs/tas2770.h
index 96683971ee9b..07e3556fc702 100644
--- a/sound/soc/codecs/tas2770.h
+++ b/sound/soc/codecs/tas2770.h
@@ -19,7 +19,7 @@
#define TAS2770_RST BIT(0)
/* Power Control */
#define TAS2770_PWR_CTRL TAS2770_REG(0X0, 0x02)
-#define TAS2770_PWR_CTRL_MASK 0x3
+#define TAS2770_PWR_CTRL_MASK GENMASK(1, 0)
#define TAS2770_PWR_CTRL_ACTIVE 0x0
#define TAS2770_PWR_CTRL_MUTE BIT(0)
#define TAS2770_PWR_CTRL_SHUTDOWN 0x2
@@ -37,43 +37,43 @@
#define TAS2770_TDM_CFG_REG0_SMP_MASK BIT(5)
#define TAS2770_TDM_CFG_REG0_SMP_48KHZ 0x0
#define TAS2770_TDM_CFG_REG0_SMP_44_1KHZ BIT(5)
-#define TAS2770_TDM_CFG_REG0_31_MASK 0xe
+#define TAS2770_TDM_CFG_REG0_31_MASK GENMASK(3, 1)
#define TAS2770_TDM_CFG_REG0_31_44_1_48KHZ 0x6
#define TAS2770_TDM_CFG_REG0_31_88_2_96KHZ 0x8
#define TAS2770_TDM_CFG_REG0_31_176_4_192KHZ 0xa
/* TDM Configuration Reg1 */
#define TAS2770_TDM_CFG_REG1 TAS2770_REG(0X0, 0x0B)
-#define TAS2770_TDM_CFG_REG1_MASK 0x3e
+#define TAS2770_TDM_CFG_REG1_MASK GENMASK(5, 1)
#define TAS2770_TDM_CFG_REG1_51_SHIFT 1
#define TAS2770_TDM_CFG_REG1_RX_MASK BIT(0)
#define TAS2770_TDM_CFG_REG1_RX_RSING 0x0
#define TAS2770_TDM_CFG_REG1_RX_FALING BIT(0)
/* TDM Configuration Reg2 */
#define TAS2770_TDM_CFG_REG2 TAS2770_REG(0X0, 0x0C)
-#define TAS2770_TDM_CFG_REG2_RXW_MASK 0xc
+#define TAS2770_TDM_CFG_REG2_RXW_MASK GENMASK(3, 2)
#define TAS2770_TDM_CFG_REG2_RXW_16BITS 0x0
#define TAS2770_TDM_CFG_REG2_RXW_24BITS 0x8
#define TAS2770_TDM_CFG_REG2_RXW_32BITS 0xc
-#define TAS2770_TDM_CFG_REG2_RXS_MASK 0x3
+#define TAS2770_TDM_CFG_REG2_RXS_MASK GENMASK(1, 0)
#define TAS2770_TDM_CFG_REG2_RXS_16BITS 0x0
#define TAS2770_TDM_CFG_REG2_RXS_24BITS BIT(0)
#define TAS2770_TDM_CFG_REG2_RXS_32BITS 0x2
/* TDM Configuration Reg3 */
#define TAS2770_TDM_CFG_REG3 TAS2770_REG(0X0, 0x0D)
-#define TAS2770_TDM_CFG_REG3_RXS_MASK 0xf0
+#define TAS2770_TDM_CFG_REG3_RXS_MASK GENMASK(7, 4)
#define TAS2770_TDM_CFG_REG3_RXS_SHIFT 0x4
-#define TAS2770_TDM_CFG_REG3_30_MASK 0xf
+#define TAS2770_TDM_CFG_REG3_30_MASK GENMASK(3, 0)
#define TAS2770_TDM_CFG_REG3_30_SHIFT 0
/* TDM Configuration Reg5 */
#define TAS2770_TDM_CFG_REG5 TAS2770_REG(0X0, 0x0F)
#define TAS2770_TDM_CFG_REG5_VSNS_MASK BIT(6)
#define TAS2770_TDM_CFG_REG5_VSNS_ENABLE BIT(6)
-#define TAS2770_TDM_CFG_REG5_50_MASK 0x3f
+#define TAS2770_TDM_CFG_REG5_50_MASK GENMASK(5, 0)
/* TDM Configuration Reg6 */
#define TAS2770_TDM_CFG_REG6 TAS2770_REG(0X0, 0x10)
#define TAS2770_TDM_CFG_REG6_ISNS_MASK BIT(6)
#define TAS2770_TDM_CFG_REG6_ISNS_ENABLE BIT(6)
-#define TAS2770_TDM_CFG_REG6_50_MASK 0x3f
+#define TAS2770_TDM_CFG_REG6_50_MASK GENMASK(5, 0)
/* Brown Out Prevention Reg0 */
#define TAS2770_BO_PRV_REG0 TAS2770_REG(0X0, 0x1B)
/* Interrupt MASK Reg0 */
@@ -116,15 +116,16 @@
/* Revision and PG ID */
#define TAS2770_REV_AND_GPID TAS2770_REG(0X0, 0x7D)
-#define TAS2770_POWER_ACTIVE 0
-#define TAS2770_POWER_MUTE 1
-#define TAS2770_POWER_SHUTDOWN 2
-#define ERROR_OVER_CURRENT 0x0000001
-#define ERROR_DIE_OVERTEMP 0x0000002
-#define ERROR_OVER_VOLTAGE 0x0000004
-#define ERROR_UNDER_VOLTAGE 0x0000008
-#define ERROR_BROWNOUT 0x0000010
-#define ERROR_CLASSD_PWR 0x0000020
+#define TAS2770_POWER_ACTIVE 0
+#define TAS2770_POWER_MUTE BIT(0)
+#define TAS2770_POWER_SHUTDOWN BIT(1)
+
+#define ERROR_OVER_CURRENT BIT(0)
+#define ERROR_DIE_OVERTEMP BIT(1)
+#define ERROR_OVER_VOLTAGE BIT(2)
+#define ERROR_UNDER_VOLTAGE BIT(3)
+#define ERROR_BROWNOUT BIT(4)
+#define ERROR_CLASSD_PWR BIT(5)
struct tas2770_priv {
struct device *dev;
--
2.28.0
On Fri, Sep 18, 2020 at 02:05:45PM -0500, Dan Murphy wrote:
> Update the hardcoded masks with the GENMASK macro. Also update some of
> the hardcoded bits with the BIT macro
Cleanups like this should come after any fixes in the series, that way
fixes can be sent as fixes if needed which isn't appropriate for random
cleanups.
Mark
On 9/21/20 2:04 PM, Mark Brown wrote:
> On Fri, Sep 18, 2020 at 02:05:45PM -0500, Dan Murphy wrote:
>> Update the hardcoded masks with the GENMASK macro. Also update some of
>> the hardcoded bits with the BIT macro
> Cleanups like this should come after any fixes in the series, that way
> fixes can be sent as fixes if needed which isn't appropriate for random
> cleanups.
OK I can re-order so the clean up comes at the end.? During the clean up
I found patch 7-9.
Dan
Mark
On 9/21/20 2:18 PM, Dan Murphy wrote:
> Mark
>
> On 9/21/20 2:04 PM, Mark Brown wrote:
>> On Fri, Sep 18, 2020 at 02:05:45PM -0500, Dan Murphy wrote:
>>> Update the hardcoded masks with the GENMASK macro. Also update some of
>>> the hardcoded bits with the BIT macro
>> Cleanups like this should come after any fixes in the series, that way
>> fixes can be sent as fixes if needed which isn't appropriate for random
>> cleanups.
>
> OK I can re-order so the clean up comes at the end.? During the clean
> up I found patch 7-9.
>
Forgot to ask are you going to take 1-5? If so I can rebase on top of
for-5.10 and re-submit.
Dan
> Dan
>
On Mon, Sep 21, 2020 at 02:19:36PM -0500, Dan Murphy wrote:
> Forgot to ask are you going to take 1-5? If so I can rebase on top of
> for-5.10 and re-submit.
I think managed to apply everything with manual picking things, there
weren't any actual dependencies.