APSS PLL found in IPQ9574 platform is of type Huayra.
This series adds support for the APSS clock to bump the CPU frequency
above 800MHz.
DTS patch is based on the below series
https://lore.kernel.org/linux-arm-msm/[email protected]/
[V3]:
- Detailed change logs are added to the respective patches
[V2]:
https://lore.kernel.org/linux-arm-msm/[email protected]/
- Reordered the patches as suggested
- Dropped [PATCH 6/6] clk: qcom: Fix APSS PLL and RCG Configuration
as it was unrelated
- Detailed Change logs are added to the respective patches
[V1]:
https://lore.kernel.org/linux-arm-msm/[email protected]/
Devi Priya (5):
dt-bindings: clock: qcom,a53pll: add IPQ9574 compatible
clk: qcom: apss-ipq-pll: Add support for IPQ9574
dt-bindings: mailbox: qcom: add compatible for IPQ9574 SoC
arm64: dts: qcom: ipq9574: Add support for APSS clock controller
arm64: defconfig: Enable ipq6018 apss clock and PLL controller
.../bindings/clock/qcom,a53pll.yaml | 1 +
.../mailbox/qcom,apcs-kpss-global.yaml | 1 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
5 files changed, 40 insertions(+)
base-commit: 8417c8f5007bf4567ccffda850a3157c7d905f67
--
2.17.1
Add the compatible and configuration values for A73 Huayra PLL found
on IPQ9574.
Co-developed-by: Praveenkumar I <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- Updated the subject and aligned the commit message
drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index cf4f0d340cbf..ce28d882ee78 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
.test_ctl_hi_val = 0x4000,
};
+static const struct alpha_pll_config ipq9574_pll_config = {
+ .l = 0x3b,
+ .config_ctl_val = 0x200d4828,
+ .config_ctl_hi_val = 0x6,
+ .early_output_mask = BIT(3),
+ .aux2_output_mask = BIT(2),
+ .aux_output_mask = BIT(1),
+ .main_output_mask = BIT(0),
+ .test_ctl_val = 0x0,
+ .test_ctl_hi_val = 0x4000,
+};
+
struct apss_pll_data {
int pll_type;
struct clk_alpha_pll *pll;
@@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
.pll_config = &ipq6018_pll_config,
};
+static struct apss_pll_data ipq9574_pll_data = {
+ .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
+ .pll = &ipq_pll_huayra,
+ .pll_config = &ipq9574_pll_config,
+};
+
static const struct regmap_config ipq_pll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
+ { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
{ }
};
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
--
2.17.1
IPQ9574 uses A73 PLL of type Huayra. Add the IPQ9574 A73 compatible to A53
bindings as the PLL properties match with that of A53.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- picked up the Acked-by tag
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
index 659669bf224b..9436266828af 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
@@ -19,6 +19,7 @@ properties:
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
+ - qcom,ipq9574-a73pll
- qcom,msm8916-a53pll
- qcom,msm8939-a53pll
--
2.17.1
Add the APCS & A73 PLL nodes to support CPU frequency scaling.
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- No change
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 068c3950dcec..7c820463a79d 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -525,6 +525,24 @@
timeout-sec = <30>;
};
+ apcs_glb: mailbox@b111000 {
+ compatible = "qcom,ipq9574-apcs-apps-global",
+ "qcom,ipq6018-apcs-apps-global";
+ reg = <0x0b111000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&a73pll>, <&xo_board_clk>;
+ clock-names = "pll", "xo";
+ #mbox-cells = <1>;
+ };
+
+ a73pll: clock@b116000 {
+ compatible = "qcom,ipq9574-a73pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo_board_clk>;
+ clock-names = "xo";
+ };
+
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
--
2.17.1
The PLL and IPQ6018 APSS clock controller are used on several
IPQ platforms to clock the CPU. Hence it should be enabled and built-in.
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- No change
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 8f24c280dec2..27dc617ec296 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1153,6 +1153,7 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y
CONFIG_QCOM_CLK_APCC_MSM8996=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
+CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_GCC_5332=y
CONFIG_IPQ_GCC_6018=y
CONFIG_IPQ_GCC_8074=y
--
2.17.1
Add the mailbox compatible for IPQ9574 SoC.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- picked up the Acked-by tag
.../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 8f924bb4c583..c5f56c197cd4 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- qcom,ipq5332-apcs-apps-global
+ - qcom,ipq9574-apcs-apps-global
- const: qcom,ipq6018-apcs-apps-global
- items:
- enum:
--
2.17.1
On 6.04.2023 08:13, Devi Priya wrote:
> Add the compatible and configuration values for A73 Huayra PLL found
> on IPQ9574.
>
> Co-developed-by: Praveenkumar I <[email protected]>
> Signed-off-by: Praveenkumar I <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> Changes in V3:
> - Updated the subject and aligned the commit message
>
> drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
> index cf4f0d340cbf..ce28d882ee78 100644
> --- a/drivers/clk/qcom/apss-ipq-pll.c
> +++ b/drivers/clk/qcom/apss-ipq-pll.c
> @@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
> .test_ctl_hi_val = 0x4000,
> };
>
> +static const struct alpha_pll_config ipq9574_pll_config = {
> + .l = 0x3b,
> + .config_ctl_val = 0x200d4828,
> + .config_ctl_hi_val = 0x6,
> + .early_output_mask = BIT(3),
> + .aux2_output_mask = BIT(2),
> + .aux_output_mask = BIT(1),
> + .main_output_mask = BIT(0),
> + .test_ctl_val = 0x0,
> + .test_ctl_hi_val = 0x4000,
> +};
> +
> struct apss_pll_data {
> int pll_type;
> struct clk_alpha_pll *pll;
> @@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
> .pll_config = &ipq6018_pll_config,
> };
>
> +static struct apss_pll_data ipq9574_pll_data = {
> + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
> + .pll = &ipq_pll_huayra,
> + .pll_config = &ipq9574_pll_config,
> +};
> +
> static const struct regmap_config ipq_pll_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> @@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
> { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
> { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
> { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
> + { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
> { }
> };
> MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
On 6.04.2023 08:13, Devi Priya wrote:
> Add the APCS & A73 PLL nodes to support CPU frequency scaling.
>
> Signed-off-by: Devi Priya <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> Changes in V3:
> - No change
>
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 068c3950dcec..7c820463a79d 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -525,6 +525,24 @@
> timeout-sec = <30>;
> };
>
> + apcs_glb: mailbox@b111000 {
> + compatible = "qcom,ipq9574-apcs-apps-global",
> + "qcom,ipq6018-apcs-apps-global";
> + reg = <0x0b111000 0x1000>;
> + #clock-cells = <1>;
> + clocks = <&a73pll>, <&xo_board_clk>;
> + clock-names = "pll", "xo";
> + #mbox-cells = <1>;
> + };
> +
> + a73pll: clock@b116000 {
> + compatible = "qcom,ipq9574-a73pll";
> + reg = <0x0b116000 0x40>;
> + #clock-cells = <0>;
> + clocks = <&xo_board_clk>;
> + clock-names = "xo";
> + };
> +
> timer@b120000 {
> compatible = "arm,armv7-timer-mem";
> reg = <0x0b120000 0x1000>;
On 6.04.2023 08:13, Devi Priya wrote:
> The PLL and IPQ6018 APSS clock controller are used on several
> IPQ platforms to clock the CPU. Hence it should be enabled and built-in.
>
> Signed-off-by: Devi Priya <[email protected]>
> ---
Acked-by: Konrad Dybcio <[email protected]>
Konrad
> Changes in V3:
> - No change
>
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 8f24c280dec2..27dc617ec296 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1153,6 +1153,7 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y
> CONFIG_QCOM_CLK_APCC_MSM8996=y
> CONFIG_QCOM_CLK_SMD_RPM=y
> CONFIG_QCOM_CLK_RPMH=y
> +CONFIG_IPQ_APSS_6018=y
> CONFIG_IPQ_GCC_5332=y
> CONFIG_IPQ_GCC_6018=y
> CONFIG_IPQ_GCC_8074=y
Quoting Devi Priya (2023-04-05 23:13:11)
> Add the compatible and configuration values for A73 Huayra PLL found
> on IPQ9574.
>
> Co-developed-by: Praveenkumar I <[email protected]>
> Signed-off-by: Praveenkumar I <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
Acked-by: Stephen Boyd <[email protected]>
Quoting Devi Priya (2023-04-05 23:13:10)
> IPQ9574 uses A73 PLL of type Huayra. Add the IPQ9574 A73 compatible to A53
> bindings as the PLL properties match with that of A53.
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
Acked-by: Stephen Boyd <[email protected]>
On Thu, 6 Apr 2023 11:43:09 +0530, Devi Priya wrote:
> APSS PLL found in IPQ9574 platform is of type Huayra.
> This series adds support for the APSS clock to bump the CPU frequency
> above 800MHz.
>
> DTS patch is based on the below series
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> [...]
Applied, thanks!
[5/5] arm64: defconfig: Enable ipq6018 apss clock and PLL controller
commit: 3098f34977480c9aa75cf328501f1b47ec49fec7
Best regards,
--
Bjorn Andersson <[email protected]>
On 5/27/2023 1:08 AM, Bjorn Andersson wrote:
> On Thu, 6 Apr 2023 11:43:09 +0530, Devi Priya wrote:
>> APSS PLL found in IPQ9574 platform is of type Huayra.
>> This series adds support for the APSS clock to bump the CPU frequency
>> above 800MHz.
>>
>> DTS patch is based on the below series
>> https://lore.kernel.org/linux-arm-msm/[email protected]/
>>
>> [...]
>
Thanks! To update on the dependency, This series does not hold any
dependencies as the DTS patch cleanly applies on [1] which has already
been picked up for linux-next.
[PATCH V3 4/5] arm64: dts: qcom: ipq9574: Add support for APSS clock
controller
[1] -
https://lore.kernel.org/linux-arm-msm/[email protected]/
> Applied, thanks!
>
> [5/5] arm64: defconfig: Enable ipq6018 apss clock and PLL controller
> commit: 3098f34977480c9aa75cf328501f1b47ec49fec7
>
> Best regards,