From: Xingui Yang <[email protected]>
On Hisilicon Kunpeng920, ESP is set to 1 by default for all ports of
SATA controller. In some scenarios, some ports are not external SATA ports,
and it cause disks connected to these ports to be identified as removable
disks. So disable the SXS capability on the software side to prevent users
from mistakenly considering non-removable disks as removable disks and
performing related operations.
Signed-off-by: Xingui Yang <[email protected]>
Signed-off-by: Luo Jiaxing <[email protected]>
Reviewed-by: John Garry <[email protected]>
---
drivers/ata/ahci.c | 5 +++++
drivers/ata/ahci.h | 1 +
drivers/ata/libahci.c | 5 +++++
3 files changed, 11 insertions(+)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 00ba8e5..33192a8 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1772,6 +1772,11 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
#ifdef CONFIG_ARM64
+ if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
+ pdev->device == 0xa235 &&
+ pdev->revision < 0x30)
+ hpriv->flags |= AHCI_HFLAG_NO_SXS;
+
if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
hpriv->irq_handler = ahci_thunderx_irq_handler;
#endif
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 98b8baa..d1f284f 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -242,6 +242,7 @@ enum {
suspend/resume */
AHCI_HFLAG_IGN_NOTSUPP_POWER_ON = (1 << 27), /* ignore -EOPNOTSUPP
from phy_power_on() */
+ AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */
/* ap->flags bits */
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index ea5bf5f..fec2e97 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -493,6 +493,11 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
cap |= HOST_CAP_ALPM;
}
+ if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
+ dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
+ cap &= ~HOST_CAP_SXS;
+ }
+
if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
port_map, hpriv->force_port_map);
--
2.7.4
On 3/12/21 3:24 AM, Luo Jiaxing wrote:
> From: Xingui Yang <[email protected]>
>
> On Hisilicon Kunpeng920, ESP is set to 1 by default for all ports of
> SATA controller. In some scenarios, some ports are not external SATA ports,
> and it cause disks connected to these ports to be identified as removable
> disks. So disable the SXS capability on the software side to prevent users
> from mistakenly considering non-removable disks as removable disks and
> performing related operations.
>
> Signed-off-by: Xingui Yang <[email protected]>
> Signed-off-by: Luo Jiaxing <[email protected]>
> Reviewed-by: John Garry <[email protected]>
> ---
> drivers/ata/ahci.c | 5 +++++
> drivers/ata/ahci.h | 1 +
> drivers/ata/libahci.c | 5 +++++
> 3 files changed, 11 insertions(+)
>
> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> index 00ba8e5..33192a8 100644
> --- a/drivers/ata/ahci.c
> +++ b/drivers/ata/ahci.c
> @@ -1772,6 +1772,11 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
> hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
>
> #ifdef CONFIG_ARM64
> + if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
> + pdev->device == 0xa235 &&
> + pdev->revision < 0x30)
> + hpriv->flags |= AHCI_HFLAG_NO_SXS;
Is this controller arm exclusive?
--
Jens Axboe
On 2021/3/12 22:27, Jens Axboe wrote:
> Is this controller arm exclusive?
Yes, our SoC is base on ARM64 only.
Thanks
Jiaxing
kindly ping.
Hi, Jens, are there any further comments from you?
Two weeks from your first comment now.
And it's a bugfix for our SoC, So the customer is asking whether this
patch is merged or not.
They want to pull back.
Thanks
Jiaxing
On 2021/3/12 18:24, Luo Jiaxing wrote:
> From: Xingui Yang <[email protected]>
>
> On Hisilicon Kunpeng920, ESP is set to 1 by default for all ports of
> SATA controller. In some scenarios, some ports are not external SATA ports,
> and it cause disks connected to these ports to be identified as removable
> disks. So disable the SXS capability on the software side to prevent users
> from mistakenly considering non-removable disks as removable disks and
> performing related operations.
>
> Signed-off-by: Xingui Yang <[email protected]>
> Signed-off-by: Luo Jiaxing <[email protected]>
> Reviewed-by: John Garry <[email protected]>
> ---
> drivers/ata/ahci.c | 5 +++++
> drivers/ata/ahci.h | 1 +
> drivers/ata/libahci.c | 5 +++++
> 3 files changed, 11 insertions(+)
>
> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> index 00ba8e5..33192a8 100644
> --- a/drivers/ata/ahci.c
> +++ b/drivers/ata/ahci.c
> @@ -1772,6 +1772,11 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
> hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
>
> #ifdef CONFIG_ARM64
> + if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
> + pdev->device == 0xa235 &&
> + pdev->revision < 0x30)
> + hpriv->flags |= AHCI_HFLAG_NO_SXS;
> +
> if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
> hpriv->irq_handler = ahci_thunderx_irq_handler;
> #endif
> diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
> index 98b8baa..d1f284f 100644
> --- a/drivers/ata/ahci.h
> +++ b/drivers/ata/ahci.h
> @@ -242,6 +242,7 @@ enum {
> suspend/resume */
> AHCI_HFLAG_IGN_NOTSUPP_POWER_ON = (1 << 27), /* ignore -EOPNOTSUPP
> from phy_power_on() */
> + AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */
>
> /* ap->flags bits */
>
> diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
> index ea5bf5f..fec2e97 100644
> --- a/drivers/ata/libahci.c
> +++ b/drivers/ata/libahci.c
> @@ -493,6 +493,11 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
> cap |= HOST_CAP_ALPM;
> }
>
> + if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
> + dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
> + cap &= ~HOST_CAP_SXS;
> + }
> +
> if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
> dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
> port_map, hpriv->force_port_map);
On 3/15/21 5:29 AM, luojiaxing wrote:
>
> On 2021/3/12 22:27, Jens Axboe wrote:
>> Is this controller arm exclusive?
>
>
> Yes, our SoC is base on ARM64 only.
Applied, thanks.
--
Jens Axboe