Hi,
We follow-up the platform support series for Mobileye EyeQ5 [1] with
this reset controller patch series.
The registers are located in a shared register region called OLB
("Other Logic Block"). A single driver instance handles the three
existing reset domains, each with their custom logic:
- We busy-wait on the first two for hardware LBIST reasons (logic
built-in self-test).
- Domains 0 & 2 work in a bit-per-reset fashion while domain 1 works in
a register-per-reset fashion.
We end the series by adding the node to the platform devicetree and
reset handles to the three UARTs.
[1]: https://lore.kernel.org/lkml/[email protected]/
Have a nice day,
Théo Lebrun
Signed-off-by: Théo Lebrun <[email protected]>
---
Théo Lebrun (4):
dt-bindings: reset: mobileye,eyeq5-reset: add bindings
reset: eyeq5: add driver
MIPS: mobileye: eyeq5: add OLB reset controller node
MIPS: mobileye: eyeq5: add reset properties to uarts
.../bindings/reset/mobileye,eyeq5-reset.yaml | 69 +++++
MAINTAINERS | 3 +
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 9 +
drivers/reset/Kconfig | 13 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-eyeq5.c | 323 +++++++++++++++++++++
include/dt-bindings/reset/mobileye,eyeq5-reset.h | 80 +++++
7 files changed, 498 insertions(+)
---
base-commit: 0bb6b85cadabf93a754df740bd1b6c56ef41ac2c
change-id: 20231023-mbly-reset-b587dac68d0b
Best regards,
--
Théo Lebrun <[email protected]>
Add DT-Schema bindings for the EyeQ5 reset controller.
Signed-off-by: Théo Lebrun <[email protected]>
---
.../bindings/reset/mobileye,eyeq5-reset.yaml | 69 +++++++++++++++++++
MAINTAINERS | 2 +
include/dt-bindings/reset/mobileye,eyeq5-reset.h | 80 ++++++++++++++++++++++
3 files changed, 151 insertions(+)
diff --git a/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml b/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml
new file mode 100644
index 000000000000..cab6a75ba59d
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ5 reset controller
+
+description:
+ The EyeQ5 reset driver handles three reset domains. It is custom to this
+ platform, its registers live in a shared region called OLB.
+
+maintainers:
+ - Grégory Clement <[email protected]>
+ - Théo Lebrun <[email protected]>
+ - Vladimir Kondratiev <[email protected]>
+
+properties:
+ $nodename:
+ pattern: "^reset-controller$"
+ description:
+ We have no unique address, we rely on OLB.
+
+ compatible:
+ const: mobileye,eyeq5-reset
+
+ "#reset-cells":
+ const: 2
+ description:
+ The first cell is the domain (0 to 2 inclusive) and the second one is the
+ reset index inside that domain.
+
+ mobileye,olb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ A phandle to the OLB syscon. This is a fallback to using the parent as
+ syscon node.
+
+required:
+ - compatible
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ olb@e00000 {
+ compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
+ reg = <0xe00000 0x400>;
+ reg-io-width = <4>;
+
+ reset-controller {
+ compatible = "mobileye,eyeq5-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ - |
+ olb: olb@e00000 {
+ compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
+ reg = <0xe00000 0x400>;
+ reg-io-width = <4>;
+ };
+
+ reset-controller {
+ compatible = "mobileye,eyeq5-reset";
+ #reset-cells = <2>;
+ mobileye,olb = <&olb>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 4a7bd6b40d74..9096a940b425 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14553,9 +14553,11 @@ M: Théo Lebrun <[email protected]>
L: [email protected]
S: Maintained
F: Documentation/devicetree/bindings/mips/mobileye.yaml
+F: Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml
F: arch/mips/boot/dts/mobileye/
F: arch/mips/configs/generic/board-eyeq5.config
F: arch/mips/generic/board-epm5.its.S
+F: include/dt-bindings/reset/mobileye,eyeq5-reset.h
F: include/dt-bindings/soc/mobileye,eyeq5.h
MODULE SUPPORT
diff --git a/include/dt-bindings/reset/mobileye,eyeq5-reset.h b/include/dt-bindings/reset/mobileye,eyeq5-reset.h
new file mode 100644
index 000000000000..ce59fe5409ac
--- /dev/null
+++ b/include/dt-bindings/reset/mobileye,eyeq5-reset.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Mobileye Vision Technologies Ltd.
+ */
+
+#ifndef _DT_BINDINGS_RESET_MOBILEYE_EYEQ5_RESET_H
+#define _DT_BINDINGS_RESET_MOBILEYE_EYEQ5_RESET_H
+
+/* Domain 0 */
+
+/* 0..2 are reserved */
+#define EQ5R_D0_CAN0 3
+#define EQ5R_D0_CAN1 4
+#define EQ5R_D0_CAN2 5
+#define EQ5R_D0_SPI0 6
+#define EQ5R_D0_SPI1 7
+#define EQ5R_D0_SPI2 8
+#define EQ5R_D0_SPI3 9
+#define EQ5R_D0_UART0 10
+#define EQ5R_D0_UART1 11
+#define EQ5R_D0_UART2 12
+#define EQ5R_D0_I2C0 13
+#define EQ5R_D0_I2C1 14
+#define EQ5R_D0_I2C2 15
+#define EQ5R_D0_I2C3 16
+#define EQ5R_D0_I2C4 17
+#define EQ5R_D0_TIMER0 18
+#define EQ5R_D0_TIMER1 19
+#define EQ5R_D0_TIMER2 20
+#define EQ5R_D0_TIMER3 21
+#define EQ5R_D0_TIMER4 22
+#define EQ5R_D0_WD0 23
+#define EQ5R_D0_EXT0 24
+#define EQ5R_D0_EXT1 25
+#define EQ5R_D0_GPIO 26
+#define EQ5R_D0_WD1 27
+/* 28..31 are reserved */
+
+/* Domain 1 */
+
+/* Vector Microcode Processors */
+#define EQ5R_D1_VMP0 0
+#define EQ5R_D1_VMP1 1
+#define EQ5R_D1_VMP2 2
+#define EQ5R_D1_VMP3 3
+/* Programmable Macro Array */
+#define EQ5R_D1_PMA0 4
+#define EQ5R_D1_PMA1 5
+#define EQ5R_D1_PMAC0 6
+#define EQ5R_D1_PMAC1 7
+/* Multi-threaded Processing Clusters */
+#define EQ5R_D1_MPC0 8
+#define EQ5R_D1_MPC1 9
+
+/* Domain 2 */
+
+#define EQ5R_D2_PCIE0_CORE_SWRST_DIS 0
+#define EQ5R_D2_PCIE0_APB_SWRST_DIS 1
+#define EQ5R_D2_PCIE0_LINK_AXI_RST_DIS 2
+#define EQ5R_D2_PCIE0_LINK_MGMT_RST_DIS 3
+#define EQ5R_D2_PCIE0_LINK_HOT_RST_DIS 4
+#define EQ5R_D2_PCIE0_LINK_PIPE_RST_DIS 5
+
+#define EQ5R_D2_PCIE1_CORE_SWRST_DIS 6
+#define EQ5R_D2_PCIE1_APB_SWRST_DIS 7
+#define EQ5R_D2_PCIE1_LINK_AXI_RST_DIS 8
+#define EQ5R_D2_PCIE1_LINK_MGMT_RST_DIS 9
+#define EQ5R_D2_PCIE1_LINK_HOT_RST_DIS 10
+#define EQ5R_D2_PCIE1_LINK_PIPE_RST_DIS 11
+
+#define EQ5R_D2_MULTIPHY_SWRST_DIS 12
+#define EQ5R_D2_MULTIPHY_APB_RST_DIS 13
+/* 14 is refclk select, ie not a reset */
+#define EQ5R_D2_PCIE0_LINK_MGMT_RST 15
+#define EQ5R_D2_PCIE1_LINK_MGMT_RST 16
+#define EQ5R_D2_PCIE0_LINK_PM_RST 17
+#define EQ5R_D2_PCIE1_LINK_PM_RST 18
+/* 19..31 are unknown */
+
+#endif
--
2.43.0
Add the Mobileye EyeQ5 reset controller driver. See the header comment
for more information on how it works. This driver is specific to this
platform; it might grow to add later support of other platforms from
Mobileye.
Signed-off-by: Théo Lebrun <[email protected]>
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 13 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-eyeq5.c | 323 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 338 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9096a940b425..138e0303c5da 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14557,6 +14557,7 @@ F: Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml
F: arch/mips/boot/dts/mobileye/
F: arch/mips/configs/generic/board-eyeq5.config
F: arch/mips/generic/board-epm5.its.S
+F: drivers/reset/reset-eyeq5.c
F: include/dt-bindings/reset/mobileye,eyeq5-reset.h
F: include/dt-bindings/soc/mobileye,eyeq5.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index ccd59ddd7610..488f2f38a2e2 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -66,6 +66,19 @@ config RESET_BRCMSTB_RESCAL
This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
BCM7216.
+config RESET_EYEQ5
+ bool "Mobileye EyeQ5 reset controller"
+ depends on MFD_SYSCON
+ depends on SOC_EYEQ5 || COMPILE_TEST
+ default SOC_EYEQ5
+ help
+ This enables the Mobileye EyeQ5 reset controller; a custom IP block
+ for this platform.
+
+ It has three domains, with a varying number of resets in each of them.
+ Registers are located in a shared register region called OLB accessed
+ through a syscon & regmap.
+
config RESET_HSDK
bool "Synopsys HSDK Reset Driver"
depends on HAS_IOMEM
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 8270da8a4baa..4fabe0070390 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
+obj-$(CONFIG_RESET_EYEQ5) += reset-eyeq5.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
diff --git a/drivers/reset/reset-eyeq5.c b/drivers/reset/reset-eyeq5.c
new file mode 100644
index 000000000000..45bb330f35ed
--- /dev/null
+++ b/drivers/reset/reset-eyeq5.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Reset driver for the Mobileye EyeQ5 platform.
+ *
+ * The registers are located in a syscon region called OLB. We handle three
+ * reset domains. Domains 0 and 2 look similar in that they both use one bit
+ * per reset line. Domain 1 has a register per reset.
+ *
+ * We busy-wait after updating a reset in domains 0 or 1. The reason is hardware
+ * logic built-in self-test (LBIST) that might be enabled.
+ *
+ * We use eq5r_ as prefix, as-in "EyeQ5 Reset", but way shorter.
+ *
+ * Copyright (C) 2023 Mobileye Vision Technologies Ltd.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/mutex.h>
+
+/* Offsets into the OLB region as well as masks for domain 1 registers. */
+#define EQ5R_OLB_SARCR0 (0x004)
+#define EQ5R_OLB_SARCR1 (0x008)
+#define EQ5R_OLB_PCIE_GP (0x120)
+#define EQ5R_OLB_ACRP_REG(n) (0x200 + 4 * (n)) // n=0..12
+#define EQ5R_OLB_ACRP_PD_REQ BIT(0)
+#define EQ5R_OLB_ACRP_ST_POWER_DOWN BIT(27)
+#define EQ5R_OLB_ACRP_ST_ACTIVE BIT(29)
+
+/* Vendor-provided values. D1 has a long timeout because of LBIST. */
+#define D0_TIMEOUT_POLL 10
+#define D1_TIMEOUT_POLL 40000
+
+/* Masks for valid reset lines in each domain. This array is also used to get
+ * the domain and reset counts.
+ */
+static const u32 eq5r_valid_masks[] = { 0x0FFFFFF8, 0x00001FFF, 0x0007BFFF };
+
+#define EQ5R_DOMAIN_COUNT ARRAY_SIZE(eq5r_valid_masks)
+
+struct eq5r_private {
+ struct mutex mutexes[EQ5R_DOMAIN_COUNT]; /* We serialize all reset operations. */
+ struct regmap *olb; /* Writes go to a syscon regmap. */
+ struct reset_controller_dev rcdev;
+};
+
+static int _eq5r_busy_wait(struct eq5r_private *priv, struct device *dev,
+ u32 domain, u32 offset, bool assert)
+{
+ unsigned int val, mask;
+ int i;
+
+ lockdep_assert_held(&priv->mutexes[domain]);
+
+ switch (domain) {
+ case 0:
+ for (i = 0; i < D0_TIMEOUT_POLL; i++) {
+ regmap_read(priv->olb, EQ5R_OLB_SARCR1, &val);
+ val = !(val & BIT(offset));
+ if (val == assert)
+ return 0;
+ __udelay(1);
+ }
+ break;
+ case 1:
+ mask = assert ? EQ5R_OLB_ACRP_ST_POWER_DOWN : EQ5R_OLB_ACRP_ST_ACTIVE;
+ for (i = 0; i < D1_TIMEOUT_POLL; i++) {
+ regmap_read(priv->olb, EQ5R_OLB_ACRP_REG(offset), &val);
+ if (val & mask)
+ return 0;
+ __udelay(1);
+ }
+ break;
+ case 2:
+ return 0; /* No busy waiting for domain 2. */
+ default:
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "%u-%u: timeout\n", domain, offset);
+ return -ETIMEDOUT;
+}
+
+static void _eq5r_assert(struct eq5r_private *priv, u32 domain, u32 offset)
+{
+ lockdep_assert_held(&priv->mutexes[domain]);
+
+ switch (domain) {
+ case 0:
+ regmap_clear_bits(priv->olb, EQ5R_OLB_SARCR0, BIT(offset));
+ break;
+ case 1:
+ regmap_set_bits(priv->olb, EQ5R_OLB_ACRP_REG(offset),
+ EQ5R_OLB_ACRP_PD_REQ);
+ break;
+ case 2:
+ regmap_clear_bits(priv->olb, EQ5R_OLB_PCIE_GP, BIT(offset));
+ break;
+ default:
+ WARN_ON(1);
+ }
+}
+
+static int eq5r_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct eq5r_private *priv = dev_get_drvdata(rcdev->dev);
+ u32 offset = id & GENMASK(7, 0);
+ u32 domain = id >> 8;
+ int ret;
+
+ if (WARN_ON(domain >= EQ5R_DOMAIN_COUNT))
+ return -EINVAL;
+
+ dev_dbg(rcdev->dev, "%u-%u: assert request\n", domain, offset);
+
+ mutex_lock(&priv->mutexes[domain]);
+ _eq5r_assert(priv, domain, offset);
+ ret = _eq5r_busy_wait(priv, rcdev->dev, domain, offset, true);
+ mutex_unlock(&priv->mutexes[domain]);
+
+ return ret;
+}
+
+static void _eq5r_deassert(struct eq5r_private *priv, u32 domain, u32 offset)
+{
+ lockdep_assert_held(&priv->mutexes[domain]);
+
+ switch (domain) {
+ case 0:
+ regmap_set_bits(priv->olb, EQ5R_OLB_SARCR0, BIT(offset));
+ break;
+ case 1:
+ regmap_clear_bits(priv->olb, EQ5R_OLB_ACRP_REG(offset),
+ EQ5R_OLB_ACRP_PD_REQ);
+ break;
+ case 2:
+ regmap_set_bits(priv->olb, EQ5R_OLB_PCIE_GP, BIT(offset));
+ break;
+ default:
+ WARN_ON(1);
+ }
+}
+
+static int eq5r_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct eq5r_private *priv = dev_get_drvdata(rcdev->dev);
+ u32 offset = id & GENMASK(7, 0);
+ u32 domain = id >> 8;
+ int ret;
+
+ if (WARN_ON(domain >= EQ5R_DOMAIN_COUNT))
+ return -EINVAL;
+
+ dev_dbg(rcdev->dev, "%u-%u: deassert request\n", domain, offset);
+
+ mutex_lock(&priv->mutexes[domain]);
+ _eq5r_deassert(priv, domain, offset);
+ ret = _eq5r_busy_wait(priv, rcdev->dev, domain, offset, false);
+ mutex_unlock(&priv->mutexes[domain]);
+
+ return ret;
+}
+
+static int eq5r_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct device *dev = rcdev->dev;
+ struct eq5r_private *priv = dev_get_drvdata(dev);
+ u32 offset = id & GENMASK(7, 0);
+ u32 domain = id >> 8;
+ int ret;
+
+ if (WARN_ON(domain >= EQ5R_DOMAIN_COUNT))
+ return -EINVAL;
+
+ dev_dbg(dev, "%u-%u: reset request\n", domain, offset);
+
+ mutex_lock(&priv->mutexes[domain]);
+
+ _eq5r_assert(priv, domain, offset);
+ ret = _eq5r_busy_wait(priv, dev, domain, offset, true);
+ if (ret) /* don't let an error disappear silently */
+ dev_warn(dev, "%u-%u: reset assert failed: %d\n",
+ domain, offset, ret);
+
+ _eq5r_deassert(priv, domain, offset);
+ ret = _eq5r_busy_wait(priv, dev, domain, offset, false);
+
+ mutex_unlock(&priv->mutexes[domain]);
+
+ return ret;
+}
+
+static int eq5r_status(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct eq5r_private *priv = dev_get_drvdata(rcdev->dev);
+ u32 offset = id & GENMASK(7, 0);
+ u32 domain = id >> 8;
+ unsigned int val;
+ int ret;
+
+ if (WARN_ON(domain >= EQ5R_DOMAIN_COUNT))
+ return -EINVAL;
+
+ dev_dbg(rcdev->dev, "%u-%u: status request\n", domain, offset);
+
+ mutex_lock(&priv->mutexes[domain]);
+
+ switch (domain) {
+ case 0:
+ regmap_read(priv->olb, EQ5R_OLB_SARCR1, &val);
+ ret = !(val & BIT(offset));
+ break;
+ case 1:
+ regmap_read(priv->olb, EQ5R_OLB_ACRP_REG(offset), &val);
+ ret = !(val & EQ5R_OLB_ACRP_ST_ACTIVE);
+ break;
+ case 2:
+ regmap_read(priv->olb, EQ5R_OLB_PCIE_GP, &val);
+ ret = !(val & BIT(offset));
+ break;
+ }
+
+ mutex_unlock(&priv->mutexes[domain]);
+
+ return ret;
+}
+
+static const struct reset_control_ops eq5r_ops = {
+ .reset = eq5r_reset,
+ .assert = eq5r_assert,
+ .deassert = eq5r_deassert,
+ .status = eq5r_status,
+};
+
+static int eq5r_of_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *reset_spec)
+{
+ u32 domain, offset;
+
+ if (WARN_ON(reset_spec->args_count != 2))
+ return -EINVAL;
+
+ domain = reset_spec->args[0];
+ offset = reset_spec->args[1];
+
+ if (domain >= EQ5R_DOMAIN_COUNT || offset > 31 ||
+ !(eq5r_valid_masks[domain] & BIT(offset))) {
+ dev_err(rcdev->dev, "%u-%u: invalid reset\n", domain, offset);
+ return -EINVAL;
+ }
+
+ return (domain << 8) | offset;
+}
+
+static int eq5r_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *parent_np = of_get_parent(np);
+ struct eq5r_private *priv;
+ int ret, i;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, priv);
+
+ priv->olb = ERR_PTR(-ENODEV);
+ if (parent_np)
+ priv->olb = syscon_node_to_regmap(parent_np);
+ if (IS_ERR(priv->olb))
+ priv->olb = syscon_regmap_lookup_by_phandle(np, "mobileye,olb");
+ if (IS_ERR(priv->olb))
+ return PTR_ERR(priv->olb);
+
+ for (i = 0; i < EQ5R_DOMAIN_COUNT; i++)
+ mutex_init(&priv->mutexes[i]);
+
+ priv->rcdev.ops = &eq5r_ops;
+ priv->rcdev.owner = THIS_MODULE;
+ priv->rcdev.dev = dev;
+ priv->rcdev.of_node = np;
+ priv->rcdev.of_reset_n_cells = 2;
+ priv->rcdev.of_xlate = eq5r_of_xlate;
+
+ priv->rcdev.nr_resets = 0;
+ for (i = 0; i < EQ5R_DOMAIN_COUNT; i++)
+ priv->rcdev.nr_resets += __builtin_popcount(eq5r_valid_masks[i]);
+
+ ret = reset_controller_register(&priv->rcdev);
+ if (ret) {
+ dev_err(dev, "Failed registering reset controller: %d\n", ret);
+ return ret;
+ }
+
+ dev_info(dev, "probed\n");
+
+ return 0;
+}
+
+static const struct of_device_id eq5r_match_table[] = {
+ { .compatible = "mobileye,eyeq5-reset" },
+ {}
+};
+
+static struct platform_driver eq5r_driver = {
+ .probe = eq5r_probe,
+ .driver = {
+ .name = "eyeq5-reset",
+ .of_match_table = eq5r_match_table,
+ },
+};
+
+static int __init eq5r_init(void)
+{
+ return platform_driver_register(&eq5r_driver);
+}
+
+arch_initcall(eq5r_init);
--
2.43.0
Add the devicetree node for the reset controller on the Mobileye EyeQ5
platform. It appears as a subnode to the OLB syscon as its registers
are located in this shared register region.
Signed-off-by: Théo Lebrun <[email protected]>
---
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index d32da8fabe5a..b7da037ef324 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/reset/mobileye,eyeq5-reset.h>
/memreserve/ 0x40000000 0xc0000000; /* DDR32 */
@@ -76,6 +77,11 @@ olb: olb@e00000 {
compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
reg = <0 0xe00000 0x0 0x400>;
reg-io-width = <4>;
+
+ reset: reset-controller {
+ compatible = "mobileye,eyeq5-reset";
+ #reset-cells = <2>;
+ };
};
gic: interrupt-controller@140000 {
--
2.43.0
UART nodes have been added to the devicetree by the initial platform
support patch series. Add reset properties now that the reset node is
declared.
Signed-off-by: Théo Lebrun <[email protected]>
---
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index b7da037ef324..746148eb423f 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -51,6 +51,7 @@ uart0: serial@800000 {
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&occ_periph>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&reset 0 EQ5R_D0_UART0>;
};
uart1: serial@900000 {
@@ -61,6 +62,7 @@ uart1: serial@900000 {
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&occ_periph>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&reset 0 EQ5R_D0_UART1>;
};
uart2: serial@a00000 {
@@ -71,6 +73,7 @@ uart2: serial@a00000 {
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&occ_periph>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&reset 0 EQ5R_D0_UART2>;
};
olb: olb@e00000 {
--
2.43.0
On Mon, 18 Dec 2023 18:16:12 +0100, Théo Lebrun wrote:
> Add DT-Schema bindings for the EyeQ5 reset controller.
>
> Signed-off-by: Théo Lebrun <[email protected]>
> ---
> .../bindings/reset/mobileye,eyeq5-reset.yaml | 69 +++++++++++++++++++
> MAINTAINERS | 2 +
> include/dt-bindings/reset/mobileye,eyeq5-reset.h | 80 ++++++++++++++++++++++
> 3 files changed, 151 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.example.dtb: /example-0/olb@e00000: failed to match any schema with compatible: ['mobileye,eyeq5-olb', 'syscon', 'simple-mfd']
Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.example.dtb: /example-1/olb@e00000: failed to match any schema with compatible: ['mobileye,eyeq5-olb', 'syscon', 'simple-mfd']
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.example.dtb: reset-controller: 'mobileye,olb' does not match any of the regexes: '^#.*', '^(at25|bm|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio-key|gpio|gpmc|hdmi|i2c-gpio),.*', '^(keypad|m25p|max8952|max8997|max8998|mpmc),.*', '^(pinctrl-single|#pinctrl-single|PowerPC),.*', '^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*', '^(simple-audio-card|st-plgpio|st-spics|ts),.*', '^100ask,.*', '^70mai,.*', '^8dev,.*', '^GEFanuc,.*', '^ORCL,.*', '^SUNW,.*', '^[a-zA-Z0-9#_][a-zA-Z0-9+\\-._@]{0,63}$', '^[a-zA-Z0-9+\\-._]*@[0-9a-zA-Z,]*$', '^abb,.*', '^abilis,.*', '^abracon,.*', '^abt,.*', '^acbel,.*', '^acer,.*', '^acme,.*', '^actions,.*', '^active-semi,.*', '^ad,.*', '^adafruit,.*', '^adapteva,.*', '^adaptrum,.*', '^adh,.*', '^adi,.*', '^adieng,.*', '^advantech,.*', '^aeroflexgaisler,.*', '^aesop,.*', '^airoha,.*', '^al,.*', '^alcatel,.*', '^aldec,.*', '^alfa-network,.*', '^allegr
o,.*', '^allo,.*', '^allwinner,.*', '^alphascale,.*', '^alps,.*', '^alt,.*', '^altr,.*', '^amarula,.*', '^amazon,.*', '^amcc,.*', '^amd,.*', '^amediatech,.*', '^amlogic,.*', '^ampere,.*', '^ampire,.*', '^ams,.*', '^amstaos,.*', '^analogix,.*', '^anbernic,.*', '^andestech,.*', '^anvo,.*', '^apm,.*', '^apple,.*', '^aptina,.*', '^arasan,.*', '^archermind,.*', '^arcom,.*', '^arctic,.*', '^arcx,.*', '^aries,.*', '^arm,.*', '^armadeus,.*', '^arrow,.*', '^artesyn,.*', '^asahi-kasei,.*', '^asc,.*', '^asix,.*', '^aspeed,.*', '^asrock,.*', '^asus,.*', '^atheros,.*', '^atlas,.*', '^atmel,.*', '^auo,.*', '^auvidea,.*', '^avago,.*', '^avia,.*', '^avic,.*', '^avnet,.*', '^awinic,.*', '^axentia,.*', '^axis,.*', '^azoteq,.*', '^azw,.*', '^baikal,.*', '^bananapi,.*', '^beacon,.*', '^beagle,.*', '^belling,.*', '^bhf,.*', '^bigtreetech,.*', '^bitmain,.*', '^blutek,.*', '^boe,.*', '^bosch,.*', '^boundary,.*', '^brcm,.*', '^broadmobi,.*', '^bsh,.*', '^bticino,.*', '^buffalo,.*', '^bur,.*', '^bytedance,.
*', '^calamp,.*', '^calaosystems,.*', '^calxeda,.*', '^canaan,.*', '^caninos,.*', '^capella,.*', '^cascoda,.*', '^catalyst,.*', '^cavium,.*', '^cdns,.*', '^cdtech,.*', '^cellwise,.*', '^ceva,.*', '^chargebyte,.*', '^checkpoint,.*', '^chefree,.*', '^chipidea,.*', '^chipone,.*', '^chipspark,.*', '^chongzhou,.*', '^chrontel,.*', '^chrp,.*', '^chunghwa,.*', '^chuwi,.*', '^ciaa,.*', '^cirrus,.*', '^cisco,.*', '^clockwork,.*', '^cloos,.*', '^cloudengines,.*', '^cnm,.*', '^cnxt,.*', '^colorfly,.*', '^compulab,.*', '^congatec,.*', '^coreriver,.*', '^corpro,.*', '^cortina,.*', '^cosmic,.*', '^crane,.*', '^creative,.*', '^crystalfontz,.*', '^csky,.*', '^csq,.*', '^ctera,.*', '^ctu,.*', '^cubietech,.*', '^cui,.*', '^cypress,.*', '^cyx,.*', '^cznic,.*', '^dallas,.*', '^dataimage,.*', '^davicom,.*', '^dell,.*', '^delta,.*', '^densitron,.*', '^denx,.*', '^devantech,.*', '^dfi,.*', '^dh,.*', '^difrnce,.*', '^digi,.*', '^digilent,.*', '^diodes,.*', '^dioo,.*', '^dlc,.*', '^dlg,.*', '^dlink,.*', '^d
mo,.*', '^domintech,.*', '^dongwoon,.*', '^dptechnics,.*', '^dragino,.*', '^ds,.*', '^dserve,.*', '^dynaimage,.*', '^ea,.*', '^ebang,.*', '^ebbg,.*', '^ebs-systart,.*', '^ebv,.*', '^eckelmann,.*', '^edgeble,.*', '^edimax,.*', '^edt,.*', '^ees,.*', '^eeti,.*', '^einfochips,.*', '^eink,.*', '^elan,.*', '^element14,.*', '^elgin,.*', '^elida,.*', '^elimo,.*', '^elpida,.*', '^embedfire,.*', '^embest,.*', '^emlid,.*', '^emmicro,.*', '^empire-electronix,.*', '^emtrion,.*', '^enclustra,.*', '^endless,.*', '^ene,.*', '^energymicro,.*', '^engicam,.*', '^engleder,.*', '^epcos,.*', '^epfl,.*', '^epson,.*', '^esp,.*', '^est,.*', '^ettus,.*', '^eukrea,.*', '^everest,.*', '^everspin,.*', '^evervision,.*', '^exar,.*', '^excito,.*', '^exegin,.*', '^ezchip,.*', '^facebook,.*', '^fairphone,.*', '^faraday,.*', '^fastrax,.*', '^fcs,.*', '^feixin,.*', '^feiyang,.*', '^fii,.*', '^firefly,.*', '^focaltech,.*', '^forlinx,.*', '^freecom,.*', '^frida,.*', '^friendlyarm,.*', '^fsl,.*', '^fujitsu,.*', '^fxtec,.
*', '^gardena,.*', '^gateway,.*', '^gateworks,.*', '^gcw,.*', '^ge,.*', '^geekbuying,.*', '^gef,.*', '^gemei,.*', '^gemtek,.*', '^genesys,.*', '^geniatech,.*', '^giantec,.*', '^giantplus,.*', '^globalscale,.*', '^globaltop,.*', '^gmt,.*', '^goldelico,.*', '^goodix,.*', '^google,.*', '^goramo,.*', '^gplus,.*', '^grinn,.*', '^grmn,.*', '^gumstix,.*', '^gw,.*', '^hannstar,.*', '^haochuangyi,.*', '^haoyu,.*', '^hardkernel,.*', '^hechuang,.*', '^hideep,.*', '^himax,.*', '^hirschmann,.*', '^hisi,.*', '^hisilicon,.*', '^hit,.*', '^hitex,.*', '^holt,.*', '^holtek,.*', '^honestar,.*', '^honeywell,.*', '^hoperun,.*', '^hp,.*', '^hpe,.*', '^hsg,.*', '^huawei,.*', '^hugsun,.*', '^hwacom,.*', '^hxt,.*', '^hycon,.*', '^hydis,.*', '^hynitron,.*', '^hynix,.*', '^hyundai,.*', '^i2se,.*', '^ibm,.*', '^icplus,.*', '^idt,.*', '^ifi,.*', '^ilitek,.*', '^imagis,.*', '^img,.*', '^imi,.*', '^inanbo,.*', '^incircuit,.*', '^indiedroid,.*', '^inet-tek,.*', '^infineon,.*', '^inforce,.*', '^ingenic,.*', '^ingra
sys,.*', '^injoinic,.*', '^innocomm,.*', '^innolux,.*', '^inside-secure,.*', '^insignal,.*', '^inspur,.*', '^intel,.*', '^intercontrol,.*', '^invensense,.*', '^inventec,.*', '^inversepath,.*', '^iom,.*', '^irondevice,.*', '^isee,.*', '^isil,.*', '^issi,.*', '^ite,.*', '^itead,.*', '^itian,.*', '^ivo,.*', '^iwave,.*', '^jadard,.*', '^jasonic,.*', '^jdi,.*', '^jedec,.*', '^jesurun,.*', '^jethome,.*', '^jianda,.*', '^joz,.*', '^kam,.*', '^karo,.*', '^keithkoep,.*', '^keymile,.*', '^khadas,.*', '^kiebackpeter,.*', '^kinetic,.*', '^kingdisplay,.*', '^kingnovel,.*', '^kionix,.*', '^kobo,.*', '^kobol,.*', '^koe,.*', '^kontron,.*', '^kosagi,.*', '^kvg,.*', '^kyo,.*', '^lacie,.*', '^laird,.*', '^lamobo,.*', '^lantiq,.*', '^lattice,.*', '^lctech,.*', '^leadtek,.*', '^leez,.*', '^lego,.*', '^lemaker,.*', '^lenovo,.*', '^lg,.*', '^lgphilips,.*', '^libretech,.*', '^licheepi,.*', '^linaro,.*', '^lineartechnology,.*', '^linksprite,.*', '^linksys,.*', '^linutronix,.*', '^linux,.*', '^linx,.*', '^li
teon,.*', '^litex,.*', '^lltc,.*', '^logicpd,.*', '^logictechno,.*', '^longcheer,.*', '^lontium,.*', '^loongmasses,.*', '^loongson,.*', '^lsi,.*', '^lunzn,.*', '^lwn,.*', '^lxa,.*', '^m5stack,.*', '^macnica,.*', '^mantix,.*', '^mapleboard,.*', '^marantec,.*', '^marvell,.*', '^maxbotix,.*', '^maxim,.*', '^maxlinear,.*', '^mbvl,.*', '^mcube,.*', '^meas,.*', '^mecer,.*', '^mediatek,.*', '^megachips,.*', '^mele,.*', '^melexis,.*', '^melfas,.*', '^mellanox,.*', '^memsensing,.*', '^memsic,.*', '^menlo,.*', '^mentor,.*', '^meraki,.*', '^merrii,.*', '^methode,.*', '^micrel,.*', '^microchip,.*', '^microcrystal,.*', '^micron,.*', '^microsoft,.*', '^microsys,.*', '^mikroe,.*', '^mikrotik,.*', '^milkv,.*', '^miniand,.*', '^minix,.*', '^miramems,.*', '^mitsubishi,.*', '^mitsumi,.*', '^mixel,.*', '^miyoo,.*', '^mntre,.*', '^modtronix,.*', '^moortec,.*', '^mosaixtech,.*', '^motorcomm,.*', '^motorola,.*', '^moxa,.*', '^mpl,.*', '^mps,.*', '^mqmaker,.*', '^mrvl,.*', '^mscc,.*', '^msi,.*', '^mstar,.*
', '^mti,.*', '^multi-inno,.*', '^mundoreader,.*', '^murata,.*', '^mxic,.*', '^mxicy,.*', '^myir,.*', '^national,.*', '^nec,.*', '^neonode,.*', '^netgear,.*', '^netlogic,.*', '^netron-dy,.*', '^netronix,.*', '^netxeon,.*', '^neweast,.*', '^newhaven,.*', '^newvision,.*', '^nexbox,.*', '^nextthing,.*', '^ni,.*', '^nintendo,.*', '^nlt,.*', '^nokia,.*', '^nordic,.*', '^novatek,.*', '^novtech,.*', '^nutsboard,.*', '^nuvoton,.*', '^nvd,.*', '^nvidia,.*', '^nxp,.*', '^oceanic,.*', '^ocs,.*', '^oct,.*', '^okaya,.*', '^oki,.*', '^olimex,.*', '^olpc,.*', '^oneplus,.*', '^onie,.*', '^onion,.*', '^onnn,.*', '^ontat,.*', '^opalkelly,.*', '^openailab,.*', '^opencores,.*', '^openembed,.*', '^openpandora,.*', '^openrisc,.*', '^option,.*', '^oranth,.*', '^orisetech,.*', '^ortustech,.*', '^osddisplays,.*', '^osmc,.*', '^ouya,.*', '^overkiz,.*', '^ovti,.*', '^oxsemi,.*', '^ozzmaker,.*', '^panasonic,.*', '^parade,.*', '^parallax,.*', '^pda,.*', '^pericom,.*', '^pervasive,.*', '^phicomm,.*', '^phytec,.*
', '^picochip,.*', '^pine64,.*', '^pineriver,.*', '^pixcir,.*', '^plantower,.*', '^plathome,.*', '^plda,.*', '^plx,.*', '^ply,.*', '^pni,.*', '^pocketbook,.*', '^polaroid,.*', '^polyhex,.*', '^portwell,.*', '^poslab,.*', '^pov,.*', '^powertip,.*', '^powervr,.*', '^powkiddy,.*', '^primux,.*', '^probox2,.*', '^prt,.*', '^pulsedlight,.*', '^purism,.*', '^qca,.*', '^qcom,.*', '^qemu,.*', '^qi,.*', '^qiaodian,.*', '^qihua,.*', '^qishenglong,.*', '^qnap,.*', '^quanta,.*', '^radxa,.*', '^raidsonic,.*', '^ralink,.*', '^ramtron,.*', '^raspberrypi,.*', '^raydium,.*', '^rda,.*', '^realtek,.*', '^remarkable,.*', '^renesas,.*', '^rervision,.*', '^revotics,.*', '^rex,.*', '^richtek,.*', '^ricoh,.*', '^rikomagic,.*', '^riot,.*', '^riscv,.*', '^rockchip,.*', '^rocktech,.*', '^rohm,.*', '^ronbo,.*', '^roofull,.*', '^roseapplepi,.*', '^saef,.*', '^samsung,.*', '^samtec,.*', '^sancloud,.*', '^sandisk,.*', '^satoz,.*', '^sbs,.*', '^schindler,.*', '^seagate,.*', '^seeed,.*', '^seirobotics,.*', '^semtech
,.*', '^senseair,.*', '^sensirion,.*', '^sensortek,.*', '^sercomm,.*', '^sff,.*', '^sgd,.*', '^sgmicro,.*', '^sgx,.*', '^sharp,.*', '^shift,.*', '^shimafuji,.*', '^shineworld,.*', '^shiratech,.*', '^si-en,.*', '^si-linux,.*', '^siemens,.*', '^sifive,.*', '^sigma,.*', '^sii,.*', '^sil,.*', '^silabs,.*', '^silan,.*', '^silead,.*', '^silergy,.*', '^silex-insight,.*', '^siliconfile,.*', '^siliconmitus,.*', '^silvaco,.*', '^simtek,.*', '^sinlinx,.*', '^sinovoip,.*', '^sinowealth,.*', '^sipeed,.*', '^sirf,.*', '^sis,.*', '^sitronix,.*', '^skov,.*', '^skyworks,.*', '^smartlabs,.*', '^smsc,.*', '^snps,.*', '^sochip,.*', '^socionext,.*', '^solidrun,.*', '^solomon,.*', '^sony,.*', '^sophgo,.*', '^sourceparts,.*', '^spansion,.*', '^sparkfun,.*', '^spinalhdl,.*', '^sprd,.*', '^square,.*', '^ssi,.*', '^sst,.*', '^sstar,.*', '^st,.*', '^st-ericsson,.*', '^starfive,.*', '^starry,.*', '^startek,.*', '^starterkit,.*', '^ste,.*', '^stericsson,.*', '^storlink,.*', '^storm,.*', '^storopack,.*', '^summi
t,.*', '^sunchip,.*', '^sundance,.*', '^sunplus,.*', '^supermicro,.*', '^swir,.*', '^syna,.*', '^synology,.*', '^synopsys,.*', '^tbs,.*', '^tbs-biometrics,.*', '^tcg,.*', '^tcl,.*', '^tcs,.*', '^tdo,.*', '^team-source-display,.*', '^technexion,.*', '^technologic,.*', '^techstar,.*', '^teejet,.*', '^teltonika,.*', '^tempo,.*', '^terasic,.*', '^tesla,.*', '^tfc,.*', '^thead,.*', '^thine,.*', '^thingyjp,.*', '^thundercomm,.*', '^thwc,.*', '^ti,.*', '^tianma,.*', '^tlm,.*', '^tmt,.*', '^topeet,.*', '^topic,.*', '^toppoly,.*', '^topwise,.*', '^toradex,.*', '^toshiba,.*', '^toumaz,.*', '^tpk,.*', '^tplink,.*', '^tpo,.*', '^tq,.*', '^traverse,.*', '^tronfy,.*', '^tronsmart,.*', '^truly,.*', '^tsd,.*', '^turing,.*', '^tyan,.*', '^u-blox,.*', '^u-boot,.*', '^ubnt,.*', '^ucrobotics,.*', '^udoo,.*', '^ufispace,.*', '^ugoos,.*', '^uniwest,.*', '^upisemi,.*', '^urt,.*', '^usi,.*', '^usr,.*', '^utoo,.*', '^v3,.*', '^vaisala,.*', '^vamrs,.*', '^variscite,.*', '^vdl,.*', '^vertexcom,.*', '^via,.*',
'^vialab,.*', '^vicor,.*', '^videostrong,.*', '^virtio,.*', '^virtual,.*', '^vishay,.*', '^visionox,.*', '^vitesse,.*', '^vivante,.*', '^vivax,.*', '^vocore,.*', '^voipac,.*', '^vot,.*', '^vxt,.*', '^wanchanglong,.*', '^wand,.*', '^waveshare,.*', '^wd,.*', '^we,.*', '^welltech,.*', '^wetek,.*', '^wexler,.*', '^whwave,.*', '^wi2wi,.*', '^widora,.*', '^wiligear,.*', '^willsemi,.*', '^winbond,.*', '^wingtech,.*', '^winlink,.*', '^winstar,.*', '^wirelesstag,.*', '^wits,.*', '^wlf,.*', '^wm,.*', '^wobo,.*', '^x-powers,.*', '^xen,.*', '^xes,.*', '^xiaomi,.*', '^xillybus,.*', '^xingbangda,.*', '^xinpeng,.*', '^xiphera,.*', '^xlnx,.*', '^xnano,.*', '^xunlong,.*', '^xylon,.*', '^yadro,.*', '^yamaha,.*', '^yes-optoelectronics,.*', '^yic,.*', '^yiming,.*', '^ylm,.*', '^yna,.*', '^yones-toptech,.*', '^ys,.*', '^ysoft,.*', '^zarlink,.*', '^zealz,.*', '^zeitec,.*', '^zidoo,.*', '^zii,.*', '^zinitix,.*', '^zkmagic,.*', '^zte,.*', '^zyxel,.*', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/vendor-prefixes.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On 18/12/2023 18:16, Théo Lebrun wrote:
> Add DT-Schema bindings for the EyeQ5 reset controller.
>
> Signed-off-by: Théo Lebrun <[email protected]>
> ---
> .../bindings/reset/mobileye,eyeq5-reset.yaml | 69 +++++++++++++++++++
> MAINTAINERS | 2 +
> include/dt-bindings/reset/mobileye,eyeq5-reset.h | 80 ++++++++++++++++++++++
> 3 files changed, 151 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml b/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml
> new file mode 100644
> index 000000000000..cab6a75ba59d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mobileye EyeQ5 reset controller
> +
> +description:
> + The EyeQ5 reset driver handles three reset domains. It is custom to this
> + platform, its registers live in a shared region called OLB.
> +
> +maintainers:
> + - Grégory Clement <[email protected]>
> + - Théo Lebrun <[email protected]>
> + - Vladimir Kondratiev <[email protected]>
> +
> +properties:
> + $nodename:
> + pattern: "^reset-controller$"
> + description:
> + We have no unique address, we rely on OLB.
NAK, third time.
> +
> + compatible:
> + const: mobileye,eyeq5-reset
> +
> + "#reset-cells":
> + const: 2
> + description:
> + The first cell is the domain (0 to 2 inclusive) and the second one is the
> + reset index inside that domain.
> +
> + mobileye,olb:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + A phandle to the OLB syscon. This is a fallback to using the parent as
> + syscon node.
No, the same rationale as before.
> +
> +required:
> + - compatible
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + olb@e00000 {
> + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
No, the same rationale as before.
> + reg = <0xe00000 0x400>;
> + reg-io-width = <4>;
> +
> + reset-controller {
> + compatible = "mobileye,eyeq5-reset";
> + #reset-cells = <2>;
> + };
> + };
> +
> + - |
> + olb: olb@e00000 {
> + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
No, the same rationale as before. The hardware is either A or B, not both.
> + reg = <0xe00000 0x400>;
> + reg-io-width = <4>;
> + };
> +
> + reset-controller {
> + compatible = "mobileye,eyeq5-reset";
> + #reset-cells = <2>;
> + mobileye,olb = <&olb>;
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4a7bd6b40d74..9096a940b425 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14553,9 +14553,11 @@ M: Théo Lebrun <[email protected]>
> L: [email protected]
> S: Maintained
> F: Documentation/devicetree/bindings/mips/mobileye.yaml
> +F: Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml
> F: arch/mips/boot/dts/mobileye/
> F: arch/mips/configs/generic/board-eyeq5.config
> F: arch/mips/generic/board-epm5.its.S
> +F: include/dt-bindings/reset/mobileye,eyeq5-reset.h
> F: include/dt-bindings/soc/mobileye,eyeq5.h
>
> MODULE SUPPORT
> diff --git a/include/dt-bindings/reset/mobileye,eyeq5-reset.h b/include/dt-bindings/reset/mobileye,eyeq5-reset.h
> new file mode 100644
> index 000000000000..ce59fe5409ac
> --- /dev/null
> +++ b/include/dt-bindings/reset/mobileye,eyeq5-reset.h
> @@ -0,0 +1,80 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Mobileye Vision Technologies Ltd.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_MOBILEYE_EYEQ5_RESET_H
> +#define _DT_BINDINGS_RESET_MOBILEYE_EYEQ5_RESET_H
> +
> +/* Domain 0 */
> +
> +/* 0..2 are reserved */
No, they are not. IDs cannot be reserved. IDs start from 0 and are
incremented by 1. Reserving an ID contradicts to entire point of that
ID, so either drop entire file or make this proper IDs.
> +#define EQ5R_D0_CAN0 3
> +#define EQ5R_D0_CAN1 4
> +#define EQ5R_D0_CAN2 5
> +#define EQ5R_D0_SPI0 6
> +#define EQ5R_D0_SPI1 7
> +#define EQ5R_D0_SPI2 8
> +#define EQ5R_D0_SPI3 9
...
> +
> +#define EQ5R_D2_MULTIPHY_SWRST_DIS 12
> +#define EQ5R_D2_MULTIPHY_APB_RST_DIS 13
> +/* 14 is refclk select, ie not a reset */
> +#define EQ5R_D2_PCIE0_LINK_MGMT_RST 15
> +#define EQ5R_D2_PCIE1_LINK_MGMT_RST 16
> +#define EQ5R_D2_PCIE0_LINK_PM_RST 17
> +#define EQ5R_D2_PCIE1_LINK_PM_RST 18
> +/* 19..31 are unknown */
No, they are not unknown. They are explicitly implemented by driver or
these are not IDs.
Best regards,
Krzysztof
On 18/12/2023 18:16, Théo Lebrun wrote:
> Add the Mobileye EyeQ5 reset controller driver. See the header comment
> for more information on how it works. This driver is specific to this
> platform; it might grow to add later support of other platforms from
> Mobileye.
>
> Signed-off-by: Théo Lebrun <[email protected]>
> ---
...
> +static int eq5r_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct device_node *parent_np = of_get_parent(np);
> + struct eq5r_private *priv;
> + int ret, i;
> +
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, priv);
> +
> + priv->olb = ERR_PTR(-ENODEV);
> + if (parent_np)
> + priv->olb = syscon_node_to_regmap(parent_np);
> + if (IS_ERR(priv->olb))
> + priv->olb = syscon_regmap_lookup_by_phandle(np, "mobileye,olb");
> + if (IS_ERR(priv->olb))
> + return PTR_ERR(priv->olb);
NAK for such code. In all of your patches. This is part of the OLB, as
you explained before, and cannot be anything else.
> +
> + for (i = 0; i < EQ5R_DOMAIN_COUNT; i++)
> + mutex_init(&priv->mutexes[i]);
> +
> + priv->rcdev.ops = &eq5r_ops;
> + priv->rcdev.owner = THIS_MODULE;
> + priv->rcdev.dev = dev;
> + priv->rcdev.of_node = np;
> + priv->rcdev.of_reset_n_cells = 2;
> + priv->rcdev.of_xlate = eq5r_of_xlate;
> +
> + priv->rcdev.nr_resets = 0;
> + for (i = 0; i < EQ5R_DOMAIN_COUNT; i++)
> + priv->rcdev.nr_resets += __builtin_popcount(eq5r_valid_masks[i]);
> +
> + ret = reset_controller_register(&priv->rcdev);
> + if (ret) {
> + dev_err(dev, "Failed registering reset controller: %d\n", ret);
> + return ret;
> + }
> +
> + dev_info(dev, "probed\n");
Drop
Best regards,
Krzysztof
Hello,
Thanks for your comments. I have a question for one:
On Tue Dec 19, 2023 at 8:40 AM CET, Krzysztof Kozlowski wrote:
> On 18/12/2023 18:16, Théo Lebrun wrote:
> > Add DT-Schema bindings for the EyeQ5 reset controller.
> >
> > Signed-off-by: Théo Lebrun <[email protected]>
> > ---
> > .../bindings/reset/mobileye,eyeq5-reset.yaml | 69 +++++++++++++++++++
> > MAINTAINERS | 2 +
> > include/dt-bindings/reset/mobileye,eyeq5-reset.h | 80 ++++++++++++++++++++++
> > 3 files changed, 151 insertions(+)
> >
[...]
> > diff --git a/include/dt-bindings/reset/mobileye,eyeq5-reset.h b/include/dt-bindings/reset/mobileye,eyeq5-reset.h
> > new file mode 100644
> > index 000000000000..ce59fe5409ac
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/mobileye,eyeq5-reset.h
> > @@ -0,0 +1,80 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * Copyright (C) 2023 Mobileye Vision Technologies Ltd.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_RESET_MOBILEYE_EYEQ5_RESET_H
> > +#define _DT_BINDINGS_RESET_MOBILEYE_EYEQ5_RESET_H
> > +
> > +/* Domain 0 */
> > +
> > +/* 0..2 are reserved */
>
> No, they are not. IDs cannot be reserved. IDs start from 0 and are
> incremented by 1. Reserving an ID contradicts to entire point of that
> ID, so either drop entire file or make this proper IDs.
Those are hardware IDs. I get what you mean is that they should not leak
into bindings. That implies a mapping operation from bindings IDs to
understood-by-hardware IDs. Can you confirm this is what you expect?
Thanks,
--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On 20/12/2023 10:25, Théo Lebrun wrote:
> Hello,
>
> Thanks for your comments. I have a question for one:
>
> On Tue Dec 19, 2023 at 8:40 AM CET, Krzysztof Kozlowski wrote:
>> On 18/12/2023 18:16, Théo Lebrun wrote:
>>> Add DT-Schema bindings for the EyeQ5 reset controller.
>>>
>>> Signed-off-by: Théo Lebrun <[email protected]>
>>> ---
>>> .../bindings/reset/mobileye,eyeq5-reset.yaml | 69 +++++++++++++++++++
>>> MAINTAINERS | 2 +
>>> include/dt-bindings/reset/mobileye,eyeq5-reset.h | 80 ++++++++++++++++++++++
>>> 3 files changed, 151 insertions(+)
>>>
>
> [...]
>
>>> diff --git a/include/dt-bindings/reset/mobileye,eyeq5-reset.h b/include/dt-bindings/reset/mobileye,eyeq5-reset.h
>>> new file mode 100644
>>> index 000000000000..ce59fe5409ac
>>> --- /dev/null
>>> +++ b/include/dt-bindings/reset/mobileye,eyeq5-reset.h
>>> @@ -0,0 +1,80 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>> +/*
>>> + * Copyright (C) 2023 Mobileye Vision Technologies Ltd.
>>> + */
>>> +
>>> +#ifndef _DT_BINDINGS_RESET_MOBILEYE_EYEQ5_RESET_H
>>> +#define _DT_BINDINGS_RESET_MOBILEYE_EYEQ5_RESET_H
>>> +
>>> +/* Domain 0 */
>>> +
>>> +/* 0..2 are reserved */
>>
>> No, they are not. IDs cannot be reserved. IDs start from 0 and are
>> incremented by 1. Reserving an ID contradicts to entire point of that
>> ID, so either drop entire file or make this proper IDs.
>
> Those are hardware IDs. I get what you mean is that they should not leak
There is no such thing as "hardware ID". It is some value passed to
hardware/firmware or hardware register address/offset.
There is no point to store hardware register values/offsets in the bindings.
> into bindings. That implies a mapping operation from bindings IDs to
> understood-by-hardware IDs. Can you confirm this is what you expect?
https://en.wikipedia.org/wiki/Language_binding
Bindings is an abstraction layer, not hardware, therefore my expectation
is not having some sort of register values or offsets in the binding.
Drop the header from bindings.
Best regards,
Krzysztof