From: Frank Wunderlich <[email protected]>
This series adds Rockchip PCIe V3 support found on rk3568 SOC.
Compared to PCIeV2 which uses the Naneng combphy, PCIe v3 uses a dedicated
PCI-phy.
Frank Wunderlich (4):
dt-bindings: phy: rockchip: add PCIe v3 phy
dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf
arm64: dts: rockchip: rk3568: Add PCIe v3 nodes
arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro
Shawn Lin (1):
phy: rockchip: Support PCIe v3
.../bindings/phy/rockchip,pcie3-phy.yaml | 80 +++++
.../devicetree/bindings/soc/rockchip/grf.yaml | 3 +
.../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 117 +++++++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++
drivers/phy/rockchip/Kconfig | 9 +
drivers/phy/rockchip/Makefile | 1 +
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 319 ++++++++++++++++++
include/linux/phy/pcie.h | 12 +
8 files changed, 663 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
create mode 100644 include/linux/phy/pcie.h
--
2.34.1
From: Frank Wunderlich <[email protected]>
Add nodes to rk356x devicetree to support PCIe v3.
Signed-off-by: Peter Geis <[email protected]>
Signed-off-by: Frank Wunderlich <[email protected]>
---
v4:
- update pcie3 reg/ranges
v3:
- fix from Peter: change bus-range and msi-map, msi-map needs
to start from 0x0
v2:
- change to compatible with soc-part
- change rockchip,bifurcation to vendor unspecific bifurcation
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 2bdf8c7e9765..ba67b58f05b7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 {
reg = <0x0 0xfe190200 0x0 0x20>;
};
+ pcie30_phy_grf: syscon@fdcb8000 {
+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
+ reg = <0x0 0xfdcb8000 0x0 0x10000>;
+ };
+
+ pcie30phy: phy@fe8c0000 {
+ compatible = "rockchip,rk3568-pcie3-phy";
+ reg = <0x0 0xfe8c0000 0x0 0x20000>;
+ #phy-cells = <0>;
+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
+ <&cru PCLK_PCIE30PHY>;
+ clock-names = "refclk_m", "refclk_n", "pclk";
+ resets = <&cru SRST_PCIE30PHY>;
+ reset-names = "phy";
+ rockchip,phy-grf = <&pcie30_phy_grf>;
+ status = "disabled";
+ };
+
+ pcie3x1: pcie@fe270000 {
+ compatible = "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
+ <&cru CLK_PCIE30X1_AUX_NDFT>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
+ <0 0 0 2 &pcie3x1_intc 1>,
+ <0 0 0 3 &pcie3x1_intc 2>,
+ <0 0 0 4 &pcie3x1_intc 3>;
+ linux,pci-domain = <1>;
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ max-link-speed = <3>;
+ msi-map = <0x0 &gic 0x1000 0x1000>;
+ num-lanes = <1>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3568_PD_PIPE>;
+ reg = <0x3 0xc0400000 0x0 0x00400000>,
+ <0x0 0xfe270000 0x0 0x00010000>,
+ <0x3 0x7f000000 0x0 0x01000000>;
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE30X1_POWERUP>;
+ reset-names = "pipe";
+ /* bifurcation; lane1 when using 1+1 */
+ status = "disabled";
+
+ pcie3x1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie3x2: pcie@fe280000 {
+ compatible = "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+ <&cru CLK_PCIE30X2_AUX_NDFT>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
+ <0 0 0 2 &pcie3x2_intc 1>,
+ <0 0 0 3 &pcie3x2_intc 2>,
+ <0 0 0 4 &pcie3x2_intc 3>;
+ linux,pci-domain = <2>;
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ max-link-speed = <3>;
+ msi-map = <0x0 &gic 0x2000 0x1000>;
+ num-lanes = <2>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3568_PD_PIPE>;
+ reg = <0x3 0xc0800000 0x0 0x00400000>,
+ <0x0 0xfe280000 0x0 0x00010000>,
+ <0x3 0xbf000000 0x0 0x01000000>;
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE30X2_POWERUP>;
+ reset-names = "pipe";
+ /* bifurcation; lane0 when using 1+1 */
+ status = "disabled";
+
+ pcie3x2_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
gmac0: ethernet@fe2a0000 {
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe2a0000 0x0 0x10000>;
--
2.34.1
From: Frank Wunderlich <[email protected]>
Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and
set PCIe related regulators to always on.
Suggested-by: Peter Geis <[email protected]>
Signed-off-by: Frank Wunderlich <[email protected]>
---
v5:
- rebase on 6.0-rc1
- add pinctrl for pcie
- fix ngff pwr_en_h gpio for hw ref 1.1
v4:
- change u8 lane-map to u32 data-lanes
v3:
- squash lane-map over bifurcation property
- add comment which slot is M2 and which one if mPCIe
- fixes from Peter:
- drop regulator-always-on/regulator-boot-on from regulators
- increase startup-delay-us for regulators
- set phy-mode on PCIe3-phy
- add num-lanes to PCIe overrides
- add usb node for to PCIe/m2
- move lane-map from PCIe controller to PCIe-phy
v2:
- underscores in nodenames
- rockchip,bifurcation to vendor unspecific bifurcation
- fix trailing space
---
.../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 117 ++++++++++++++++++
1 file changed, 117 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index 93d383b8be87..40b90c052634 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -86,6 +86,66 @@ vcc5v0_sys: vcc5v0-sys {
vin-supply = <&dc_12v>;
};
+ pcie30_avdd0v9: pcie30-avdd0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ /* pi6c pcie clock generator feeds both ports */
+ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <200000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
+ vcc3v3_minipcie: vcc3v3-minipcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_minipcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_enable_h>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc3v3_pi6c_05>;
+ };
+
+ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
+ vcc3v3_ngff: vcc3v3-ngff-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_ngff";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ngffpcie_enable_h>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc3v3_pi6c_05>;
+ };
+
vcc5v0_usb: vcc5v0_usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
@@ -513,6 +573,32 @@ rgmii_phy1: ethernet-phy@0 {
};
};
+&pcie30phy {
+ data-lanes = <1 2>;
+ phy-supply = <&vcc3v3_pi6c_05>;
+ status = "okay";
+};
+
+&pcie3x1 {
+ /* M.2 slot */
+ num-lanes = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ngffpcie_reset_h>;
+ reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_ngff>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ /* mPCIe slot */
+ num-lanes = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_reset_h>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_minipcie>;
+ status = "okay";
+};
+
&pinctrl {
leds {
blue_led_pin: blue-led-pin {
@@ -529,6 +615,24 @@ hym8563_int: hym8563-int {
};
};
+ pcie {
+ minipcie_enable_h: minipcie-enable-h {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
+ };
+
+ ngffpcie_enable_h: ngffpcie-enable-h {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
+ };
+
+ minipcie_reset_h: minipcie-reset-h {
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
+ };
+
+ ngffpcie_reset_h: ngffpcie-reset-h {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
+ };
+ };
+
pmic {
pmic_int: pmic_int {
rockchip,pins =
@@ -708,6 +812,19 @@ &usb2phy0_otg {
status = "okay";
};
+&usb2phy1 {
+ /* USB for PCIe/M2 */
+ status = "okay";
+};
+
+&usb2phy1_host {
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ status = "okay";
+};
+
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
--
2.34.1
On 25/08/2022 22:38, Frank Wunderlich wrote:
> From: Frank Wunderlich <[email protected]>
>
> Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and
> set PCIe related regulators to always on.
>
> Suggested-by: Peter Geis <[email protected]>
> Signed-off-by: Frank Wunderlich <[email protected]>
> ---
> v5:
> - rebase on 6.0-rc1
> - add pinctrl for pcie
> - fix ngff pwr_en_h gpio for hw ref 1.1
>
> v4:
> - change u8 lane-map to u32 data-lanes
>
> v3:
> - squash lane-map over bifurcation property
> - add comment which slot is M2 and which one if mPCIe
> - fixes from Peter:
> - drop regulator-always-on/regulator-boot-on from regulators
> - increase startup-delay-us for regulators
> - set phy-mode on PCIe3-phy
> - add num-lanes to PCIe overrides
> - add usb node for to PCIe/m2
> - move lane-map from PCIe controller to PCIe-phy
>
> v2:
> - underscores in nodenames
> - rockchip,bifurcation to vendor unspecific bifurcation
> - fix trailing space
> ---
> .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 117 ++++++++++++++++++
> 1 file changed, 117 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> index 93d383b8be87..40b90c052634 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> @@ -86,6 +86,66 @@ vcc5v0_sys: vcc5v0-sys {
> vin-supply = <&dc_12v>;
> };
>
> + pcie30_avdd0v9: pcie30-avdd0v9 {
Use consistent naming, so if other nodes have "regulator" suffix, use it
here as well.
> + compatible = "regulator-fixed";
> + regulator-name = "pcie30_avdd0v9";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + vin-supply = <&vcc3v3_sys>;
> + };
> +
> + pcie30_avdd1v8: pcie30-avdd1v8 {
Ditto.
> + compatible = "regulator-fixed";
> + regulator-name = "pcie30_avdd1v8";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <&vcc3v3_sys>;
> + };
> +
> + /* pi6c pcie clock generator feeds both ports */
> + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3_pcie";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
> + startup-delay-us = <200000>;
> + vin-supply = <&vcc5v0_sys>;
> + };
> +
Best regards,
Krzysztof
Hi
> Gesendet: Freitag, 26. August 2022 um 08:50 Uhr
> Von: "Krzysztof Kozlowski" <[email protected]>
> On 25/08/2022 22:38, Frank Wunderlich wrote:
> > From: Frank Wunderlich <[email protected]>
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> > index 93d383b8be87..40b90c052634 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> > @@ -86,6 +86,66 @@ vcc5v0_sys: vcc5v0-sys {
> > vin-supply = <&dc_12v>;
> > };
> >
> > + pcie30_avdd0v9: pcie30-avdd0v9 {
>
> Use consistent naming, so if other nodes have "regulator" suffix, use it
> here as well.
only these 3 new have the suffix:
vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator
vcc3v3_minipcie: vcc3v3-minipcie-regulator
vcc3v3_ngff: vcc3v3-ngff-regulator
so i would drop it there...
so i end up with (including existing ones to compare):
vcc3v3_sys: vcc3v3-sys
vcc5v0_sys: vcc5v0-sys
pcie30_avdd0v9: pcie30-avdd0v9
pcie30_avdd1v8: pcie30-avdd1v8
vcc3v3_pi6c_05: vcc3v3-pi6c-05
vcc3v3_minipcie: vcc3v3-minipcie
vcc3v3_ngff: vcc3v3-ngff
vcc5v0_usb: vcc5v0_usb
vcc5v0_usb_host: vcc5v0-usb-host
vcc5v0_usb_otg: vcc5v0-usb-otg
is this ok?
maybe swap avdd* and pcie30 part to have voltage in front of function.
> > + compatible = "regulator-fixed";
> > + regulator-name = "pcie30_avdd0v9";
> > + regulator-always-on;
> > + regulator-boot-on;
> > + regulator-min-microvolt = <900000>;
> > + regulator-max-microvolt = <900000>;
> > + vin-supply = <&vcc3v3_sys>;
> > + };
> > +
> > + pcie30_avdd1v8: pcie30-avdd1v8 {
>
> Ditto.
>
>
> > + compatible = "regulator-fixed";
> > + regulator-name = "pcie30_avdd1v8";
> > + regulator-always-on;
> > + regulator-boot-on;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + vin-supply = <&vcc3v3_sys>;
> > + };
> > +
> > + /* pi6c pcie clock generator feeds both ports */
> > + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc3v3_pcie";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + enable-active-high;
> > + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
> > + startup-delay-us = <200000>;
> > + vin-supply = <&vcc5v0_sys>;
> > + };
> > +
>
> Best regards,
> Krzysztof
>
On Thu, 25 Aug 2022 21:38:31 +0200, Frank Wunderlich wrote:
> This series adds Rockchip PCIe V3 support found on rk3568 SOC.
>
> Compared to PCIeV2 which uses the Naneng combphy, PCIe v3 uses a dedicated
> PCI-phy.
>
> Frank Wunderlich (4):
> dt-bindings: phy: rockchip: add PCIe v3 phy
> dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf
> arm64: dts: rockchip: rk3568: Add PCIe v3 nodes
> arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro
>
> [...]
Applied, thanks!
[2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf
commit: 4e441643b32249b4dac89be063255957f3d2938c
[4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes
commit: faedfa5b40f095d09040c3a040e2f8dee4a36b4b
[5/5] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro
commit: 86973ae0355bc302d5e4c10fa382f6801feb4b90
As stated in the separate mail, I've added the -regulator
suffixes to the regulator node names.
Best regards,
--
Heiko Stuebner <[email protected]>