This patch series adds support for coresight on SDM845 and MSM8996.
* Patch 1 adds device tree nodes for SDM845 coresight components.
* Patch 2 adds device tree nodes for MSM8996 coresight components.
* Patch 3 enables support for ETMv4.2 and enables SDM845 to make
use of same driver(etm4x).
* Patch 4 is a trivial removal of duplicate header file.
Patch 1 and 3 depends on below AOSS QMP patches by Bjorn:
https://patchwork.kernel.org/patch/10749469/
https://patchwork.kernel.org/patch/10749481/
https://patchwork.kernel.org/patch/10749479/
https://patchwork.kernel.org/patch/10749475/
This patch series has been tested on SDM845 MTP and MSM8996
based Dragonboard 820c.
v3:
* Added arm,scatter-gather property as suggested by Suzuki.
v2:
* Added coresight support for msm8996 based on Vivek's patch.
Cleaned up and added coresight cpu debug nodes for msm8996.
* Merged coresight dtsi file into sdm845.dtsi as suggested by Bjorn
* Addressed Mathieu's feedback about masking the minor version in
etm4_arch_supported() and added a comment for reason to bypass
the AMBA bus discovery method.
Sai Prakash Ranjan (3):
arm64: dts: qcom: sdm845: Add Coresight support
coresight: etm4x: Add support to enable ETMv4.2
arm64: dts: qcom: sdm845: Remove the duplicate header inclusion
Vivek Gautam (1):
arm64: dts: qcom: msm8996: Add Coresight support
arch/arm64/boot/dts/qcom/msm8996.dtsi | 448 +++++++++++++++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 449 +++++++++++++++++-
drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
4 files changed, 898 insertions(+), 3 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Vivek Gautam <[email protected]>
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 448 ++++++++++++++++++++++++++
1 file changed, 448 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 99b7495455a6..95a92491a87f 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -429,6 +429,454 @@
reg = <0x300000 0x90000>;
};
+ stm@3002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x3002000 0x1000>,
+ <0x8280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint =
+ <&funnel0_in>;
+ };
+ };
+ };
+ };
+
+ tpiu@3020000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x3020000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ tpiu_in: endpoint {
+ remote-endpoint =
+ <&replicator_out1>;
+ };
+ };
+ };
+ };
+
+ funnel@3021000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3021000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ funnel0_in: endpoint {
+ remote-endpoint =
+ <&stm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@3022000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3022000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ funnel1_in: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel1_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@3025000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3025000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ merge_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&etf_in>;
+ };
+ };
+ };
+ };
+
+ replicator@3026000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x3026000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint =
+ <&etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator_out0: endpoint {
+ remote-endpoint =
+ <&etr_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ replicator_out1: endpoint {
+ remote-endpoint =
+ <&tpiu_in>;
+ };
+ };
+ };
+ };
+
+ etf@3027000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x3027000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ etf_in: endpoint {
+ remote-endpoint =
+ <&merge_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+ };
+
+ etr@3028000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x3028000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator_out0>;
+ };
+ };
+ };
+ };
+
+ /*
+ * On msm8996, we bypass the normal AMBA bus discovery
+ * method by forcing the peripheral ID because of the wrong
+ * value read from PID registers.
+ */
+
+ debug@3810000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ arm,primecell-periphid = <0x000bbd03>;
+ reg = <0x3810000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU0>;
+ };
+
+ etm@3840000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x3840000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU0>;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in0>;
+ };
+ };
+ };
+ };
+
+ debug@3910000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ arm,primecell-periphid = <0x000bbd03>;
+ reg = <0x3910000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU1>;
+ };
+
+ etm@3940000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x3940000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU1>;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@39b0000 { /* APSS Funnel 0 */
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x39b0000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel0_in0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel0_in1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel0_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ debug@3a10000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ arm,primecell-periphid = <0x000bbd03>;
+ reg = <0x3a10000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU2>;
+ };
+
+ etm@3a40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x3a40000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU2>;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_in0>;
+ };
+ };
+ };
+ };
+
+ debug@3b10000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ arm,primecell-periphid = <0x000bbd03>;
+ reg = <0x3b10000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU3>;
+ };
+
+ etm@3b40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x3b40000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU3>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@3bb0000 { /* APSS Funnel 1 */
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3bb0000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel1_in0: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel1_in1: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel1_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@3bc0000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3bc0000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_merge_funnel_in1: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel1_in>;
+ };
+ };
+ };
+ };
+
kryocc: clock-controller@6400000 {
compatible = "qcom,apcc-msm8996";
reg = <0x6400000 0x90000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
This depends on AMBA bus pclk change by Bjorn Andersson [1].
Also depends on patch ("arm64: dts: qcom: sdm845: Increase address
and size cells for soc") [2].
[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 448 +++++++++++++++++++++++++++
1 file changed, 448 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index c27cbd3bcb0a..2c589f7f13a8 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1348,6 +1348,454 @@
};
};
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x06002000 0 0x1000>,
+ <0 0x16280000 0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint =
+ <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x06041000 0 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6043000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x06043000 0 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ funnel2_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in2>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@5 {
+ reg = <5>;
+ funnel2_in5: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6045000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x06045000 0 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint = <&etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ merge_funnel_in2: endpoint {
+ remote-endpoint =
+ <&funnel2_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06046000 0 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etf@6047000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06047000 0 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ etf_in: endpoint {
+ remote-endpoint =
+ <&merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06048000 0 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ /*
+ * On QCOM SDM845, we bypass the normal AMBA bus discovery
+ * method by forcing the peripheral ID because of the wrong
+ * value read from ETM PID registers.
+ */
+
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0 0x07040000 0 0x1000>;
+
+ cpu = <&CPU0>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0 0x07140000 0 0x1000>;
+
+ cpu = <&CPU1>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0 0x07240000 0 0x1000>;
+
+ cpu = <&CPU2>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0 0x07340000 0 0x1000>;
+
+ cpu = <&CPU3>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ etm@7440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0 0x07440000 0 0x1000>;
+
+ cpu = <&CPU4>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ etm@7540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0 0x07540000 0 0x1000>;
+
+ cpu = <&CPU5>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ etm@7640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0 0x07640000 0 0x1000>;
+
+ cpu = <&CPU6>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ etm@7740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0 0x07740000 0 0x1000>;
+
+ cpu = <&CPU7>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@7800000 { /* APSS Funnel */
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x07800000 0 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint =
+ <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint =
+ <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint =
+ <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint =
+ <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint =
+ <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint =
+ <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint =
+ <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint =
+ <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7810000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x07810000 0 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel2_in5>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ apss_merge_funnel_in: endpoint {
+ remote-endpoint =
+ <&apss_funnel_out>;
+ };
+ };
+ };
+ };
+
usb_1_hsphy: phy@88e2000 {
compatible = "qcom,sdm845-qusb2-phy";
reg = <0x88e2000 0x400>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Remove the duplicate inclusion of qcom,gcc-sdm845.h
mistakenly introduced by commit 6e17f8140521 ("arm64:
dts: sdm845: add prng-ee node").
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2c589f7f13a8..fc124aeb57e5 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -12,7 +12,6 @@
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
-#include <dt-bindings/clock/qcom,gcc-sdm845.h>
/ {
interrupt-parent = <&intc>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
SDM845 has ETMv4.2 and can use the existing etm4x driver.
But the current etm driver checks only for ETMv4.0 and
errors out for other etm4x versions. This patch adds this
missing support to enable SoC's with ETMv4x to use same
driver by checking only the ETM architecture major version
number.
Without this change, we get below error during etm probe:
/ # dmesg | grep etm
[ 6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22
[ 6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22
[ 6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22
[ 6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22
[ 6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22
[ 6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22
[ 6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22
[ 6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22
With this change, etm probe is successful:
/ # dmesg | grep coresight
[ 6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized
[ 6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized
[ 6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized
[ 6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized
[ 6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized
[ 6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized
[ 6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized
[ 6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 53e2fb6e86f6..93d5f1f3145e 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -55,7 +55,7 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
static bool etm4_arch_supported(u8 arch)
{
- switch (arch) {
+ switch (arch >> 4) {
case ETM_ARCH_V4:
break;
default:
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 52786e9d8926..05d4bd330881 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -136,7 +136,7 @@
#define ETM_MAX_RES_SEL 16
#define ETM_MAX_SS_CMP 8
-#define ETM_ARCH_V4 0x40
+#define ETM_ARCH_V4 0x4
#define ETMv4_SYNC_MASK 0x1F
#define ETM_CYC_THRESHOLD_MASK 0xFFF
#define ETM_CYC_THRESHOLD_DEFAULT 0x100
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 1/18/2019 5:52 PM, Sai Prakash Ranjan wrote:
> SDM845 has ETMv4.2 and can use the existing etm4x driver.
> But the current etm driver checks only for ETMv4.0 and
> errors out for other etm4x versions. This patch adds this
> missing support to enable SoC's with ETMv4x to use same
> driver by checking only the ETM architecture major version
> number.
>
> Without this change, we get below error during etm probe:
>
> / # dmesg | grep etm
> [ 6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22
> [ 6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22
> [ 6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22
> [ 6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22
> [ 6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22
> [ 6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22
> [ 6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22
> [ 6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22
>
> With this change, etm probe is successful:
>
> / # dmesg | grep coresight
> [ 6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized
> [ 6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized
> [ 6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized
> [ 6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized
> [ 6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized
> [ 6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized
> [ 6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized
> [ 6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> ---
> drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
> drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 53e2fb6e86f6..93d5f1f3145e 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -55,7 +55,7 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
>
> static bool etm4_arch_supported(u8 arch)
> {
> - switch (arch) {
> + switch (arch >> 4) {
While this looks good, from what it looks like arch is a combination of
major version
minor version. So, will it be better to masks, and shifts macros instead
of a magic
number shift.
But, frankly it's upto Mathieu to decide the readability of this. So, I
leave it to him.
Thanks
Vivek
> case ETM_ARCH_V4:
> break;
> default:
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 52786e9d8926..05d4bd330881 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -136,7 +136,7 @@
> #define ETM_MAX_RES_SEL 16
> #define ETM_MAX_SS_CMP 8
>
> -#define ETM_ARCH_V4 0x40
> +#define ETM_ARCH_V4 0x4
> #define ETMv4_SYNC_MASK 0x1F
> #define ETM_CYC_THRESHOLD_MASK 0xFFF
> #define ETM_CYC_THRESHOLD_DEFAULT 0x100
Hi Sai,
On Fri, Jan 18, 2019 at 05:52:53PM +0530, Sai Prakash Ranjan wrote:
> Add coresight components found on Qualcomm SDM845 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
>
> ---
> This depends on AMBA bus pclk change by Bjorn Andersson [1].
> Also depends on patch ("arm64: dts: qcom: sdm845: Increase address
> and size cells for soc") [2].
>
> [1] https://lore.kernel.org/lkml/[email protected]/
> [2] https://lore.kernel.org/lkml/[email protected]/
Thank you for making modifications to this patch - I am happy with how it stands
now. I tried to compile it on my side on a 5.0-rc3 kernel and even after
applying the above two patches you pointed out I get the following error:
Error: /home/mpoirier/work/coresight/kernel-maint/arch/arm64/boot/dts/qcom/sdm845.dtsi:1356.31-32 syntax error
FATAL ERROR: Unable to parse input tree
From what I see neither aoss_qmp or AOSS_QMP_QDSS_CLK are defined. Are there
more patches that need to be applied?
Thanks,
Mathieu
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 448 +++++++++++++++++++++++++++
> 1 file changed, 448 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index c27cbd3bcb0a..2c589f7f13a8 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1348,6 +1348,454 @@
> };
> };
>
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0 0x06002000 0 0x1000>,
> + <0 0x16280000 0 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint =
> + <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x06041000 0 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6043000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x06043000 0 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel2_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in2>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@5 {
> + reg = <5>;
> + funnel2_in5: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6045000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x06045000 0 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint = <&etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + merge_funnel_in2: endpoint {
> + remote-endpoint =
> + <&funnel2_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0 0x06046000 0 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6047000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x06047000 0 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint =
> + <&replicator_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + etf_in: endpoint {
> + remote-endpoint =
> + <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x06048000 0 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> + arm,scatter-gather;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint =
> + <&replicator_out>;
> + };
> + };
> + };
> + };
> +
> + /*
> + * On QCOM SDM845, we bypass the normal AMBA bus discovery
> + * method by forcing the peripheral ID because of the wrong
> + * value read from ETM PID registers.
> + */
> +
> + etm@7040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0 0x07040000 0 0x1000>;
> +
> + cpu = <&CPU0>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@7140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0 0x07140000 0 0x1000>;
> +
> + cpu = <&CPU1>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@7240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0 0x07240000 0 0x1000>;
> +
> + cpu = <&CPU2>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@7340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0 0x07340000 0 0x1000>;
> +
> + cpu = <&CPU3>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + etm@7440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0 0x07440000 0 0x1000>;
> +
> + cpu = <&CPU4>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in4>;
> + };
> + };
> + };
> + };
> +
> + etm@7540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0 0x07540000 0 0x1000>;
> +
> + cpu = <&CPU5>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in5>;
> + };
> + };
> + };
> + };
> +
> + etm@7640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0 0x07640000 0 0x1000>;
> +
> + cpu = <&CPU6>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in6>;
> + };
> + };
> + };
> + };
> +
> + etm@7740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0 0x07740000 0 0x1000>;
> +
> + cpu = <&CPU7>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@7800000 { /* APSS Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x07800000 0 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@7810000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x07810000 0 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel2_in5>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +
> usb_1_hsphy: phy@88e2000 {
> compatible = "qcom,sdm845-qusb2-phy";
> reg = <0x88e2000 0x400>;
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
On Mon, Jan 21, 2019 at 04:18:36PM +0530, Vivek Gautam wrote:
>
> On 1/18/2019 5:52 PM, Sai Prakash Ranjan wrote:
> > SDM845 has ETMv4.2 and can use the existing etm4x driver.
> > But the current etm driver checks only for ETMv4.0 and
> > errors out for other etm4x versions. This patch adds this
> > missing support to enable SoC's with ETMv4x to use same
> > driver by checking only the ETM architecture major version
> > number.
> >
> > Without this change, we get below error during etm probe:
> >
> > / # dmesg | grep etm
> > [ 6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22
> > [ 6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22
> > [ 6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22
> > [ 6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22
> > [ 6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22
> > [ 6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22
> > [ 6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22
> > [ 6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22
> >
> > With this change, etm probe is successful:
> >
> > / # dmesg | grep coresight
> > [ 6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized
> > [ 6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized
> > [ 6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized
> > [ 6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized
> > [ 6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized
> > [ 6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized
> > [ 6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized
> > [ 6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized
> >
> > Signed-off-by: Sai Prakash Ranjan <[email protected]>
> > ---
> > drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
> > drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
> > 2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > index 53e2fb6e86f6..93d5f1f3145e 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > @@ -55,7 +55,7 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
> > static bool etm4_arch_supported(u8 arch)
> > {
> > - switch (arch) {
> > + switch (arch >> 4) {
>
>
> While this looks good, from what it looks like arch is a combination of
> major version
> minor version. So, will it be better to masks, and shifts macros instead of
> a magic
> number shift.
> But, frankly it's upto Mathieu to decide the readability of this. So, I
> leave it to him.
The layout of the architecture is already well defined in etm4_init_arch_data()
[1]. As such just doing the following would be fine with me:
/* Mask out the minor version nuber */
switch (arch & 0xf) {
Of course by proceeding this way we don't need to modify the define in
coresight-etm4x.h.
Regards,
Mathieu
[1]. https://elixir.bootlin.com/linux/latest/source/drivers/hwtracing/coresight/coresight-etm4x.c#L508
>
> Thanks
> Vivek
>
> > case ETM_ARCH_V4:
> > break;
> > default:
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 52786e9d8926..05d4bd330881 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -136,7 +136,7 @@
> > #define ETM_MAX_RES_SEL 16
> > #define ETM_MAX_SS_CMP 8
> > -#define ETM_ARCH_V4 0x40
> > +#define ETM_ARCH_V4 0x4
> > #define ETMv4_SYNC_MASK 0x1F
> > #define ETM_CYC_THRESHOLD_MASK 0xFFF
> > #define ETM_CYC_THRESHOLD_DEFAULT 0x100
On Mon, 21 Jan 2019 at 11:48, Mathieu Poirier
<[email protected]> wrote:
>
> On Mon, Jan 21, 2019 at 04:18:36PM +0530, Vivek Gautam wrote:
> >
> > On 1/18/2019 5:52 PM, Sai Prakash Ranjan wrote:
> > > SDM845 has ETMv4.2 and can use the existing etm4x driver.
> > > But the current etm driver checks only for ETMv4.0 and
> > > errors out for other etm4x versions. This patch adds this
> > > missing support to enable SoC's with ETMv4x to use same
> > > driver by checking only the ETM architecture major version
> > > number.
> > >
> > > Without this change, we get below error during etm probe:
> > >
> > > / # dmesg | grep etm
> > > [ 6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22
> > > [ 6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22
> > > [ 6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22
> > > [ 6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22
> > > [ 6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22
> > > [ 6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22
> > > [ 6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22
> > > [ 6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22
> > >
> > > With this change, etm probe is successful:
> > >
> > > / # dmesg | grep coresight
> > > [ 6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized
> > > [ 6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized
> > > [ 6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized
> > > [ 6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized
> > > [ 6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized
> > > [ 6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized
> > > [ 6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized
> > > [ 6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized
> > >
> > > Signed-off-by: Sai Prakash Ranjan <[email protected]>
> > > ---
> > > drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
> > > drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
> > > 2 files changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > > index 53e2fb6e86f6..93d5f1f3145e 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > > @@ -55,7 +55,7 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
> > > static bool etm4_arch_supported(u8 arch)
> > > {
> > > - switch (arch) {
> > > + switch (arch >> 4) {
> >
> >
> > While this looks good, from what it looks like arch is a combination of
> > major version
> > minor version. So, will it be better to masks, and shifts macros instead of
> > a magic
> > number shift.
> > But, frankly it's upto Mathieu to decide the readability of this. So, I
> > leave it to him.
>
> The layout of the architecture is already well defined in etm4_init_arch_data()
> [1]. As such just doing the following would be fine with me:
>
> /* Mask out the minor version nuber */
> switch (arch & 0xf) {
s/0xf/0xf0
Apologies for the confusion.
>
> Of course by proceeding this way we don't need to modify the define in
> coresight-etm4x.h.
>
> Regards,
> Mathieu
>
> [1]. https://elixir.bootlin.com/linux/latest/source/drivers/hwtracing/coresight/coresight-etm4x.c#L508
>
> >
> > Thanks
> > Vivek
> >
> > > case ETM_ARCH_V4:
> > > break;
> > > default:
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > > index 52786e9d8926..05d4bd330881 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > > @@ -136,7 +136,7 @@
> > > #define ETM_MAX_RES_SEL 16
> > > #define ETM_MAX_SS_CMP 8
> > > -#define ETM_ARCH_V4 0x40
> > > +#define ETM_ARCH_V4 0x4
> > > #define ETMv4_SYNC_MASK 0x1F
> > > #define ETM_CYC_THRESHOLD_MASK 0xFFF
> > > #define ETM_CYC_THRESHOLD_DEFAULT 0x100
Hi Mathieu,
On 1/22/2019 12:07 AM, Mathieu Poirier wrote:
> Hi Sai,
>
> On Fri, Jan 18, 2019 at 05:52:53PM +0530, Sai Prakash Ranjan wrote:
>> Add coresight components found on Qualcomm SDM845 SoC.
>>
>> Signed-off-by: Sai Prakash Ranjan <[email protected]>
>>
>> ---
>> This depends on AMBA bus pclk change by Bjorn Andersson [1].
>> Also depends on patch ("arm64: dts: qcom: sdm845: Increase address
>> and size cells for soc") [2].
>>
>> [1] https://lore.kernel.org/lkml/[email protected]/
>> [2] https://lore.kernel.org/lkml/[email protected]/
>
> Thank you for making modifications to this patch - I am happy with how it stands
> now. I tried to compile it on my side on a 5.0-rc3 kernel and even after
> applying the above two patches you pointed out I get the following error:
>
> Error: /home/mpoirier/work/coresight/kernel-maint/arch/arm64/boot/dts/qcom/sdm845.dtsi:1356.31-32 syntax error
> FATAL ERROR: Unable to parse input tree
>
> From what I see neither aoss_qmp or AOSS_QMP_QDSS_CLK are defined. Are there
> more patches that need to be applied?
>
Sorry, I added all the dependent patches in the cover letter, but
forgot to add the main dependent patch here, now added in v4.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 1/22/2019 3:07 AM, Mathieu Poirier wrote:
> On Mon, 21 Jan 2019 at 11:48, Mathieu Poirier
> <[email protected]> wrote:
>>
>> On Mon, Jan 21, 2019 at 04:18:36PM +0530, Vivek Gautam wrote:
>>>
>>> On 1/18/2019 5:52 PM, Sai Prakash Ranjan wrote:
>>>> SDM845 has ETMv4.2 and can use the existing etm4x driver.
>>>> But the current etm driver checks only for ETMv4.0 and
>>>> errors out for other etm4x versions. This patch adds this
>>>> missing support to enable SoC's with ETMv4x to use same
>>>> driver by checking only the ETM architecture major version
>>>> number.
>>>>
>>>> Without this change, we get below error during etm probe:
>>>>
>>>> / # dmesg | grep etm
>>>> [ 6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22
>>>> [ 6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22
>>>> [ 6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22
>>>> [ 6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22
>>>> [ 6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22
>>>> [ 6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22
>>>> [ 6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22
>>>> [ 6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22
>>>>
>>>> With this change, etm probe is successful:
>>>>
>>>> / # dmesg | grep coresight
>>>> [ 6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized
>>>> [ 6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized
>>>> [ 6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized
>>>> [ 6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized
>>>> [ 6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized
>>>> [ 6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized
>>>> [ 6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized
>>>> [ 6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized
>>>>
>>>> Signed-off-by: Sai Prakash Ranjan <[email protected]>
>>>> ---
>>>> drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
>>>> drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
>>>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> index 53e2fb6e86f6..93d5f1f3145e 100644
>>>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> @@ -55,7 +55,7 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
>>>> static bool etm4_arch_supported(u8 arch)
>>>> {
>>>> - switch (arch) {
>>>> + switch (arch >> 4) {
>>>
>>>
>>> While this looks good, from what it looks like arch is a combination of
>>> major version
>>> minor version. So, will it be better to masks, and shifts macros instead of
>>> a magic
>>> number shift.
>>> But, frankly it's upto Mathieu to decide the readability of this. So, I
>>> leave it to him.
>>
>> The layout of the architecture is already well defined in etm4_init_arch_data()
>> [1]. As such just doing the following would be fine with me:
>>
>> /* Mask out the minor version nuber */
>> switch (arch & 0xf) {
>
> s/0xf/0xf0
>
> Apologies for the confusion.
>
Thanks Mathieu, made this change in v4 of this series.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation