Good Morning,
This is my patch series that I have maintained out of tree until the
combophy driver landed.
Patch 1 fixes the grf dt binding from the combophy merge.
Patches 2 and 3 add the dt bindings for the grf changes necessary for
this series.
Patch 4 adds support to the grf driver to set the rk3566 otg clock
source.
Patch 5 is a downstream patch ported forward to shut down the usb3 clock
when the controller is operating in usb2 mode.
Patches 6, 7, and 8 clean up the dwc3-of-simple driver, allow the use of
of-match-data, and add the compatible for the rk3568.
Patch 9 adds the dwc3 nodes to the rk356x device tree includes.
Patch 10 enables the dwc3 nodes on the Quartz64 Model A.
Patch 11 enables the dwc3 nodes on the rk3568-evb.
Please review and apply.
Very Respectfully,
Peter Geis
Changelog:
v2:
- Add a dt-bindings fix for grf.yaml
- Unify the reset names.
- Constrain the force usb2 clock dwc3 patch to only supported variants of
the ip.
- Change dwc3-of-simple to support of-match-data.
- Drop the PCLK-PIPE clk.
- Rename the usb nodes to be more friendly.
- Add the rk3568-evb enable patch.
Bin Yang (1):
usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode
Michael Riesch (1):
arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10
Peter Geis (9):
dt-bindings: soc: grf: fix rk3568 usb definitions
dt-bindings: soc: grf: add rk3566-pipe-grf compatible
dt-bindings: usb: dwc3: add description for rk3568
soc: rockchip: set dwc3 clock for rk3566
usb: dwc3: reorder dwc-of-simple compatibles
usb: dwc3: convert dwc3-of-simple to use match-data
usb: dwc3: add rk3568 dwc3 support
arm64: dts: rockchip: add rk356x dwc3 usb3 nodes
arm64: dts: rockchip: enable dwc3 on quartz64-a
.../devicetree/bindings/soc/rockchip/grf.yaml | 5 +-
.../bindings/usb/rockchip,dwc3.yaml | 2 +
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 37 +++++++++++++++
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 12 +++++
.../boot/dts/rockchip/rk3568-evb1-v10.dts | 46 +++++++++++++++++++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 ++++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 +++++++++++++++++-
drivers/soc/rockchip/grf.c | 17 +++++++
drivers/usb/dwc3/core.c | 5 ++
drivers/usb/dwc3/core.h | 1 +
drivers/usb/dwc3/dwc3-of-simple.c | 43 +++++++++++++----
11 files changed, 210 insertions(+), 12 deletions(-)
--
2.25.1
The quartz64 model a has support for both the dwc3 otg port and the dwc3
host port. Add the otg power supply and dwc3 nodes to the device tree to
enable support for these.
Signed-off-by: Peter Geis <[email protected]>
---
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index dd7f4b9b686b..141a433429b5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -151,6 +151,16 @@ vcc5v0_usb20_host: vcc5v0_usb20_host {
vin-supply = <&vcc5v0_usb>;
};
+ vcc5v0_usb20_otg: vcc5v0_usb20_otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_usb20_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dcdc_boost>;
+ };
+
vcc3v3_sd: vcc3v3_sd {
compatible = "regulator-fixed";
enable-active-low;
@@ -187,6 +197,10 @@ vcc_wl: vcc_wl {
};
};
+&combphy1 {
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
@@ -672,6 +686,29 @@ &usb_host1_ohci {
status = "okay";
};
+&usb_host0_xhci {
+ status = "okay";
+};
+
+/* usb3 controller is muxed with sata1 */
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb20_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb20_otg>;
+ status = "okay";
+};
+
&usb2phy1 {
status = "okay";
};
--
2.25.1
The rk3568 dwc3 controller is backwards compatible with the rk3399 dwc3
controller.
Add support for it to the dwc3-of-simple driver.
Signed-off-by: Peter Geis <[email protected]>
---
drivers/usb/dwc3/dwc3-of-simple.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index 57ba9427ad74..d9d1c5bfac3f 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -195,6 +195,10 @@ static const struct of_device_id of_dwc3_simple_match[] = {
.compatible = "rockchip,rk3399-dwc3",
.data = &dwc3_of_simple_data_rk3399,
},
+ {
+ .compatible = "rockchip,rk3568-dwc3",
+ .data = &dwc3_of_simple_data_rk3399,
+ },
{
.compatible = "sprd,sc9860-dwc3",
},
--
2.25.1
Add the dwc3 device nodes to the rk356x device trees.
The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.
The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.
Signed-off-by: Peter Geis <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 12 +++++++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 +++++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 +++++++++++++++++++++++-
3 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
index 3839eef5e4f7..a57eb68faba2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -6,6 +6,10 @@ / {
compatible = "rockchip,rk3566";
};
+&pipegrf {
+ compatible = "rockchip,rk3566-pipe-grf", "syscon";
+};
+
&power {
power-domain@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
@@ -18,3 +22,11 @@ power-domain@RK3568_PD_PIPE {
#power-domain-cells = <0>;
};
};
+
+&usb_host0_xhci {
+ phys = <&usb2phy0_otg>;
+ phy-names = "usb2-phy";
+ extcon = <&usb2phy0>;
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 5b0f528d6818..8ba9334f9753 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -99,6 +99,10 @@ opp-1992000000 {
};
};
+&pipegrf {
+ compatible = "rockchip,rk3568-pipe-grf", "syscon";
+};
+
&power {
power-domain@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
@@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE {
#power-domain-cells = <0>;
};
};
+
+&usb_host0_xhci {
+ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..b22e5a514ad7 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,50 @@ scmi_shmem: sram@0 {
};
};
+ usb_host0_xhci: usb@fcc00000 {
+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+ reg = <0x0 0xfcc00000 0x0 0x400000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
+ <&cru ACLK_USB3OTG0>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk";
+ dr_mode = "host";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3568_PD_PIPE>;
+ resets = <&cru SRST_USB3OTG0>;
+ reset-names = "usb3-otg";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,xhci-trb-ent-quirk;
+ status = "disabled";
+ };
+
+ usb_host1_xhci: usb@fd000000 {
+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+ reg = <0x0 0xfd000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk";
+ dr_mode = "host";
+ phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3568_PD_PIPE>;
+ resets = <&cru SRST_USB3OTG1>;
+ reset-names = "usb3-otg";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
@@ -297,7 +341,6 @@ pmu_io_domains: io-domains {
};
pipegrf: syscon@fdc50000 {
- compatible = "rockchip,rk3568-pipe-grf", "syscon";
reg = <0x0 0xfdc50000 0x0 0x1000>;
};
--
2.25.1
The rk3566 requires special handling for the dwc3-otg clock in order for
the port to function correctly.
Add a binding for the rk3566-pipe-grf so we can handle setup with the
grf driver.
Signed-off-by: Peter Geis <[email protected]>
---
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 5079e9d24af6..75a2b8bb25fb 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -15,6 +15,7 @@ properties:
- items:
- enum:
- rockchip,rk3288-sgrf
+ - rockchip,rk3566-pipe-grf
- rockchip,rk3568-pipe-grf
- rockchip,rk3568-pipe-phy-grf
- rockchip,rk3568-usb2phy-grf
--
2.25.1
Hi Peter,
See comments by rob+dt:
https://lore.kernel.org/linux-rockchip/CAL_JsqJwNdUfoYM8SZmOgMG9iAyZkJ4-kzjjiDDm_mdmghTEOA@mail.gmail.com/
> Presumably you are getting lucky here (with link order). The kernel
> has no logic to decide which driver to bind to if there are 2 matching
> drivers.
Due to the fall back string you make a mess with two drivers.
Don't use dwc3-of-simple.c
(only for rk3399 and legacy support. Not for new SoCs),
because core.c has now reset support.
You are creating a race which driver get probed first.
Handle your quirks in core.
Johan
On 2/26/22 19:41, Peter Geis wrote:
> The rk3568 dwc3 controller is backwards compatible with the rk3399 dwc3
> controller.
> Add support for it to the dwc3-of-simple driver.
>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> drivers/usb/dwc3/dwc3-of-simple.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
> index 57ba9427ad74..d9d1c5bfac3f 100644
> --- a/drivers/usb/dwc3/dwc3-of-simple.c
> +++ b/drivers/usb/dwc3/dwc3-of-simple.c
> @@ -195,6 +195,10 @@ static const struct of_device_id of_dwc3_simple_match[] = {
> .compatible = "rockchip,rk3399-dwc3",
> .data = &dwc3_of_simple_data_rk3399,
> },
> + {
> + .compatible = "rockchip,rk3568-dwc3",
> + .data = &dwc3_of_simple_data_rk3399,
> + },
> {
> .compatible = "sprd,sc9860-dwc3",
> },
On 2/26/22 19:41, Peter Geis wrote:
> Add the dwc3 device nodes to the rk356x device trees.
> The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable
> dwc3 host controller.
> The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable
> dwc3 host controller.
>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> arch/arm64/boot/dts/rockchip/rk3566.dtsi | 12 +++++++
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 +++++
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 +++++++++++++++++++++++-
> 3 files changed, 65 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
> index 3839eef5e4f7..a57eb68faba2 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
> @@ -6,6 +6,10 @@ / {
> compatible = "rockchip,rk3566";
> };
>
> +&pipegrf {
> + compatible = "rockchip,rk3566-pipe-grf", "syscon";
> +};
> +
> &power {
> power-domain@RK3568_PD_PIPE {
> reg = <RK3568_PD_PIPE>;
> @@ -18,3 +22,11 @@ power-domain@RK3568_PD_PIPE {
> #power-domain-cells = <0>;
> };
> };
> +
> +&usb_host0_xhci {
> + phys = <&usb2phy0_otg>;
> + phy-names = "usb2-phy";
> + extcon = <&usb2phy0>;
> + maximum-speed = "high-speed";
> + snps,dis_u2_susphy_quirk;
> +};
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 5b0f528d6818..8ba9334f9753 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -99,6 +99,10 @@ opp-1992000000 {
> };
> };
>
> +&pipegrf {
> + compatible = "rockchip,rk3568-pipe-grf", "syscon";
> +};
> +
> &power {
> power-domain@RK3568_PD_PIPE {
> reg = <RK3568_PD_PIPE>;
> @@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE {
> #power-domain-cells = <0>;
> };
> };
> +
> +&usb_host0_xhci {
> + phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
> + phy-names = "usb2-phy", "usb3-phy";
> +};
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 7cdef800cb3c..b22e5a514ad7 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -230,6 +230,50 @@ scmi_shmem: sram@0 {
> };
> };
>
> + usb_host0_xhci: usb@fcc00000 {
> + compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
> + reg = <0x0 0xfcc00000 0x0 0x400000>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
> + <&cru ACLK_USB3OTG0>;
> + clock-names = "ref_clk", "suspend_clk",
> + "bus_clk";
> + dr_mode = "host";
> + phy_type = "utmi_wide";
> + power-domains = <&power RK3568_PD_PIPE>;
When both usb_host0_xhci and usb_host1_xhci are connected to a usb2phy
and the combphy's disabled there's no PCLK_PIPE enabled.
Fix logic for RK3568_PD_PIPE by adding the USB3 clocks.
> + resets = <&cru SRST_USB3OTG0>;
> + reset-names = "usb3-otg";
remove
snps,dwc3.yaml only mentions the "resets" because
devm_reset_control_array_get_optional_shared is used.
reset-names is only a rk3399 legacy that I included due to the YAML
conversion.
With unevaluatedProperties now working "resets" also could be removed
from rockchip,dwc3.yaml I think.
https://github.com/torvalds/linux/commit/2f8e928408885dad5d8d6afefacb82100b6b62c7
Added properties for rk3399 are:
power-domains
resets
reset-names
> + snps,dis_enblslpm_quirk;
> + snps,dis-u2-freeclk-exists-quirk;
> + snps,dis-del-phy-power-chg-quirk;
> + snps,dis-tx-ipgap-linecheck-quirk;
sort
> + snps,xhci-trb-ent-quirk;
???
check snps,dwc3.yaml
> + status = "disabled";
> + };
> +
> + usb_host1_xhci: usb@fd000000 {
> + compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
> + reg = <0x0 0xfd000000 0x0 0x400000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
> + <&cru ACLK_USB3OTG1>;
> + clock-names = "ref_clk", "suspend_clk",
> + "bus_clk";
> + dr_mode = "host";
> + phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
> + phy-names = "usb2-phy", "usb3-phy";
> + phy_type = "utmi_wide";
> + power-domains = <&power RK3568_PD_PIPE>;
dito
> + resets = <&cru SRST_USB3OTG1>;
> + reset-names = "usb3-otg";
remove
> + snps,dis_enblslpm_quirk;
> + snps,dis-u2-freeclk-exists-quirk;
> + snps,dis_u2_susphy_quirk;
> + snps,dis-del-phy-power-chg-quirk;
> + snps,dis-tx-ipgap-linecheck-quirk;
sort
> + status = "disabled";
> + };
> +
> gic: interrupt-controller@fd400000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
> @@ -297,7 +341,6 @@ pmu_io_domains: io-domains {
> };
>
> pipegrf: syscon@fdc50000 {
> - compatible = "rockchip,rk3568-pipe-grf", "syscon";
> reg = <0x0 0xfdc50000 0x0 0x1000>;
> };
>
On Sat, Feb 26, 2022 at 4:43 PM Johan Jonker <[email protected]> wrote:
>
> Hi Peter,
>
> See comments by rob+dt:
>
> https://lore.kernel.org/linux-rockchip/CAL_JsqJwNdUfoYM8SZmOgMG9iAyZkJ4-kzjjiDDm_mdmghTEOA@mail.gmail.com/
>
> > Presumably you are getting lucky here (with link order). The kernel
> > has no logic to decide which driver to bind to if there are 2 matching
> > drivers.
>
> Due to the fall back string you make a mess with two drivers.
> Don't use dwc3-of-simple.c
> (only for rk3399 and legacy support. Not for new SoCs),
> because core.c has now reset support.
> You are creating a race which driver get probed first.
> Handle your quirks in core.
I finally understood what you were trying to get at here.
After some testing, it seems the core driver handles everything we need now.
This makes me want to revisit the rk3399 support.
Thanks!
>
> Johan
>
> On 2/26/22 19:41, Peter Geis wrote:
> > The rk3568 dwc3 controller is backwards compatible with the rk3399 dwc3
> > controller.
> > Add support for it to the dwc3-of-simple driver.
> >
> > Signed-off-by: Peter Geis <[email protected]>
> > ---
> > drivers/usb/dwc3/dwc3-of-simple.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
> > index 57ba9427ad74..d9d1c5bfac3f 100644
> > --- a/drivers/usb/dwc3/dwc3-of-simple.c
> > +++ b/drivers/usb/dwc3/dwc3-of-simple.c
> > @@ -195,6 +195,10 @@ static const struct of_device_id of_dwc3_simple_match[] = {
> > .compatible = "rockchip,rk3399-dwc3",
> > .data = &dwc3_of_simple_data_rk3399,
> > },
> > + {
> > + .compatible = "rockchip,rk3568-dwc3",
> > + .data = &dwc3_of_simple_data_rk3399,
> > + },
> > {
> > .compatible = "sprd,sc9860-dwc3",
> > },
On Sat, Feb 26, 2022 at 6:01 PM Johan Jonker <[email protected]> wrote:
>
>
>
> On 2/26/22 19:41, Peter Geis wrote:
> > Add the dwc3 device nodes to the rk356x device trees.
> > The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable
> > dwc3 host controller.
> > The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable
> > dwc3 host controller.
> >
> > Signed-off-by: Peter Geis <[email protected]>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3566.dtsi | 12 +++++++
> > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 +++++
> > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 +++++++++++++++++++++++-
> > 3 files changed, 65 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
> > index 3839eef5e4f7..a57eb68faba2 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
> > @@ -6,6 +6,10 @@ / {
> > compatible = "rockchip,rk3566";
> > };
> >
> > +&pipegrf {
> > + compatible = "rockchip,rk3566-pipe-grf", "syscon";
> > +};
> > +
> > &power {
> > power-domain@RK3568_PD_PIPE {
> > reg = <RK3568_PD_PIPE>;
> > @@ -18,3 +22,11 @@ power-domain@RK3568_PD_PIPE {
> > #power-domain-cells = <0>;
> > };
> > };
> > +
> > +&usb_host0_xhci {
> > + phys = <&usb2phy0_otg>;
> > + phy-names = "usb2-phy";
> > + extcon = <&usb2phy0>;
> > + maximum-speed = "high-speed";
> > + snps,dis_u2_susphy_quirk;
> > +};
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > index 5b0f528d6818..8ba9334f9753 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > @@ -99,6 +99,10 @@ opp-1992000000 {
> > };
> > };
> >
> > +&pipegrf {
> > + compatible = "rockchip,rk3568-pipe-grf", "syscon";
> > +};
> > +
> > &power {
> > power-domain@RK3568_PD_PIPE {
> > reg = <RK3568_PD_PIPE>;
> > @@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE {
> > #power-domain-cells = <0>;
> > };
> > };
> > +
> > +&usb_host0_xhci {
> > + phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
> > + phy-names = "usb2-phy", "usb3-phy";
> > +};
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index 7cdef800cb3c..b22e5a514ad7 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -230,6 +230,50 @@ scmi_shmem: sram@0 {
> > };
> > };
> >
> > + usb_host0_xhci: usb@fcc00000 {
> > + compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
> > + reg = <0x0 0xfcc00000 0x0 0x400000>;
> > + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
> > + <&cru ACLK_USB3OTG0>;
> > + clock-names = "ref_clk", "suspend_clk",
> > + "bus_clk";
> > + dr_mode = "host";
> > + phy_type = "utmi_wide";
>
> > + power-domains = <&power RK3568_PD_PIPE>;
>
> When both usb_host0_xhci and usb_host1_xhci are connected to a usb2phy
> and the combphy's disabled there's no PCLK_PIPE enabled.
> Fix logic for RK3568_PD_PIPE by adding the USB3 clocks.
>
>
> > + resets = <&cru SRST_USB3OTG0>;
>
> > + reset-names = "usb3-otg";
>
> remove
>
> snps,dwc3.yaml only mentions the "resets" because
> devm_reset_control_array_get_optional_shared is used.
> reset-names is only a rk3399 legacy that I included due to the YAML
> conversion.
> With unevaluatedProperties now working "resets" also could be removed
> from rockchip,dwc3.yaml I think.
I've tested removing the reset entirely, and it seems the issues that
affected the rk3399 do not affect us here.
>
> https://github.com/torvalds/linux/commit/2f8e928408885dad5d8d6afefacb82100b6b62c7
> Added properties for rk3399 are:
> power-domains
> resets
> reset-names
>
> > + snps,dis_enblslpm_quirk;
> > + snps,dis-u2-freeclk-exists-quirk;
> > + snps,dis-del-phy-power-chg-quirk;
> > + snps,dis-tx-ipgap-linecheck-quirk;
>
> sort
>
> > + snps,xhci-trb-ent-quirk;
>
> ???
>
> check snps,dwc3.yaml
I've tried dropping all of these and testing all the configurations I
can think of.
The only one we seem to absolutely need is snps,dis_u2_susphy_quirk,
without which sometimes devices fail to enumerate after being removed.
The only weird behavior I found was on the Pinenote, where there is
only the OTG port and when a state change happens from host to device
mode the controller locks up the AXI bus for a few seconds until it
times out and gets reset by core.
OTG support is still a work in progress here though and is not supported yet.
TLDR: I'll be dropping all the quirks that have no apparent effect in
the v3, they can be added in if needed following broader testing.
Thanks for all the insight here!
>
> > + status = "disabled";
> > + };
> > +
> > + usb_host1_xhci: usb@fd000000 {
> > + compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
> > + reg = <0x0 0xfd000000 0x0 0x400000>;
> > + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
> > + <&cru ACLK_USB3OTG1>;
> > + clock-names = "ref_clk", "suspend_clk",
> > + "bus_clk";
> > + dr_mode = "host";
> > + phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
> > + phy-names = "usb2-phy", "usb3-phy";
> > + phy_type = "utmi_wide";
>
> > + power-domains = <&power RK3568_PD_PIPE>;
>
> dito
>
> > + resets = <&cru SRST_USB3OTG1>;
>
> > + reset-names = "usb3-otg";
>
> remove
>
> > + snps,dis_enblslpm_quirk;
> > + snps,dis-u2-freeclk-exists-quirk;
> > + snps,dis_u2_susphy_quirk;
> > + snps,dis-del-phy-power-chg-quirk;
> > + snps,dis-tx-ipgap-linecheck-quirk;
>
> sort
>
> > + status = "disabled";
> > + };
> > +
> > gic: interrupt-controller@fd400000 {
> > compatible = "arm,gic-v3";
> > reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
> > @@ -297,7 +341,6 @@ pmu_io_domains: io-domains {
> > };
> >
> > pipegrf: syscon@fdc50000 {
> > - compatible = "rockchip,rk3568-pipe-grf", "syscon";
> > reg = <0x0 0xfdc50000 0x0 0x1000>;
> > };
> >