LinuxLists.cc - [PATCH v2 0/1] arm64: dts: mt8195: Add Ethernet controller

2022-10-19 10:25:49

Subject: [PATCH v2 0/1] arm64: dts: mt8195: Add Ethernet controller

Changes in v2:
1. modify pinctrl node used by ethernet to match rules in pinctrl-mt8195.yaml,
as comments from Krzysztof.
2. remove "mac-address" property in ethernet node as comments from Krzysztof.

Changes in v1:
add dts node for MT8195 Ethernet controller

Biao Huang (1):
arm64: dts: mt8195: Add Ethernet controller

arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 88 ++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 +++++++++++++++++++
2 files changed, 174 insertions(+)

--
2.18.0

2022-10-19 13:21:45

by Biao Huang (黄彪)

[permalink] [raw]

Subject: [PATCH v2] arm64: dts: mt8195: Add Ethernet controller

Add Ethernet controller node for mt8195.

Signed-off-by: Biao Huang <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 88 ++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 +++++++++++++++++++
2 files changed, 174 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
index 4fbd99eb496a..0e8496d837ef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
@@ -258,6 +258,72 @@ &mt6359_vsram_others_ldo_reg {
};

&pio {
+ eth_default_pins: eth-default-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
+ <PINMUX_GPIO78__FUNC_GBE_TXD2>,
+ <PINMUX_GPIO79__FUNC_GBE_TXD1>,
+ <PINMUX_GPIO80__FUNC_GBE_TXD0>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
+ <PINMUX_GPIO88__FUNC_GBE_TXEN>,
+ <PINMUX_GPIO87__FUNC_GBE_RXDV>,
+ <PINMUX_GPIO86__FUNC_GBE_RXC>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
+ <PINMUX_GPIO82__FUNC_GBE_RXD2>,
+ <PINMUX_GPIO83__FUNC_GBE_RXD1>,
+ <PINMUX_GPIO84__FUNC_GBE_RXD0>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
+ <PINMUX_GPIO90__FUNC_GBE_MDIO>;
+ input-enable;
+ };
+ pins-power {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ output-high;
+ };
+ };
+
+ eth_sleep_pins: eth-sleep-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
+ <PINMUX_GPIO78__FUNC_GPIO78>,
+ <PINMUX_GPIO79__FUNC_GPIO79>,
+ <PINMUX_GPIO80__FUNC_GPIO80>;
+ };
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
+ <PINMUX_GPIO88__FUNC_GPIO88>,
+ <PINMUX_GPIO87__FUNC_GPIO87>,
+ <PINMUX_GPIO86__FUNC_GPIO86>;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
+ <PINMUX_GPIO82__FUNC_GPIO82>,
+ <PINMUX_GPIO83__FUNC_GPIO83>,
+ <PINMUX_GPIO84__FUNC_GPIO84>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
+ <PINMUX_GPIO90__FUNC_GPIO90>;
+ input-disable;
+ bias-disable;
+ };
+ pins-power {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ input-disable;
+ bias-disable;
+ };
+ };
+
gpio_keys_pins: gpio-keys-pins {
pins {
pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
@@ -434,6 +500,28 @@ &xhci0 {
status = "okay";
};

+&eth {
+ phy-mode ="rgmii-rxid";
+ phy-handle = <&ethernet_phy0>;
+ snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
+ snps,reset-delays-us = <0 10000 10000>;
+ mediatek,tx-delay-ps = <2030>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&eth_default_pins>;
+ pinctrl-1 = <&eth_sleep_pins>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethernet_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ };
+ };
+};
+
&xhci1 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..7f7d9f8e72ee 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1042,6 +1042,92 @@ spis1: spi@1101e000 {
status = "disabled";
};

+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+ snps,tx-sched-wrr;
+ queue0 {
+ snps,weight = <0x10>;
+ snps,dcb-algorithm;
+ snps,priority = <0x0>;
+ };
+ queue1 {
+ snps,weight = <0x11>;
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+ queue2 {
+ snps,weight = <0x12>;
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+ queue3 {
+ snps,weight = <0x13>;
+ snps,dcb-algorithm;
+ snps,priority = <0x3>;
+ };
+ };
+
+ eth: ethernet@11021000 {
+ compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
+ reg = <0 0x11021000 0 0x4000>;
+ interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "macirq";
+ clock-names = "axi",
+ "apb",
+ "mac_cg",
+ "mac_main",
+ "ptp_ref",
+ "rmii_internal";
+ clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
+ <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
+ <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>,
+ <&topckgen CLK_TOP_SNPS_ETH_250M>,
+ <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+ <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
+ assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
+ <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+ <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
+ <&topckgen CLK_TOP_ETHPLL_D8>,
+ <&topckgen CLK_TOP_ETHPLL_D10>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
+ mediatek,pericfg = <&infracfg_ao>;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ snps,clk-csr = <0>;
+ status = "disabled";
+ };
+
xhci0: usb@11200000 {
compatible = "mediatek,mt8195-xhci",
"mediatek,mtk-xhci";
--
2.25.1

2022-10-19 15:37:13

by AngeloGioacchino Del Regno

[permalink] [raw]

Subject: Re: [PATCH v2] arm64: dts: mt8195: Add Ethernet controller

Il 19/10/22 11:15, Biao Huang ha scritto:
> Add Ethernet controller node for mt8195.
>
> Signed-off-by: Biao Huang <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 88 ++++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 +++++++++++++++++++
> 2 files changed, 174 insertions(+)
>

..snip..

> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..7f7d9f8e72ee 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1042,6 +1042,92 @@ spis1: spi@1101e000 {
> status = "disabled";
> };
>
> + stmmac_axi_setup: stmmac-axi-config {

Didn't you get a warning during dtb build for these ones?
And if you did, why have you ignored it? :-)

> + snps,wr_osr_lmt = <0x7>;
> + snps,rd_osr_lmt = <0x7>;
> + snps,blen = <0 0 0 0 16 8 4>;
> + };
> +

..snip..

> +
> + eth: ethernet@11021000 {
> + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
> + reg = <0 0x11021000 0 0x4000>;
> + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "macirq";
> + clock-names = "axi",
> + "apb",
> + "mac_cg",
> + "mac_main",
> + "ptp_ref",
> + "rmii_internal";
> + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
> + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
> + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>,
> + <&topckgen CLK_TOP_SNPS_ETH_250M>,
> + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
> + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
> + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
> + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
> + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
> + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
> + <&topckgen CLK_TOP_ETHPLL_D8>,
> + <&topckgen CLK_TOP_ETHPLL_D10>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
> + mediatek,pericfg = <&infracfg_ao>;
> + snps,axi-config = <&stmmac_axi_setup>;
> + snps,mtl-rx-config = <&mtl_rx_setup>;
> + snps,mtl-tx-config = <&mtl_tx_setup>;
> + snps,txpbl = <16>;
> + snps,rxpbl = <16>;
> + snps,clk-csr = <0>;
> + status = "disabled";

Please move stmmac-axi-config, rx-queues-config, tx-queues-config here as a subnode
or in the root node, respecting address/size cells being zero.
Of course adding that here means also specifying {address,size}-cells = <0> in this
ethernet node.

Regards,
Angelo

2022-10-20 02:25:14

by Biao Huang (黄彪)

[permalink] [raw]

Subject: Re: [PATCH v2] arm64: dts: mt8195: Add Ethernet controller

Dear Angelo,
Thanks for your comments!

On Wed, 2022-10-19 at 15:57 +0200, AngeloGioacchino Del Regno wrote:
> Il 19/10/22 11:15, Biao Huang ha scritto:
> > Add Ethernet controller node for mt8195.
> >
> > Signed-off-by: Biao Huang <[email protected]>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 88
> > ++++++++++++++++++++
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86
> > +++++++++++++++++++
> > 2 files changed, 174 insertions(+)
> >
>
> ..snip..
>
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 905d1a90b406..7f7d9f8e72ee 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1042,6 +1042,92 @@ spis1: spi@1101e000 {
> > status = "disabled";
> > };
> >
> > + stmmac_axi_setup: stmmac-axi-config {
>
> Didn't you get a warning during dtb build for these ones?
> And if you did, why have you ignored it? :-)
I checked some dts, they keep stmmac-axi-config outside ethernet node,
so I keep the similar way with them, maybe that's old style.
>
> > + snps,wr_osr_lmt = <0x7>;
> > + snps,rd_osr_lmt = <0x7>;
> > + snps,blen = <0 0 0 0 16 8 4>;
> > + };
> > +
>
> ..snip..
>
> > +
> > + eth: ethernet@11021000 {
> > + compatible = "mediatek,mt8195-gmac",
> > "snps,dwmac-5.10a";
> > + reg = <0 0x11021000 0 0x4000>;
> > + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + interrupt-names = "macirq";
> > + clock-names = "axi",
> > + "apb",
> > + "mac_cg",
> > + "mac_main",
> > + "ptp_ref",
> > + "rmii_internal";
> > + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
> > + <&pericfg_ao
> > CLK_PERI_AO_ETHERNET_BUS>,
> > + <&pericfg_ao
> > CLK_PERI_AO_ETHERNET_MAC>,
> > + <&topckgen CLK_TOP_SNPS_ETH_250M>,
> > + <&topckgen
> > CLK_TOP_SNPS_ETH_62P4M_PTP>,
> > + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
> > + assigned-clocks = <&topckgen
> > CLK_TOP_SNPS_ETH_250M>,
> > + <&topckgen
> > CLK_TOP_SNPS_ETH_62P4M_PTP>,
> > + <&topckgen
> > CLK_TOP_SNPS_ETH_50M_RMII>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_ETHPLL_D2>,
> > + <&topckgen
> > CLK_TOP_ETHPLL_D8>,
> > + <&topckgen
> > CLK_TOP_ETHPLL_D10>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_ETHER>;
> > + mediatek,pericfg = <&infracfg_ao>;
> > + snps,axi-config = <&stmmac_axi_setup>;
> > + snps,mtl-rx-config = <&mtl_rx_setup>;
> > + snps,mtl-tx-config = <&mtl_tx_setup>;
> > + snps,txpbl = <16>;
> > + snps,rxpbl = <16>;
> > + snps,clk-csr = <0>;
> > + status = "disabled";
>
> Please move stmmac-axi-config, rx-queues-config, tx-queues-config
> here as a subnode
> or in the root node, respecting address/size cells being zero.
> Of course adding that here means also specifying {address,size}-cells
> = <0> in this
> ethernet node.
OK, I'll move them to ethernet node, and add address/size-cells in
thernet node.
>
> Regards,
> Angelo
Best Regards!
Biao