Thosre are the only missing parts for PCI to work on HiKey970 and
for USB on HiKey960 and HiKey 970 boards.
John Stultz (1):
arm64: dts: hisilicon: Add usb mux hub for hikey960
Manivannan Sadhasivam (1):
arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller
hardware
Mauro Carvalho Chehab (4):
dt-bindings: clock: hi3670-clock.txt: add pmctrl compatible
dt-bindings: usb: hisilicon,hi3670-dwc3: add binding for Kirin970
arm64: dts: hisilicon: Add support for Hikey 970 USB3 PHY
arm64: dts: hisilicon: Add usb mux hub for hikey970
Yu Chen (1):
dt-bindings: misc: add schema for USB hub on Kirin devices
.../bindings/clock/hi3670-clock.txt | 1 +
.../bindings/misc/hisilicon,hikey-usb.yaml | 87 ++++++++++
.../bindings/usb/hisilicon,hi3670-dwc3.yaml | 105 +++++++++++
.../boot/dts/hisilicon/hi3660-hikey960.dts | 35 +++-
.../boot/dts/hisilicon/hi3670-hikey970.dts | 106 ++++++++++++
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 163 ++++++++++++++++++
6 files changed, 495 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/misc/hisilicon,hikey-usb.yaml
create mode 100644 Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
--
2.33.1
Add documentation for the DWC3 USB3 controller found on Kirin970
CPUs.
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover.
See [PATCH RESEND 0/7] at: https://lore.kernel.org/all/[email protected]/
.../bindings/usb/hisilicon,hi3670-dwc3.yaml | 105 ++++++++++++++++++
1 file changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml b/Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
new file mode 100644
index 000000000000..309a876ea615
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/hisilicon,hi3670-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Kirin970 USB3 Controller
+
+maintainers:
+ - Mauro Carvalho Chehab <[email protected]>
+
+description:
+ Bindings for the USB3 DWC3 controller present on Kirin970.
+
+properties:
+ compatible:
+ const: hisilicon,hi3670-dwc3
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: clk_gate_abb_usb
+ - const: hclk_gate_usb3otg
+ - const: clk_gate_usb3otg_ref
+ - const: aclk_gate_usb3dvfs
+
+ ranges: true
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-rates:
+ maxItems: 1
+
+ resets:
+ maxItems: 4
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 2
+
+# Required child node:
+
+patternProperties:
+ "^usb@[0-9a-f]+$":
+ $ref: snps,dwc3.yaml#
+
+required:
+ - compatible
+ - ranges
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-rates
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/hi3670-clock.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb3: hisi_dwc3 {
+ compatible = "hisilicon,hi3670-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&crg_ctrl HI3670_CLK_GATE_ABB_USB>,
+ <&crg_ctrl HI3670_HCLK_GATE_USB3OTG>,
+ <&crg_ctrl HI3670_CLK_GATE_USB3OTG_REF>,
+ <&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
+ clock-names = "clk_gate_abb_usb",
+ "hclk_gate_usb3otg",
+ "clk_gate_usb3otg_ref",
+ "aclk_gate_usb3dvfs";
+
+ assigned-clocks = <&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
+ assigned-clock-rates = <238000000>;
+ resets = <&crg_rst 0x90 6>,
+ <&crg_rst 0x90 7>,
+ <&usb31_misc_rst 0xA0 8>,
+ <&usb31_misc_rst 0xA0 9>;
+
+ dwc3: usb@ff100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff100000 0x0 0x100000>;
+
+ interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>,
+ <0 161 IRQ_TYPE_LEVEL_HIGH>;
+
+ phys = <&usb_phy>;
+ phy-names = "usb3-phy";
+ };
+ };
+ };
--
2.33.1
On Wed, Dec 15, 2021 at 09:54:29AM +0100, Mauro Carvalho Chehab wrote:
> Add documentation for the DWC3 USB3 controller found on Kirin970
> CPUs.
>
> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
> ---
>
> To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover.
> See [PATCH RESEND 0/7] at: https://lore.kernel.org/all/[email protected]/
>
> .../bindings/usb/hisilicon,hi3670-dwc3.yaml | 105 ++++++++++++++++++
> 1 file changed, 105 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml b/Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
> new file mode 100644
> index 000000000000..309a876ea615
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: GPL-2.0
dual license
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/hisilicon,hi3670-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: HiSilicon Kirin970 USB3 Controller
> +
> +maintainers:
> + - Mauro Carvalho Chehab <[email protected]>
> +
> +description:
> + Bindings for the USB3 DWC3 controller present on Kirin970.
> +
> +properties:
> + compatible:
> + const: hisilicon,hi3670-dwc3
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: clk_gate_abb_usb
> + - const: hclk_gate_usb3otg
> + - const: clk_gate_usb3otg_ref
> + - const: aclk_gate_usb3dvfs
Seems like abb, hclk, ref, and aclk would be sufficient. The names are
local to the device.
> +
> + ranges: true
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-rates:
> + maxItems: 1
> +
> + resets:
> + maxItems: 4
Need to define what they are.
> +
> + '#address-cells':
> + const: 2
> +
> + '#size-cells':
> + const: 2
> +
> +# Required child node:
> +
> +patternProperties:
> + "^usb@[0-9a-f]+$":
> + $ref: snps,dwc3.yaml#
> +
> +required:
> + - compatible
> + - ranges
> + - clocks
> + - clock-names
> + - assigned-clocks
> + - assigned-clock-rates
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/hi3670-clock.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + usb3: hisi_dwc3 {
dwc3 {
> + compatible = "hisilicon,hi3670-dwc3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&crg_ctrl HI3670_CLK_GATE_ABB_USB>,
> + <&crg_ctrl HI3670_HCLK_GATE_USB3OTG>,
> + <&crg_ctrl HI3670_CLK_GATE_USB3OTG_REF>,
> + <&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
> + clock-names = "clk_gate_abb_usb",
> + "hclk_gate_usb3otg",
> + "clk_gate_usb3otg_ref",
> + "aclk_gate_usb3dvfs";
> +
> + assigned-clocks = <&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
> + assigned-clock-rates = <238000000>;
> + resets = <&crg_rst 0x90 6>,
> + <&crg_rst 0x90 7>,
> + <&usb31_misc_rst 0xA0 8>,
> + <&usb31_misc_rst 0xA0 9>;
> +
> + dwc3: usb@ff100000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0xff100000 0x0 0x100000>;
> +
> + interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>,
> + <0 161 IRQ_TYPE_LEVEL_HIGH>;
> +
> + phys = <&usb_phy>;
> + phy-names = "usb3-phy";
> + };
> + };
> + };
> --
> 2.33.1
>
>