This is new features and bug fix patch set for DW_HDMI DRM bridge driver
that has verified by NXP i.MX8MPlus.
Three new feature added:
1. Add GPA interface for DW_HDMI Audio.
2. Add CEC PM functions to restore CEC status when device suspend/resume
3. New API for reset PHY Gen1.
Two bugs fixed:
1. Enable overflow workaround for all IP versions later than v1.30a.
2. Clear GCP_Auto bit for 24-bit color depth to pass CTS.
v1->v2:
1. Save CEC interrupt registers in struct dw_hdmi_cec
2. Restore CEC logical address register by cec->addresses.
3. Default enable overflow workaround for all versions later than v1.30a.
4. Add clear_gcp_auto flag to clear gcp_auto bit for all 24-bit color.
5. Remove i.MX8MPlus specific reference.
Sandor Yu (5):
drm: bridge: dw_hdmi: cec: Add cec suspend/resume function
drm: bridge: dw_hdmi: default enable workaround to clear the overflow
drm: bridge: dw_hdmi: Enable GCP only for Deep Color
drm: bridge: dw_hdmi: add reset function for PHY GEN1
drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver
drivers/gpu/drm/bridge/synopsys/Kconfig | 10 +
drivers/gpu/drm/bridge/synopsys/Makefile | 1 +
drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 37 ++++
.../drm/bridge/synopsys/dw-hdmi-gp-audio.c | 199 ++++++++++++++++++
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 177 ++++++++++++++--
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 13 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +-
include/drm/bridge/dw_hdmi.h | 9 +-
8 files changed, 424 insertions(+), 24 deletions(-)
create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
--
2.25.1
PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2,
and active low reset control for PHY GEN1.
Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset.
Add dw_hdmi_phy_gen1_reset function for PHY GEN1.
Signed-off-by: Sandor Yu <[email protected]>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +++++++++++---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +-
include/drm/bridge/dw_hdmi.h | 4 +++-
3 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 5a7ec066e37a..13270d96e5be 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1369,13 +1369,21 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
HDMI_PHY_CONF0_SELDIPIF_MASK);
}
-void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
+void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi)
+{
+ /* PHY reset. The reset signal is active low on Gen1 PHYs. */
+ hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
+ hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset);
+
+void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)
{
/* PHY reset. The reset signal is active high on Gen2 PHYs. */
hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
}
-EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
+EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset);
void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
{
@@ -1529,7 +1537,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
if (phy->has_svsret)
dw_hdmi_phy_enable_svsret(hdmi, 1);
- dw_hdmi_phy_reset(hdmi);
+ dw_hdmi_phy_gen2_reset(hdmi);
hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 5e2b0175df36..2860e6bff8b7 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -135,7 +135,7 @@ static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
dw_hdmi_phy_gen2_txpwron(hdmi, 0);
dw_hdmi_phy_gen2_pddq(hdmi, 1);
- dw_hdmi_phy_reset(hdmi);
+ dw_hdmi_phy_gen2_reset(hdmi);
dw_hdmi_phy_gen2_pddq(hdmi, 0);
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 2a1f85f9a8a3..70082f80a8c8 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -187,9 +187,11 @@ void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
unsigned char addr);
+void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi);
+
void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
-void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
+void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi);
enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
void *data);
--
2.25.1
On 08/04/2022 12:32, Sandor Yu wrote:
> PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2,
> and active low reset control for PHY GEN1.
>
> Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset.
> Add dw_hdmi_phy_gen1_reset function for PHY GEN1.
>
> Signed-off-by: Sandor Yu <[email protected]>
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +++++++++++---
> drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +-
> include/drm/bridge/dw_hdmi.h | 4 +++-
> 3 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 5a7ec066e37a..13270d96e5be 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -1369,13 +1369,21 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
> HDMI_PHY_CONF0_SELDIPIF_MASK);
> }
>
> -void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
> +void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi)
> +{
> + /* PHY reset. The reset signal is active low on Gen1 PHYs. */
> + hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
> + hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
> +}
> +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset);
> +
> +void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)
> {
> /* PHY reset. The reset signal is active high on Gen2 PHYs. */
> hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
> hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
> }
> -EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
> +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset);
>
> void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
> {
> @@ -1529,7 +1537,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
> if (phy->has_svsret)
> dw_hdmi_phy_enable_svsret(hdmi, 1);
>
> - dw_hdmi_phy_reset(hdmi);
> + dw_hdmi_phy_gen2_reset(hdmi);
>
> hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> index 5e2b0175df36..2860e6bff8b7 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> @@ -135,7 +135,7 @@ static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
> dw_hdmi_phy_gen2_txpwron(hdmi, 0);
> dw_hdmi_phy_gen2_pddq(hdmi, 1);
>
> - dw_hdmi_phy_reset(hdmi);
> + dw_hdmi_phy_gen2_reset(hdmi);
>
> dw_hdmi_phy_gen2_pddq(hdmi, 0);
>
> diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
> index 2a1f85f9a8a3..70082f80a8c8 100644
> --- a/include/drm/bridge/dw_hdmi.h
> +++ b/include/drm/bridge/dw_hdmi.h
> @@ -187,9 +187,11 @@ void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
> void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
> unsigned char addr);
>
> +void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi);
> +
> void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
> void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
> -void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
> +void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi);
>
> enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
> void *data);
Reviewed-by: Neil Armstrong <[email protected]>
If a sun4i drm maintainer can ack, then it would be all good to apply.
Neil
Dne petek, 08. april 2022 ob 14:22:52 CEST je Neil Armstrong napisal(a):
> On 08/04/2022 12:32, Sandor Yu wrote:
> > PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2,
> > and active low reset control for PHY GEN1.
> >
> > Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset.
> > Add dw_hdmi_phy_gen1_reset function for PHY GEN1.
> >
> > Signed-off-by: Sandor Yu <[email protected]>
> > ---
> >
> > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +++++++++++---
> > drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +-
> > include/drm/bridge/dw_hdmi.h | 4 +++-
> > 3 files changed, 15 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index
> > 5a7ec066e37a..13270d96e5be 100644
> > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > @@ -1369,13 +1369,21 @@ static void
> > dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)>
> > HDMI_PHY_CONF0_SELDIPIF_MASK);
> >
> > }
> >
> > -void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
> > +void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi)
> > +{
> > + /* PHY reset. The reset signal is active low on Gen1 PHYs. */
> > + hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
> > + hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
> > +}
> > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset);
> > +
> > +void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)
> >
> > {
> >
> > /* PHY reset. The reset signal is active high on Gen2 PHYs. */
> > hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
> > hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
> >
> > }
> >
> > -EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
> > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset);
> >
> > void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
> > {
> >
> > @@ -1529,7 +1537,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
> >
> > if (phy->has_svsret)
> >
> > dw_hdmi_phy_enable_svsret(hdmi, 1);
> >
> > - dw_hdmi_phy_reset(hdmi);
> > + dw_hdmi_phy_gen2_reset(hdmi);
> >
> > hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT,
HDMI_MC_HEACPHY_RST);
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> > b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index 5e2b0175df36..2860e6bff8b7
> > 100644
> > --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> > +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> > @@ -135,7 +135,7 @@ static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi
> > *hdmi,>
> > dw_hdmi_phy_gen2_txpwron(hdmi, 0);
> > dw_hdmi_phy_gen2_pddq(hdmi, 1);
> >
> > - dw_hdmi_phy_reset(hdmi);
> > + dw_hdmi_phy_gen2_reset(hdmi);
> >
> > dw_hdmi_phy_gen2_pddq(hdmi, 0);
> >
> > diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
> > index 2a1f85f9a8a3..70082f80a8c8 100644
> > --- a/include/drm/bridge/dw_hdmi.h
> > +++ b/include/drm/bridge/dw_hdmi.h
> > @@ -187,9 +187,11 @@ void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi,
> > u8 address);>
> > void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
> >
> > unsigned char addr);
> >
> > +void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi);
> > +
> >
> > void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
> > void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
> >
> > -void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
> > +void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi);
> >
> > enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
> >
> > void *data);
>
> Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Jernej Skrabec <[email protected]>
Best regards,
Jernej
>
> If a sun4i drm maintainer can ack, then it would be all good to apply.
>
> Neil