2024-01-30 09:57:56

by Shravan Ramani

[permalink] [raw]
Subject: [PATCH v1 0/2] Feature additions to mlxbf-pmc driver

This submission contains 2 patches:
Patch 1 adds support for 64-bit counters and tracking cycle count
Patch 2 adds support for the clock_measure performance block

Shravan Kumar Ramani (2):
platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and
cycle count
platform/mellanox: mlxbf-pmc: Add support for clock_measure
performance block

drivers/platform/mellanox/mlxbf-pmc.c | 178 +++++++++++++++++++++++++-
1 file changed, 174 insertions(+), 4 deletions(-)

--
2.30.1



2024-01-30 10:04:10

by Shravan Ramani

[permalink] [raw]
Subject: [PATCH v1 1/2] platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and cycle count

Add support for programming any counter to monitor the cycle count.
Since counting of cycles using 32-bit ocunters would result in frequent
wraparounds, add the ability to combine 2 adjacent 32-bit counters to
form 1 64-bit counter.
Both these features are supported by BlueField-3 PMC hardware, hence
the required bit-fields are exposed by the driver via sysfs to allow
the user to configure as needed.

Signed-off-by: Shravan Kumar Ramani <[email protected]>
Reviewed-by: David Thompson <[email protected]>
Reviewed-by: Vadim Pasternak <[email protected]>
---
drivers/platform/mellanox/mlxbf-pmc.c | 132 ++++++++++++++++++++++++++
1 file changed, 132 insertions(+)

diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c
index b1995ac268d7..906dfa96f783 100644
--- a/drivers/platform/mellanox/mlxbf-pmc.c
+++ b/drivers/platform/mellanox/mlxbf-pmc.c
@@ -88,6 +88,8 @@
#define MLXBF_PMC_CRSPACE_PERFMON_CTL(n) (n * MLXBF_PMC_CRSPACE_PERFMON_REG0_SZ)
#define MLXBF_PMC_CRSPACE_PERFMON_EN BIT(30)
#define MLXBF_PMC_CRSPACE_PERFMON_CLR BIT(28)
+#define MLXBF_PMC_CRSPACE_PERFMON_UOC GENMASK(15, 0)
+#define MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0x4)
#define MLXBF_PMC_CRSPACE_PERFMON_VAL0(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0xc)

/**
@@ -114,6 +116,8 @@ struct mlxbf_pmc_attribute {
* @attr_event: Attributes for "event" sysfs files
* @attr_event_list: Attributes for "event_list" sysfs files
* @attr_enable: Attributes for "enable" sysfs files
+ * @attr_use_odd_counter: Attributes for "use_odd_counter" sysfs files
+ * @attr_count_clock: Attributes for "count_clock" sysfs files
* @block_attr: All attributes needed for the block
* @block_attr_grp: Attribute group for the block
*/
@@ -126,6 +130,8 @@ struct mlxbf_pmc_block_info {
struct mlxbf_pmc_attribute *attr_event;
struct mlxbf_pmc_attribute attr_event_list;
struct mlxbf_pmc_attribute attr_enable;
+ struct mlxbf_pmc_attribute attr_use_odd_counter;
+ struct mlxbf_pmc_attribute attr_count_clock;
struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS];
struct attribute_group block_attr_grp;
};
@@ -1759,6 +1765,101 @@ static ssize_t mlxbf_pmc_enable_store(struct device *dev,
return count;
}

+/* Show function for "use_odd_counter" sysfs files - only for crspace */
+static ssize_t mlxbf_pmc_use_odd_counter_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mlxbf_pmc_attribute *attr_use_odd_counter = container_of(
+ attr, struct mlxbf_pmc_attribute, dev_attr);
+ int blk_num, value;
+ uint32_t reg;
+
+ blk_num = attr_use_odd_counter->nr;
+
+ if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
+ MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters),
+ &reg))
+ return -EINVAL;
+
+ value = FIELD_GET(MLXBF_PMC_CRSPACE_PERFMON_UOC, reg);
+
+ return sysfs_emit(buf, "%d\n", value);
+}
+
+/* Store function for "use_odd_counter" sysfs files - only for crspace */
+static ssize_t mlxbf_pmc_use_odd_counter_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct mlxbf_pmc_attribute *attr_use_odd_counter = container_of(
+ attr, struct mlxbf_pmc_attribute, dev_attr);
+ uint32_t uoc, reg;
+ int err, blk_num;
+
+ blk_num = attr_use_odd_counter->nr;
+
+ err = kstrtoint(buf, 0, &uoc);
+ if (err < 0)
+ return err;
+
+ err = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
+ MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters),
+ &reg);
+ if (err)
+ return -EINVAL;
+
+ reg &= ~MLXBF_PMC_CRSPACE_PERFMON_UOC;
+ reg |= FIELD_PREP(MLXBF_PMC_CRSPACE_PERFMON_UOC, uoc);
+
+ mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
+ MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters),
+ MLXBF_PMC_WRITE_REG_32, reg);
+
+ return count;
+}
+
+/* Show function for "count_clock" sysfs files - only for crspace */
+static ssize_t mlxbf_pmc_count_clock_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mlxbf_pmc_attribute *attr_count_clock = container_of(
+ attr, struct mlxbf_pmc_attribute, dev_attr);
+ uint32_t reg;
+ int blk_num;
+
+ blk_num = attr_count_clock->nr;
+
+ if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
+ MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters),
+ &reg))
+ return -EINVAL;
+
+ return sysfs_emit(buf, "%d\n", reg);
+}
+
+/* Store function for "count_clock" sysfs files - only for crspace */
+static ssize_t mlxbf_pmc_count_clock_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct mlxbf_pmc_attribute *attr_count_clock = container_of(
+ attr, struct mlxbf_pmc_attribute, dev_attr);
+ int err, blk_num;
+ uint32_t reg;
+
+ blk_num = attr_count_clock->nr;
+
+ err = kstrtoint(buf, 0, &reg);
+ if (err < 0)
+ return err;
+
+ mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
+ MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters),
+ MLXBF_PMC_WRITE_REG_32, reg);
+
+ return count;
+}
+
/* Populate attributes for blocks with counters to monitor performance */
static int mlxbf_pmc_init_perftype_counter(struct device *dev, int blk_num)
{
@@ -1792,6 +1893,37 @@ static int mlxbf_pmc_init_perftype_counter(struct device *dev, int blk_num)
attr = NULL;
}

+ if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) {
+ /*
+ * Couple adjacent odd and even 32-bit counters to form 64-bit counters
+ * using "use_odd_counter" sysfs which has one bit per even counter.
+ */
+ attr = &pmc->block[blk_num].attr_use_odd_counter;
+ attr->dev_attr.attr.mode = 0644;
+ attr->dev_attr.show = mlxbf_pmc_use_odd_counter_show;
+ attr->dev_attr.store = mlxbf_pmc_use_odd_counter_store;
+ attr->nr = blk_num;
+ attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
+ "use_odd_counter");
+ if (!attr->dev_attr.attr.name)
+ return -ENOMEM;
+ pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
+ attr = NULL;
+
+ /* Program crspace counters to count clock cycles using "count_clock" sysfs */
+ attr = &pmc->block[blk_num].attr_count_clock;
+ attr->dev_attr.attr.mode = 0644;
+ attr->dev_attr.show = mlxbf_pmc_count_clock_show;
+ attr->dev_attr.store = mlxbf_pmc_count_clock_store;
+ attr->nr = blk_num;
+ attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
+ "count_clock");
+ if (!attr->dev_attr.attr.name)
+ return -ENOMEM;
+ pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
+ attr = NULL;
+ }
+
pmc->block[blk_num].attr_counter = devm_kcalloc(
dev, pmc->block[blk_num].counters,
sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);
--
2.30.1


2024-01-30 10:04:16

by Shravan Ramani

[permalink] [raw]
Subject: [PATCH v1 2/2] platform/mellanox: mlxbf-pmc: Add support for clock_measure performance block

The HW clock_measure counter info is passed to the driver from ACPI.
Create a new sub-directory for clock_measure events and provide
read access to the user. Writes are blocked since the fields are RO.

Signed-off-by: Shravan Kumar Ramani <[email protected]>
Reviewed-by: David Thompson <[email protected]>
Reviewed-by: Vadim Pasternak <[email protected]>
---
drivers/platform/mellanox/mlxbf-pmc.c | 46 ++++++++++++++++++++++++---
1 file changed, 42 insertions(+), 4 deletions(-)

diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c
index 906dfa96f783..e1c0e2f04abb 100644
--- a/drivers/platform/mellanox/mlxbf-pmc.c
+++ b/drivers/platform/mellanox/mlxbf-pmc.c
@@ -865,6 +865,37 @@ static const struct mlxbf_pmc_events mlxbf_pmc_llt_miss_events[] = {
{75, "HISTOGRAM_HISTOGRAM_BIN9"},
};

+static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] = {
+ { 0x0, "FMON_CLK_LAST_COUNT_PLL_D1_INST0" },
+ { 0x4, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST0" },
+ { 0x8, "FMON_CLK_LAST_COUNT_PLL_D1_INST1" },
+ { 0xc, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST1" },
+ { 0x10, "FMON_CLK_LAST_COUNT_PLL_G1" },
+ { 0x14, "REFERENCE_WINDOW_WIDTH_PLL_G1" },
+ { 0x18, "FMON_CLK_LAST_COUNT_PLL_W1" },
+ { 0x1c, "REFERENCE_WINDOW_WIDTH_PLL_W1" },
+ { 0x20, "FMON_CLK_LAST_COUNT_PLL_T1" },
+ { 0x24, "REFERENCE_WINDOW_WIDTH_PLL_T1" },
+ { 0x28, "FMON_CLK_LAST_COUNT_PLL_A0" },
+ { 0x2c, "REFERENCE_WINDOW_WIDTH_PLL_A0" },
+ { 0x30, "FMON_CLK_LAST_COUNT_PLL_C0" },
+ { 0x34, "REFERENCE_WINDOW_WIDTH_PLL_C0" },
+ { 0x38, "FMON_CLK_LAST_COUNT_PLL_N1" },
+ { 0x3c, "REFERENCE_WINDOW_WIDTH_PLL_N1" },
+ { 0x40, "FMON_CLK_LAST_COUNT_PLL_I1" },
+ { 0x44, "REFERENCE_WINDOW_WIDTH_PLL_I1" },
+ { 0x48, "FMON_CLK_LAST_COUNT_PLL_R1" },
+ { 0x4c, "REFERENCE_WINDOW_WIDTH_PLL_R1" },
+ { 0x50, "FMON_CLK_LAST_COUNT_PLL_P1" },
+ { 0x54, "REFERENCE_WINDOW_WIDTH_PLL_P1" },
+ { 0x58, "FMON_CLK_LAST_COUNT_REF_100_INST0" },
+ { 0x5c, "REFERENCE_WINDOW_WIDTH_REF_100_INST0" },
+ { 0x60, "FMON_CLK_LAST_COUNT_REF_100_INST1" },
+ { 0x64, "REFERENCE_WINDOW_WIDTH_REF_100_INST1" },
+ { 0x68, "FMON_CLK_LAST_COUNT_REF_156" },
+ { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" },
+};
+
static struct mlxbf_pmc_context *pmc;

/* UUID used to probe ATF service. */
@@ -1041,6 +1072,9 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk,
} else if (strstr(blk, "llt")) {
events = mlxbf_pmc_llt_events;
*size = ARRAY_SIZE(mlxbf_pmc_llt_events);
+ } else if (strstr(blk, "clock_measure")) {
+ events = mlxbf_pmc_clock_events;
+ *size = ARRAY_SIZE(mlxbf_pmc_clock_events);
} else {
events = NULL;
*size = 0;
@@ -1477,14 +1511,15 @@ static int mlxbf_pmc_read_event(int blk_num, uint32_t cnt_num, bool is_l3,
/* Method to read a register */
static int mlxbf_pmc_read_reg(int blk_num, uint32_t offset, uint64_t *result)
{
- uint32_t ecc_out;
+ uint32_t reg;

- if (strstr(pmc->block_name[blk_num], "ecc")) {
+ if ((strstr(pmc->block_name[blk_num], "ecc")) ||
+ (strstr(pmc->block_name[blk_num], "clock_measure"))) {
if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset,
- &ecc_out))
+ &reg))
return -EFAULT;

- *result = ecc_out;
+ *result = reg;
return 0;
}

@@ -1498,6 +1533,9 @@ static int mlxbf_pmc_read_reg(int blk_num, uint32_t offset, uint64_t *result)
/* Method to write to a register */
static int mlxbf_pmc_write_reg(int blk_num, uint32_t offset, uint64_t data)
{
+ if (strstr(pmc->block_name[blk_num], "clock_measure"))
+ return -EINVAL;
+
if (strstr(pmc->block_name[blk_num], "ecc")) {
return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset,
MLXBF_PMC_WRITE_REG_32, data);
--
2.30.1


2024-01-31 10:19:58

by Ilpo Järvinen

[permalink] [raw]
Subject: Re: [PATCH v1 1/2] platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and cycle count

On Tue, 30 Jan 2024, Shravan Kumar Ramani wrote:

> Add support for programming any counter to monitor the cycle count.
> Since counting of cycles using 32-bit ocunters would result in frequent
> wraparounds, add the ability to combine 2 adjacent 32-bit counters to
> form 1 64-bit counter.
> Both these features are supported by BlueField-3 PMC hardware, hence
> the required bit-fields are exposed by the driver via sysfs to allow
> the user to configure as needed.
>
> Signed-off-by: Shravan Kumar Ramani <[email protected]>
> Reviewed-by: David Thompson <[email protected]>
> Reviewed-by: Vadim Pasternak <[email protected]>
> ---
> drivers/platform/mellanox/mlxbf-pmc.c | 132 ++++++++++++++++++++++++++
> 1 file changed, 132 insertions(+)
>
> diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c
> index b1995ac268d7..906dfa96f783 100644
> --- a/drivers/platform/mellanox/mlxbf-pmc.c
> +++ b/drivers/platform/mellanox/mlxbf-pmc.c
> @@ -88,6 +88,8 @@
> #define MLXBF_PMC_CRSPACE_PERFMON_CTL(n) (n * MLXBF_PMC_CRSPACE_PERFMON_REG0_SZ)
> #define MLXBF_PMC_CRSPACE_PERFMON_EN BIT(30)
> #define MLXBF_PMC_CRSPACE_PERFMON_CLR BIT(28)
> +#define MLXBF_PMC_CRSPACE_PERFMON_UOC GENMASK(15, 0)
> +#define MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0x4)
> #define MLXBF_PMC_CRSPACE_PERFMON_VAL0(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0xc)
>
> /**
> @@ -114,6 +116,8 @@ struct mlxbf_pmc_attribute {
> * @attr_event: Attributes for "event" sysfs files
> * @attr_event_list: Attributes for "event_list" sysfs files
> * @attr_enable: Attributes for "enable" sysfs files
> + * @attr_use_odd_counter: Attributes for "use_odd_counter" sysfs files
> + * @attr_count_clock: Attributes for "count_clock" sysfs files
> * @block_attr: All attributes needed for the block
> * @block_attr_grp: Attribute group for the block
> */
> @@ -126,6 +130,8 @@ struct mlxbf_pmc_block_info {
> struct mlxbf_pmc_attribute *attr_event;
> struct mlxbf_pmc_attribute attr_event_list;
> struct mlxbf_pmc_attribute attr_enable;
> + struct mlxbf_pmc_attribute attr_use_odd_counter;
> + struct mlxbf_pmc_attribute attr_count_clock;
> struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS];
> struct attribute_group block_attr_grp;
> };
> @@ -1759,6 +1765,101 @@ static ssize_t mlxbf_pmc_enable_store(struct device *dev,
> return count;
> }
>
> +/* Show function for "use_odd_counter" sysfs files - only for crspace */
> +static ssize_t mlxbf_pmc_use_odd_counter_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct mlxbf_pmc_attribute *attr_use_odd_counter = container_of(
> + attr, struct mlxbf_pmc_attribute, dev_attr);
> + int blk_num, value;
> + uint32_t reg;
> +
> + blk_num = attr_use_odd_counter->nr;
> +
> + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
> + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters),
> + &reg))
> + return -EINVAL;
> +
> + value = FIELD_GET(MLXBF_PMC_CRSPACE_PERFMON_UOC, reg);

Is this a signed field? If not, don't use int for value and change the %d
-> %u too.

> +
> + return sysfs_emit(buf, "%d\n", value);
> +}
> +
> +/* Store function for "use_odd_counter" sysfs files - only for crspace */
> +static ssize_t mlxbf_pmc_use_odd_counter_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct mlxbf_pmc_attribute *attr_use_odd_counter = container_of(
> + attr, struct mlxbf_pmc_attribute, dev_attr);
> + uint32_t uoc, reg;

uint32_t is not to be used as in-kernel type, use u32 in kernel.

> + int err, blk_num;
> +
> + blk_num = attr_use_odd_counter->nr;
> +
> + err = kstrtoint(buf, 0, &uoc);

Hmm, uoc is unsigned but you use signed variant, kstrtouint() also
available for you so better to use that.

> + if (err < 0)
> + return err;
> +
> + err = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
> + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters),
> + &reg);
> + if (err)
> + return -EINVAL;
> +
> + reg &= ~MLXBF_PMC_CRSPACE_PERFMON_UOC;
> + reg |= FIELD_PREP(MLXBF_PMC_CRSPACE_PERFMON_UOC, uoc);
> +
> + mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
> + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters),
> + MLXBF_PMC_WRITE_REG_32, reg);
> +
> + return count;
> +}
> +
> +/* Show function for "count_clock" sysfs files - only for crspace */
> +static ssize_t mlxbf_pmc_count_clock_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct mlxbf_pmc_attribute *attr_count_clock = container_of(
> + attr, struct mlxbf_pmc_attribute, dev_attr);
> + uint32_t reg;

u32

> + int blk_num;
> +
> + blk_num = attr_count_clock->nr;
> +
> + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
> + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters),
> + &reg))
> + return -EINVAL;
> +
> + return sysfs_emit(buf, "%d\n", reg);

Use %u when printing unsigned values.

> +}
> +
> +/* Store function for "count_clock" sysfs files - only for crspace */
> +static ssize_t mlxbf_pmc_count_clock_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct mlxbf_pmc_attribute *attr_count_clock = container_of(
> + attr, struct mlxbf_pmc_attribute, dev_attr);
> + int err, blk_num;
> + uint32_t reg;

u32

> +
> + blk_num = attr_count_clock->nr;
> +
> + err = kstrtoint(buf, 0, &reg);

kstrtouint()

> + if (err < 0)
> + return err;
> +
> + mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
> + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters),
> + MLXBF_PMC_WRITE_REG_32, reg);
> +
> + return count;
> +}
> +
> /* Populate attributes for blocks with counters to monitor performance */
> static int mlxbf_pmc_init_perftype_counter(struct device *dev, int blk_num)
> {
> @@ -1792,6 +1893,37 @@ static int mlxbf_pmc_init_perftype_counter(struct device *dev, int blk_num)
> attr = NULL;
> }
>
> + if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) {
> + /*
> + * Couple adjacent odd and even 32-bit counters to form 64-bit counters
> + * using "use_odd_counter" sysfs which has one bit per even counter.
> + */
> + attr = &pmc->block[blk_num].attr_use_odd_counter;
> + attr->dev_attr.attr.mode = 0644;
> + attr->dev_attr.show = mlxbf_pmc_use_odd_counter_show;
> + attr->dev_attr.store = mlxbf_pmc_use_odd_counter_store;
> + attr->nr = blk_num;
> + attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
> + "use_odd_counter");

Why you need alloc for a constant string?

> + if (!attr->dev_attr.attr.name)
> + return -ENOMEM;
> + pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
> + attr = NULL;
> +
> + /* Program crspace counters to count clock cycles using "count_clock" sysfs */
> + attr = &pmc->block[blk_num].attr_count_clock;
> + attr->dev_attr.attr.mode = 0644;
> + attr->dev_attr.show = mlxbf_pmc_count_clock_show;
> + attr->dev_attr.store = mlxbf_pmc_count_clock_store;
> + attr->nr = blk_num;
> + attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
> + "count_clock");

Why alloc?

> + if (!attr->dev_attr.attr.name)
> + return -ENOMEM;
> + pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
> + attr = NULL;
> + }
> +
> pmc->block[blk_num].attr_counter = devm_kcalloc(
> dev, pmc->block[blk_num].counters,
> sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);
>

--
i.


2024-01-31 12:26:09

by Ilpo Järvinen

[permalink] [raw]
Subject: Re: [PATCH v1 2/2] platform/mellanox: mlxbf-pmc: Add support for clock_measure performance block

On Tue, 30 Jan 2024, Shravan Kumar Ramani wrote:

> The HW clock_measure counter info is passed to the driver from ACPI.
> Create a new sub-directory for clock_measure events and provide
> read access to the user. Writes are blocked since the fields are RO.
>
> Signed-off-by: Shravan Kumar Ramani <[email protected]>
> Reviewed-by: David Thompson <[email protected]>
> Reviewed-by: Vadim Pasternak <[email protected]>
> ---
> drivers/platform/mellanox/mlxbf-pmc.c | 46 ++++++++++++++++++++++++---
> 1 file changed, 42 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c
> index 906dfa96f783..e1c0e2f04abb 100644
> --- a/drivers/platform/mellanox/mlxbf-pmc.c
> +++ b/drivers/platform/mellanox/mlxbf-pmc.c
> @@ -865,6 +865,37 @@ static const struct mlxbf_pmc_events mlxbf_pmc_llt_miss_events[] = {
> {75, "HISTOGRAM_HISTOGRAM_BIN9"},
> };
>
> +static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] = {
> + { 0x0, "FMON_CLK_LAST_COUNT_PLL_D1_INST0" },
> + { 0x4, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST0" },
> + { 0x8, "FMON_CLK_LAST_COUNT_PLL_D1_INST1" },
> + { 0xc, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST1" },
> + { 0x10, "FMON_CLK_LAST_COUNT_PLL_G1" },
> + { 0x14, "REFERENCE_WINDOW_WIDTH_PLL_G1" },
> + { 0x18, "FMON_CLK_LAST_COUNT_PLL_W1" },
> + { 0x1c, "REFERENCE_WINDOW_WIDTH_PLL_W1" },
> + { 0x20, "FMON_CLK_LAST_COUNT_PLL_T1" },
> + { 0x24, "REFERENCE_WINDOW_WIDTH_PLL_T1" },
> + { 0x28, "FMON_CLK_LAST_COUNT_PLL_A0" },
> + { 0x2c, "REFERENCE_WINDOW_WIDTH_PLL_A0" },
> + { 0x30, "FMON_CLK_LAST_COUNT_PLL_C0" },
> + { 0x34, "REFERENCE_WINDOW_WIDTH_PLL_C0" },
> + { 0x38, "FMON_CLK_LAST_COUNT_PLL_N1" },
> + { 0x3c, "REFERENCE_WINDOW_WIDTH_PLL_N1" },
> + { 0x40, "FMON_CLK_LAST_COUNT_PLL_I1" },
> + { 0x44, "REFERENCE_WINDOW_WIDTH_PLL_I1" },
> + { 0x48, "FMON_CLK_LAST_COUNT_PLL_R1" },
> + { 0x4c, "REFERENCE_WINDOW_WIDTH_PLL_R1" },
> + { 0x50, "FMON_CLK_LAST_COUNT_PLL_P1" },
> + { 0x54, "REFERENCE_WINDOW_WIDTH_PLL_P1" },
> + { 0x58, "FMON_CLK_LAST_COUNT_REF_100_INST0" },
> + { 0x5c, "REFERENCE_WINDOW_WIDTH_REF_100_INST0" },
> + { 0x60, "FMON_CLK_LAST_COUNT_REF_100_INST1" },
> + { 0x64, "REFERENCE_WINDOW_WIDTH_REF_100_INST1" },
> + { 0x68, "FMON_CLK_LAST_COUNT_REF_156" },
> + { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" },
> +};
> +
> static struct mlxbf_pmc_context *pmc;
>
> /* UUID used to probe ATF service. */
> @@ -1041,6 +1072,9 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk,
> } else if (strstr(blk, "llt")) {
> events = mlxbf_pmc_llt_events;
> *size = ARRAY_SIZE(mlxbf_pmc_llt_events);
> + } else if (strstr(blk, "clock_measure")) {
> + events = mlxbf_pmc_clock_events;
> + *size = ARRAY_SIZE(mlxbf_pmc_clock_events);
> } else {
> events = NULL;
> *size = 0;
> @@ -1477,14 +1511,15 @@ static int mlxbf_pmc_read_event(int blk_num, uint32_t cnt_num, bool is_l3,
> /* Method to read a register */
> static int mlxbf_pmc_read_reg(int blk_num, uint32_t offset, uint64_t *result)
> {
> - uint32_t ecc_out;
> + uint32_t reg;

While at it, change to u32.

--
i.