This series originally added support also for ipq807x.
This part was split and is now merged.
This patch was originally dependent of [1] but was later reverted
due to compilation problem. [1] had some changes that weren't related
to the compilation problem and were just a fixup.
This series include these 2 required patches from [1] that are
just cleanup and won't cause any problem.
These 2 patch were already checked and accepted by maintainers.
This small series adds support for ipq806x qcom-cpufreq-nvmem driver.
Special function are required to make use of the opp-supported-hw
binding by hardcoding custom bits based on the qcom SoC ID.
[1] https://lore.kernel.org/linux-pm/20231010063235.rj2ehxugtjr5x2xr@vireshk-i7/T/#t
Christian Marangi (2):
cpufreq: qcom-nvmem: add support for IPQ8064
ARM: dts: qcom: ipq8064: Add CPU OPP table
Dmitry Baryshkov (2):
cpufreq: qcom-nvmem: drop pvs_ver for format a fuses
cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu
arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi | 30 ++++++++++
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 67 +++++++++++++++++++++
arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi | 65 ++++++++++++++++++++
drivers/cpufreq/qcom-cpufreq-nvmem.c | 75 ++++++++++++++++++++++--
4 files changed, 232 insertions(+), 5 deletions(-)
--
2.40.1
From: Dmitry Baryshkov <[email protected]>
the qcom-cpufreq-nvmem driver attempts to support both Qualcomm Kryo
(newer 64-bit ARMv8 cores) and Krait (older 32-bit ARMv7 cores). It
makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node
for the Krait cores. Add support for 'operating-points-v2-krait-cpu'
compatibility string.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Christian Marangi <[email protected]>
---
Changes v7:
* Add this patch from reverted other series
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index c399b5014b49..57842d60d6ec 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -369,7 +369,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
if (!np)
return -ENOENT;
- ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
+ ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
+ of_device_is_compatible(np, "operating-points-v2-krait-cpu");
if (!ret) {
of_node_put(np);
return -ENOENT;
--
2.40.1
From: Dmitry Baryshkov <[email protected]>
The fuses used on msm8960 / apq8064 / ipq806x families of devices do not
have the pvs version. Drop this argument from parsing function.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Christian Marangi <[email protected]>
---
Changes v7:
* Add this patch from reverted other series
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 7f9ff86cfc5f..c399b5014b49 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -78,7 +78,7 @@ static int qcom_cpufreq_simple_get_version(struct device *cpu_dev,
}
static void get_krait_bin_format_a(struct device *cpu_dev,
- int *speed, int *pvs, int *pvs_ver,
+ int *speed, int *pvs,
u8 *buf)
{
u32 pte_efuse;
@@ -209,8 +209,7 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
switch (len) {
case 4:
- get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
- speedbin);
+ get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
break;
case 8:
get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
--
2.40.1
Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC.
Use opp-supported-hw binding to correctly enable and disable the
frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to
1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports
1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled.
Signed-off-by: Christian Marangi <[email protected]>
---
Changes v6:
* Use new krait compatible
Changes v4:
* Readd OPP patch for IPQ8064
---
arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi | 30 +++++++++++
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 67 ++++++++++++++++++++++++
arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi | 65 +++++++++++++++++++++++
3 files changed, 162 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi
index 5d3ebd3e2e51..72d9782c3d6f 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi
@@ -6,3 +6,33 @@ / {
model = "Qualcomm Technologies, Inc. IPQ8062";
compatible = "qcom,ipq8062", "qcom,ipq8064";
};
+
+&opp_table_cpu {
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3 = <800000 760000 840000>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3 = <850000 807500 892500>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3 = <900000 855000 945000>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3 = <950000 902500 997500>;
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 6198f42f6a9c..54699472f187 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -30,6 +30,7 @@ cpu0: cpu@0 {
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
+ operating-points-v2 = <&opp_table_cpu>;
};
cpu1: cpu@1 {
@@ -40,6 +41,7 @@ cpu1: cpu@1 {
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
+ operating-points-v2 = <&opp_table_cpu>;
};
L2: l2-cache {
@@ -49,6 +51,71 @@ L2: l2-cache {
};
};
+ opp_table_cpu: opp-table-cpu {
+ compatible = "operating-points-v2-krait-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3 = <800000 760000 840000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3 = <850000 807500 892500>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3 = <900000 855000 945000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3 = <950000 902500 997500>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt-speed0-pvs0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs1 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs2 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs3 = <1000000 950000 1050000>;
+ opp-supported-hw = <0x2>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt-speed0-pvs0 = <1250000 1187500 1312500>;
+ opp-microvolt-speed0-pvs1 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs2 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x6>;
+ clock-latency-ns = <100000>;
+ };
+ };
+
thermal-zones {
sensor0-thermal {
polling-delay-passive = <0>;
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
index ea49f6cc416d..d9ead31b897b 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
@@ -6,3 +6,68 @@ / {
model = "Qualcomm Technologies, Inc. IPQ8065";
compatible = "qcom,ipq8065", "qcom,ipq8064";
};
+
+&opp_table_cpu {
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs1 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs2 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs4 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs5 = <825000 783750 866250>;
+ opp-microvolt-speed0-pvs6 = <775000 736250 813750>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs3 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs4 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs5 = <850000 807500 892500>;
+ opp-microvolt-speed0-pvs6 = <800000 760000 840000>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs3 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs4 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs5 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs6 = <850000 807500 892500>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs3 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs4 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs5 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs6 = <900000 855000 945000>;
+ };
+
+ opp-1400000000 {
+ opp-microvolt-speed4-pvs0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed4-pvs1 = <1150000 1092500 1207500>;
+ opp-microvolt-speed4-pvs2 = <1125000 1068750 1181250>;
+ opp-microvolt-speed4-pvs3 = <1100000 1045000 1155000>;
+ opp-microvolt-speed4-pvs4 = <1075000 1021250 1128750>;
+ opp-microvolt-speed4-pvs5 = <1025000 973750 1076250>;
+ opp-microvolt-speed4-pvs6 = <975000 926250 1023750>;
+ };
+
+ opp-1725000000 {
+ opp-hz = /bits/ 64 <1725000000>;
+ opp-microvolt-speed0-pvs0 = <1262500 1199375 1325625>;
+ opp-microvolt-speed0-pvs1 = <1225000 1163750 1286250>;
+ opp-microvolt-speed0-pvs2 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs3 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs4 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs5 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs6 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x4>;
+ clock-latency-ns = <100000>;
+ };
+};
--
2.40.1
IPQ8064 comes in 3 families:
* IPQ8062 up to 1.0GHz
* IPQ8064/IPQ8066/IPQ8068 up to 1.4GHz
* IPQ8065/IPQ8069 up to 1.7Ghz
So, in order to be able to support one OPP table, add support for
IPQ8064 family based of SMEM SoC ID-s and correctly set the version so
opp-supported-hw can be correctly used.
Bit are set with the following logic:
* IPQ8062 BIT 0
* IPQ8064/IPQ8066/IPQ8068 BIT 1
* IPQ8065/IPQ8069 BIT 2
speed is never fused, only pvs values are fused.
IPQ806x SoC doesn't have pvs_version so we drop and we use the new
pattern:
opp-microvolt-speed0-pvs<PSV_VALUE>
Example:
- for ipq8062 psv2
opp-microvolt-speed0-pvs2 = < 925000 878750 971250>
Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs")
Signed-off-by: Christian Marangi <[email protected]>
---
Changes v7:
* Rebase on top of vireshk cpufreq/arm/linux-next
Changes v6:
* Rebase on top of dependant series
* Fix leaking speedbin nvmem
* Fix format_a function to follow new functions
* Improve snprintf as suggested from Konrad
Changes v5:
* Fix leaking speedbin nvmem
Changes in v3:
* Use enum for SoC version
* Dont evaluate speed as its not fused, only pvs
Changes in v2:
* Include IPQ8064 support
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 67 +++++++++++++++++++++++++++-
1 file changed, 66 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 57842d60d6ec..59b045471f91 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -35,6 +35,12 @@ enum ipq8074_versions {
IPQ8074_ACORN_VERSION,
};
+enum ipq806x_versions {
+ IPQ8062_VERSION = 0,
+ IPQ8064_VERSION,
+ IPQ8065_VERSION,
+};
+
#define IPQ6000_VERSION BIT(2)
struct qcom_cpufreq_drv;
@@ -231,6 +237,61 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
return ret;
}
+static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
+ struct qcom_cpufreq_drv *drv)
+{
+ int speed = 0, pvs = 0;
+ int msm_id, ret = 0;
+ u8 *speedbin;
+ size_t len;
+
+ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+ if (IS_ERR(speedbin))
+ return PTR_ERR(speedbin);
+
+ if (len != 4) {
+ dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
+ ret = -ENODEV;
+ goto exit;
+ }
+
+ get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
+
+ ret = qcom_smem_get_soc_id(&msm_id);
+ if (ret)
+ goto exit;
+
+ switch (msm_id) {
+ case QCOM_ID_IPQ8062:
+ drv->versions = BIT(IPQ8062_VERSION);
+ break;
+ case QCOM_ID_IPQ8064:
+ case QCOM_ID_IPQ8066:
+ case QCOM_ID_IPQ8068:
+ drv->versions = BIT(IPQ8064_VERSION);
+ break;
+ case QCOM_ID_IPQ8065:
+ case QCOM_ID_IPQ8069:
+ drv->versions = BIT(IPQ8065_VERSION);
+ break;
+ default:
+ dev_err(cpu_dev,
+ "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n",
+ msm_id);
+ drv->versions = BIT(IPQ8062_VERSION);
+ break;
+ }
+
+ /* IPQ8064 speed is never fused. Only pvs values are fused. */
+ snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs);
+
+exit:
+ kfree(speedbin);
+ return ret;
+}
+
static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
struct nvmem_cell *speedbin_nvmem,
char **pvs_name,
@@ -345,6 +406,10 @@ static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
.get_version = qcom_cpufreq_ipq6018_name_version,
};
+static const struct qcom_cpufreq_match_data match_data_ipq8064 = {
+ .get_version = qcom_cpufreq_ipq8064_name_version,
+};
+
static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
.get_version = qcom_cpufreq_ipq8074_name_version,
};
@@ -477,7 +542,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
- { .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
--
2.40.1
On 19-10-23, 12:50, Christian Marangi wrote:
> This series originally added support also for ipq807x.
> This part was split and is now merged.
>
> This patch was originally dependent of [1] but was later reverted
> due to compilation problem. [1] had some changes that weren't related
> to the compilation problem and were just a fixup.
>
> This series include these 2 required patches from [1] that are
> just cleanup and won't cause any problem.
> These 2 patch were already checked and accepted by maintainers.
>
> This small series adds support for ipq806x qcom-cpufreq-nvmem driver.
> Special function are required to make use of the opp-supported-hw
> binding by hardcoding custom bits based on the qcom SoC ID.
>
> [1] https://lore.kernel.org/linux-pm/20231010063235.rj2ehxugtjr5x2xr@vireshk-i7/T/#t
Applied [1-3]/4. Thanks.
--
viresh
On 10/19/23 12:50, Christian Marangi wrote:
> Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC.
> Use opp-supported-hw binding to correctly enable and disable the
> frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to
> 1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports
> 1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled.
>
> Signed-off-by: Christian Marangi <[email protected]>
> ---
I didn't actually check the values against downstream, maybe we
can prettyplease ask Dmitry as he's done that before with msm8960-class
SoCs..
[...]
> + opp_table_cpu: opp-table-cpu {
> + compatible = "operating-points-v2-krait-cpu";
> + nvmem-cells = <&speedbin_efuse>;
Shouldn't this be opp-shared?
Konrad