This patch is used to detect vector support status of CPU and use
riscv_vsize to save the size of all the vector registers. It assumes
all harts has the same capabilities in SMP system.
[[email protected]: add has_vector checking]
Co-developed-by: Guo Ren <[email protected]>
Signed-off-by: Guo Ren <[email protected]>
Co-developed-by: Vincent Chen <[email protected]>
Signed-off-by: Vincent Chen <[email protected]>
Signed-off-by: Greentime Hu <[email protected]>
---
arch/riscv/include/asm/vector.h | 14 +++++
arch/riscv/kernel/cpufeature.c | 17 ++++++
arch/riscv/kernel/riscv_ksyms.c | 6 +++
arch/riscv/kernel/vector.S | 93 +++++++++++++++++++++++++++++++++
4 files changed, 130 insertions(+)
create mode 100644 arch/riscv/include/asm/vector.h
create mode 100644 arch/riscv/kernel/vector.S
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
new file mode 100644
index 000000000000..16304b0c6a6f
--- /dev/null
+++ b/arch/riscv/include/asm/vector.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2020 SiFive
+ */
+
+#ifndef __ASM_RISCV_VECTOR_H
+#define __ASM_RISCV_VECTOR_H
+
+#include <linux/types.h>
+
+void rvv_enable(void);
+void rvv_disable(void);
+
+#endif /* ! __ASM_RISCV_VECTOR_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 92a8fd6bd3ed..f2dec6cb60ed 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -24,6 +24,11 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
#ifdef CONFIG_FPU
__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
#endif
+#ifdef CONFIG_VECTOR
+#include <asm/vector.h>
+__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector);
+unsigned long riscv_vsize __read_mostly;
+#endif
/**
* riscv_isa_extension_base() - Get base extension word
@@ -76,7 +81,9 @@ void __init riscv_fill_hwcap(void)
isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+#ifdef CONFIG_VECTOR
isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
+#endif
elf_hwcap = 0;
@@ -237,4 +244,14 @@ void __init riscv_fill_hwcap(void)
if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
static_branch_enable(&cpu_hwcap_fpu);
#endif
+
+#ifdef CONFIG_VECTOR
+ if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+ static_branch_enable(&cpu_hwcap_vector);
+ /* There are 32 vector registers with vlenb length. */
+ rvv_enable();
+ riscv_vsize = csr_read(CSR_VLENB) * 32;
+ rvv_disable();
+ }
+#endif
}
diff --git a/arch/riscv/kernel/riscv_ksyms.c b/arch/riscv/kernel/riscv_ksyms.c
index 5ab1c7e1a6ed..3489d2a20ca3 100644
--- a/arch/riscv/kernel/riscv_ksyms.c
+++ b/arch/riscv/kernel/riscv_ksyms.c
@@ -15,3 +15,9 @@ EXPORT_SYMBOL(memmove);
EXPORT_SYMBOL(__memset);
EXPORT_SYMBOL(__memcpy);
EXPORT_SYMBOL(__memmove);
+
+#ifdef CONFIG_VECTOR
+#include <asm/vector.h>
+EXPORT_SYMBOL(rvv_enable);
+EXPORT_SYMBOL(rvv_disable);
+#endif
diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S
new file mode 100644
index 000000000000..9f7dc70c4443
--- /dev/null
+++ b/arch/riscv/kernel/vector.S
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 Regents of the University of California
+ * Copyright (C) 2017 SiFive
+ * Copyright (C) 2019 Alibaba Group Holding Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/asm.h>
+#include <asm/csr.h>
+#include <asm/asm-offsets.h>
+
+#define vstatep a0
+#define datap a1
+#define x_vstart t0
+#define x_vtype t1
+#define x_vl t2
+#define x_vcsr t3
+#define incr t4
+#define status t5
+
+ENTRY(__vstate_save)
+ li status, SR_VS
+ csrs CSR_STATUS, status
+
+ csrr x_vstart, CSR_VSTART
+ csrr x_vtype, CSR_VTYPE
+ csrr x_vl, CSR_VL
+ csrr x_vcsr, CSR_VCSR
+ vsetvli incr, x0, e8, m8, ta, ma
+ vse8.v v0, (datap)
+ add datap, datap, incr
+ vse8.v v8, (datap)
+ add datap, datap, incr
+ vse8.v v16, (datap)
+ add datap, datap, incr
+ vse8.v v24, (datap)
+
+ REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep)
+ REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep)
+ REG_S x_vl, RISCV_V_STATE_VL(vstatep)
+ REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep)
+
+ csrc CSR_STATUS, status
+ ret
+ENDPROC(__vstate_save)
+
+ENTRY(__vstate_restore)
+ li status, SR_VS
+ csrs CSR_STATUS, status
+
+ vsetvli incr, x0, e8, m8, ta, ma
+ vle8.v v0, (datap)
+ add datap, datap, incr
+ vle8.v v8, (datap)
+ add datap, datap, incr
+ vle8.v v16, (datap)
+ add datap, datap, incr
+ vle8.v v24, (datap)
+
+ REG_L x_vstart, RISCV_V_STATE_VSTART(vstatep)
+ REG_L x_vtype, RISCV_V_STATE_VTYPE(vstatep)
+ REG_L x_vl, RISCV_V_STATE_VL(vstatep)
+ REG_L x_vcsr, RISCV_V_STATE_VCSR(vstatep)
+ vsetvl x0, x_vl, x_vtype
+ csrw CSR_VSTART, x_vstart
+ csrw CSR_VCSR, x_vcsr
+
+ csrc CSR_STATUS, status
+ ret
+ENDPROC(__vstate_restore)
+
+ENTRY(rvv_enable)
+ li status, SR_VS
+ csrs CSR_STATUS, status
+ ret
+ENDPROC(rvv_enable)
+
+ENTRY(rvv_disable)
+ li status, SR_VS
+ csrc CSR_STATUS, status
+ ret
+ENDPROC(rvv_disable)
--
2.17.1
On Wed, May 11, 2022 at 08:31:15AM +0000, Greentime Hu wrote:
> +#ifdef CONFIG_VECTOR
> +#include <asm/vector.h>
> +EXPORT_SYMBOL(rvv_enable);
> +EXPORT_SYMBOL(rvv_disable);
> +#endif
As far as I can tell these are not used by any modular code, just by
the later added kernel mode vector enable helpers.
Even if they were used this would need to be EXPORT_SYMBOL_GPL.
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2012 Regents of the University of California
> + * Copyright (C) 2017 SiFive
> + * Copyright (C) 2019 Alibaba Group Holding Limited
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation, version 2.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
No need for all the GPL boilerplate text when you have an SPDX tag.
On 5/15/22 23:47, Christoph Hellwig wrote:
> On Wed, May 11, 2022 at 08:31:15AM +0000, Greentime Hu wrote:
>> +#ifdef CONFIG_VECTOR
>> +#include <asm/vector.h>
>> +EXPORT_SYMBOL(rvv_enable);
>> +EXPORT_SYMBOL(rvv_disable);
>> +#endif
>
> As far as I can tell these are not used by any modular code, just by
> the later added kernel mode vector enable helpers.
>
> Even if they were used this would need to be EXPORT_SYMBOL_GPL.
In the new version, I've made them static inline given the size and
frequency of them being called. So this becomes moot.
>
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2012 Regents of the University of California
>> + * Copyright (C) 2017 SiFive
>> + * Copyright (C) 2019 Alibaba Group Holding Limited
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation, version 2.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>
> No need for all the GPL boilerplate text when you have an SPDX tag.
OK.