This patchset includes below fixes for clock driver
1> Fix Divider2 calculation
2> Memory leak in clock registration
3> Fix invalid name queries
4> Limit bestdiv with maxdiv
v2:
- Updated subject for cover letter and patches
to add prefix
Quanyang Wang (1):
drivers: clk: zynqmp: fix memory leak in zynqmp_register_clocks
Rajan Vaja (2):
drivers: clk: zynqmp: Limit bestdiv with maxdiv
drivers: clk: zynqmp: Fix invalid clock name queries
Tejas Patel (1):
drivers: clk: zynqmp: Fix divider2 calculation
drivers/clk/zynqmp/clkc.c | 20 ++++++++++++++------
drivers/clk/zynqmp/divider.c | 19 ++++++++++++++-----
2 files changed, 28 insertions(+), 11 deletions(-)
--
2.7.4
From: Tejas Patel <[email protected]>
zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock,
considering best possible combination of DIV1 and DIV2.
To find best possible values of DIV1 and DIV2, DIV1's parent rate
should be consider and not DIV2's parent rate since it would rate of
div1 clock. Consider a below topology,
out_clk->div2_clk->div1_clk->fixed_parent
where out_clk = (fixed_parent/div1_clk) / div2_clk, so parent clock
of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk.
Existing code divides parent rate of div2_clk's clock instead of
div1_clk's parent rate, which is wrong.
Fix the same by considering div1's parent clock rate.
Fixes: 4ebd92d2e228 ("clk: zynqmp: Fix divider calculation")
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
---
drivers/clk/zynqmp/divider.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 7d2cb61..dea3e21 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -112,23 +112,30 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
static void zynqmp_get_divider2_val(struct clk_hw *hw,
unsigned long rate,
- unsigned long parent_rate,
struct zynqmp_clk_divider *divider,
int *bestdiv)
{
int div1;
int div2;
long error = LONG_MAX;
- struct clk_hw *parent_hw = clk_hw_get_parent(hw);
- struct zynqmp_clk_divider *pdivider = to_zynqmp_clk_divider(parent_hw);
+ unsigned long div1_prate;
+ struct clk_hw *div1_parent_hw;
+ struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw);
+ struct zynqmp_clk_divider *pdivider =
+ to_zynqmp_clk_divider(div2_parent_hw);
if (!pdivider)
return;
+ div1_parent_hw = clk_hw_get_parent(div2_parent_hw);
+ if (!div1_parent_hw)
+ return;
+
+ div1_prate = clk_hw_get_rate(div1_parent_hw);
*bestdiv = 1;
for (div1 = 1; div1 <= pdivider->max_div;) {
for (div2 = 1; div2 <= divider->max_div;) {
- long new_error = ((parent_rate / div1) / div2) - rate;
+ long new_error = ((div1_prate / div1) / div2) - rate;
if (abs(new_error) < abs(error)) {
*bestdiv = div2;
@@ -193,7 +200,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
*/
if (div_type == TYPE_DIV2 &&
(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
- zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv);
+ zynqmp_get_divider2_val(hw, rate, divider, &bestdiv);
}
if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
--
2.7.4
From: Quanyang Wang <[email protected]>
This is detected by kmemleak running on zcu102 board:
unreferenced object 0xffffffc877e48180 (size 128):
comm "swapper/0", pid 1, jiffies 4294892909 (age 315.436s)
hex dump (first 32 bytes):
64 70 5f 76 69 64 65 6f 5f 72 65 66 5f 64 69 76 dp_video_ref_div
31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1...............
backtrace:
[<00000000c9be883b>] __kmalloc_track_caller+0x200/0x380
[<00000000f02c3809>] kvasprintf+0x7c/0x100
[<00000000e51dde4d>] kasprintf+0x60/0x80
[<0000000092298b05>] zynqmp_register_clocks+0x29c/0x398
[<00000000faaff182>] zynqmp_clock_probe+0x3cc/0x4c0
[<000000005f5986f0>] platform_drv_probe+0x58/0xa8
[<00000000d5810136>] really_probe+0xd8/0x2a8
[<00000000f5b671be>] driver_probe_device+0x5c/0x100
[<0000000038f91fcf>] __device_attach_driver+0x98/0xb8
[<000000008a3f2ac2>] bus_for_each_drv+0x74/0xd8
[<000000001cb2783d>] __device_attach+0xe0/0x140
[<00000000c268031b>] device_initial_probe+0x24/0x30
[<000000006998de4b>] bus_probe_device+0x9c/0xa8
[<00000000647ae6ff>] device_add+0x3c0/0x610
[<0000000071c14bb8>] of_device_add+0x40/0x50
[<000000004bb5d132>] of_platform_device_create_pdata+0xbc/0x138
This is because that when num_nodes is larger than 1, clk_out is
allocated using kasprintf for these nodes but only the last node's
clk_out is freed.
Signed-off-by: Quanyang Wang <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
---
drivers/clk/zynqmp/clkc.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index ff2d229..bfc1e7d 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -562,7 +562,7 @@ static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
{
int j;
u32 num_nodes, clk_dev_id;
- char *clk_out = NULL;
+ char *clk_out[MAX_NODES];
struct clock_topology *nodes;
struct clk_hw *hw = NULL;
@@ -576,16 +576,16 @@ static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
* Intermediate clock names are postfixed with type of clock.
*/
if (j != (num_nodes - 1)) {
- clk_out = kasprintf(GFP_KERNEL, "%s%s", clk_name,
+ clk_out[j] = kasprintf(GFP_KERNEL, "%s%s", clk_name,
clk_type_postfix[nodes[j].type]);
} else {
- clk_out = kasprintf(GFP_KERNEL, "%s", clk_name);
+ clk_out[j] = kasprintf(GFP_KERNEL, "%s", clk_name);
}
if (!clk_topology[nodes[j].type])
continue;
- hw = (*clk_topology[nodes[j].type])(clk_out, clk_dev_id,
+ hw = (*clk_topology[nodes[j].type])(clk_out[j], clk_dev_id,
parent_names,
num_parents,
&nodes[j]);
@@ -594,9 +594,12 @@ static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
__func__, clk_dev_id, clk_name,
PTR_ERR(hw));
- parent_names[0] = clk_out;
+ parent_names[0] = clk_out[j];
}
- kfree(clk_out);
+
+ for (j = 0; j < num_nodes; j++)
+ kfree(clk_out[j]);
+
return hw;
}
--
2.7.4
From: Rajan Vaja <[email protected]>
The clock driver makes EEMI call to get the name of invalid clk
when executing versal_get_clock_info() function. This results in
error messages.
Added check for validating clock before saving clock attribute and
calling zynqmp_pm_clock_get_name() in versal_get_clock_info() function.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
---
drivers/clk/zynqmp/clkc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index 4dd8413..ff2d229 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -667,6 +667,11 @@ static void zynqmp_get_clock_info(void)
continue;
clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]);
+ /* skip query for Invalid clock */
+ ret = zynqmp_is_valid_clock(i);
+ if (ret != CLK_ATTR_VALID)
+ continue;
+
clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ?
CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
--
2.7.4
A gentle reminder for review.
Thanks,
Jolly Shah
On 3/2/20, 1:51 PM, "Jolly Shah" <[email protected]> wrote:
This patchset includes below fixes for clock driver
1> Fix Divider2 calculation
2> Memory leak in clock registration
3> Fix invalid name queries
4> Limit bestdiv with maxdiv
v2:
- Updated subject for cover letter and patches
to add prefix
Quanyang Wang (1):
drivers: clk: zynqmp: fix memory leak in zynqmp_register_clocks
Rajan Vaja (2):
drivers: clk: zynqmp: Limit bestdiv with maxdiv
drivers: clk: zynqmp: Fix invalid clock name queries
Tejas Patel (1):
drivers: clk: zynqmp: Fix divider2 calculation
drivers/clk/zynqmp/clkc.c | 20 ++++++++++++++------
drivers/clk/zynqmp/divider.c | 19 ++++++++++++++-----
2 files changed, 28 insertions(+), 11 deletions(-)
--
2.7.4
Hi Stephan,
Ping. Please review.
Thanks,
Jolly Shah
> ------Original Message------
> From: Jolly Shah <[email protected]>
> Sent: Monday, March 02, 2020 1:50PM
> To: Olof <[email protected]>, Mturquette <[email protected]>,
Sboyd <[email protected]>, Michal Simek <[email protected]>, Arm
<[email protected]>, Linux-clk <[email protected]>
> Cc: Rajan Vaja <[email protected]>,
[email protected]
<[email protected]>, [email protected]
<[email protected]>, Jolly Shah <[email protected]>
> Subject: [PATCH v2 0/4] drivers: clk: zynqmp: minor bux fixes for
zynqmp clock driver
>
> This patchset includes below fixes for clock driver
> 1> Fix Divider2 calculation
> 2> Memory leak in clock registration
> 3> Fix invalid name queries
> 4> Limit bestdiv with maxdiv
>
> v2:
> - Updated subject for cover letter and patches
> to add prefix
>
> Quanyang Wang (1):
> drivers: clk: zynqmp: fix memory leak in zynqmp_register_clocks
>
> Rajan Vaja (2):
> drivers: clk: zynqmp: Limit bestdiv with maxdiv
> drivers: clk: zynqmp: Fix invalid clock name queries
>
> Tejas Patel (1):
> drivers: clk: zynqmp: Fix divider2 calculation
>
> drivers/clk/zynqmp/clkc.c | 20 ++++++++++++++------
> drivers/clk/zynqmp/divider.c | 19 ++++++++++++++-----
> 2 files changed, 28 insertions(+), 11 deletions(-)
>
Hi Stephen,
On 02. 03. 20 22:50, Jolly Shah wrote:
> This patchset includes below fixes for clock driver
> 1> Fix Divider2 calculation
> 2> Memory leak in clock registration
> 3> Fix invalid name queries
> 4> Limit bestdiv with maxdiv
>
> v2:
> - Updated subject for cover letter and patches
> to add prefix
>
> Quanyang Wang (1):
> drivers: clk: zynqmp: fix memory leak in zynqmp_register_clocks
>
> Rajan Vaja (2):
> drivers: clk: zynqmp: Limit bestdiv with maxdiv
> drivers: clk: zynqmp: Fix invalid clock name queries
>
> Tejas Patel (1):
> drivers: clk: zynqmp: Fix divider2 calculation
>
> drivers/clk/zynqmp/clkc.c | 20 ++++++++++++++------
> drivers/clk/zynqmp/divider.c | 19 ++++++++++++++-----
> 2 files changed, 28 insertions(+), 11 deletions(-)
>
Do you see any issue with this patchset? Or do you want me to take it
via my tree? I can't see any dependency that's why I think it shouldn't
be a problem to take it via your tree.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: http://www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Quoting Jolly Shah (2020-03-02 13:50:42)
> From: Rajan Vaja <[email protected]>
>
> The clock driver makes EEMI call to get the name of invalid clk
> when executing versal_get_clock_info() function. This results in
> error messages.
> Added check for validating clock before saving clock attribute and
> calling zynqmp_pm_clock_get_name() in versal_get_clock_info() function.
>
> Signed-off-by: Rajan Vaja <[email protected]>
> Signed-off-by: Tejas Patel <[email protected]>
> Signed-off-by: Jolly Shah <[email protected]>
> ---
Applied to clk-next
Quoting Jolly Shah (2020-03-02 13:50:41)
> From: Tejas Patel <[email protected]>
>
> zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock,
> considering best possible combination of DIV1 and DIV2.
>
> To find best possible values of DIV1 and DIV2, DIV1's parent rate
> should be consider and not DIV2's parent rate since it would rate of
> div1 clock. Consider a below topology,
>
> out_clk->div2_clk->div1_clk->fixed_parent
>
> where out_clk = (fixed_parent/div1_clk) / div2_clk, so parent clock
> of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk.
>
> Existing code divides parent rate of div2_clk's clock instead of
> div1_clk's parent rate, which is wrong.
>
> Fix the same by considering div1's parent clock rate.
>
> Fixes: 4ebd92d2e228 ("clk: zynqmp: Fix divider calculation")
> Signed-off-by: Tejas Patel <[email protected]>
> Signed-off-by: Jolly Shah <[email protected]>
> ---
Applied to clk-next
Quoting Jolly Shah (2020-03-02 13:50:43)
> From: Quanyang Wang <[email protected]>
>
> This is detected by kmemleak running on zcu102 board:
>
> unreferenced object 0xffffffc877e48180 (size 128):
> comm "swapper/0", pid 1, jiffies 4294892909 (age 315.436s)
> hex dump (first 32 bytes):
> 64 70 5f 76 69 64 65 6f 5f 72 65 66 5f 64 69 76 dp_video_ref_div
> 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1...............
> backtrace:
> [<00000000c9be883b>] __kmalloc_track_caller+0x200/0x380
> [<00000000f02c3809>] kvasprintf+0x7c/0x100
> [<00000000e51dde4d>] kasprintf+0x60/0x80
> [<0000000092298b05>] zynqmp_register_clocks+0x29c/0x398
> [<00000000faaff182>] zynqmp_clock_probe+0x3cc/0x4c0
> [<000000005f5986f0>] platform_drv_probe+0x58/0xa8
> [<00000000d5810136>] really_probe+0xd8/0x2a8
> [<00000000f5b671be>] driver_probe_device+0x5c/0x100
> [<0000000038f91fcf>] __device_attach_driver+0x98/0xb8
> [<000000008a3f2ac2>] bus_for_each_drv+0x74/0xd8
> [<000000001cb2783d>] __device_attach+0xe0/0x140
> [<00000000c268031b>] device_initial_probe+0x24/0x30
> [<000000006998de4b>] bus_probe_device+0x9c/0xa8
> [<00000000647ae6ff>] device_add+0x3c0/0x610
> [<0000000071c14bb8>] of_device_add+0x40/0x50
> [<000000004bb5d132>] of_platform_device_create_pdata+0xbc/0x138
>
> This is because that when num_nodes is larger than 1, clk_out is
> allocated using kasprintf for these nodes but only the last node's
> clk_out is freed.
>
> Signed-off-by: Quanyang Wang <[email protected]>
> Signed-off-by: Michal Simek <[email protected]>
> Signed-off-by: Tejas Patel <[email protected]>
> Signed-off-by: Jolly Shah <[email protected]>
> ---
Applied to clk-next