> + phy-reset-gpio:
> + minItems: 1
> + maxItems: 3
> + description:
> + GPIO used to reset the PHY, each GPIO is for resetting the connected
> + ethernet PHY device.
This is a PHY property, so should be in the PHY node. phylib should
then take care of fit.
> +
> + phyaddr-fixup:
> + description: Register address for programing MDIO address of PHY devices
Please give a better description of this and the next two properties.
> +
> + pcsaddr-fixup:
> + description: Register address for programing MDIO address of PCS devices
> +
> + mdio-clk-fixup:
> + description: The initialization clocks to be configured
> +
> + fixup:
> + description: The MDIO address of PHY/PCS device to be programed
> + clocks:
> + items:
> + - description: MDIO clock source frequency fixed to 100MHZ
> + - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ
> + - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ
> + - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ
> + - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ
The clock frequencies is not relevent here, the driver sets that up.
Andrew
On 11/15/2023 10:35 PM, Andrew Lunn wrote:
>> + phy-reset-gpio:
>> + minItems: 1
>> + maxItems: 3
>> + description:
>> + GPIO used to reset the PHY, each GPIO is for resetting the connected
>> + ethernet PHY device.
>
> This is a PHY property, so should be in the PHY node. phylib should
> then take care of fit.
will check this and update in the next patch set.
>
>> +
>> + phyaddr-fixup:
>> + description: Register address for programing MDIO address of PHY devices
>
> Please give a better description of this and the next two properties.
these fixup flags are for customizing the MDIO address of qca8084 PHY &
PCS and doing the initialization configurations to bring up PHY.
will describe it more detail in the next patch set.
>
>> +
>> + pcsaddr-fixup:
>> + description: Register address for programing MDIO address of PCS devices
>> +
>> + mdio-clk-fixup:
>> + description: The initialization clocks to be configured
>> +
>> + fixup:
>> + description: The MDIO address of PHY/PCS device to be programed
>> + clocks:
>> + items:
>> + - description: MDIO clock source frequency fixed to 100MHZ
>> + - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ
>> + - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ
>> + - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ
>> + - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ
>
> The clock frequencies is not relevent here, the driver sets that up.
OK, will remove the clock frequency values in the next patch set.
>
> Andrew