This series adds basic support for J722S family of SoCs. Also add
J722S EVM support with basic peripheral like MMC and UART.
TRM: https://www.ti.com/lit/zip/sprujb3
EVM Schematics: https://www.ti.com/lit/zip/sprr495
Bootlog (6.8.0-rc3-next-20240206):
https://gist.github.com/vaishnavachath/23d859925277df9ccd628190e7c23371
Changelog:
V1->V2:
* Address feedback from Nishanth to reuse from AM62P5 dtsi.
* Remove bootph-all from root nodes.
* Change License to GPL-2.0-only OR MIT as followed for other
K3 files.
Vaishnav Achath (3):
dt-bindings: arm: ti: Add bindings for J722S SoCs
arm64: dts: ti: Introduce J722S family of SoCs
arm64: dts: ti: Add support for TI J722S Evaluation Module
.../devicetree/bindings/arm/ti/k3.yaml | 6 +
arch/arm64/boot/dts/ti/Makefile | 3 +
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 251 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 89 +++++++
arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +
5 files changed, 352 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s.dtsi
--
2.34.1
Add basic support for the J722S EVM with UART console and
MMC SD as rootfs.
Schematics are available at:
https://www.ti.com/lit/zip/sprr495
Co-developed-by: Jayesh Choudhary <[email protected]>
Signed-off-by: Jayesh Choudhary <[email protected]>
Signed-off-by: Vaishnav Achath <[email protected]>
---
V1->V2:
* Address feedback from Nishanth to reuse from AM62P5 dtsi.
* Remove bootph-all from root nodes.
* Change License to GPL-2.0-only OR MIT as followed for other
K3 files.
* Add label for reserved_memory node.
arch/arm64/boot/dts/ti/Makefile | 3 +
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 251 ++++++++++++++++++++++++
2 files changed, 254 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm.dts
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 52c1dc910308..ecd11f444e81 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -78,6 +78,9 @@ k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-boa
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
+# Boards with J722s SoC
+dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
+
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
new file mode 100644
index 000000000000..b4f2fee53a97
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the J722S EVM
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Schematics: https://www.ti.com/lit/zip/sprr495
+ */
+
+/dts-v1/;
+
+#include "k3-j722s.dtsi"
+
+/ {
+ compatible = "ti,j722s-evm", "ti,j722s";
+ model = "Texas Instruments J722S EVM";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial2 = &main_uart0;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ stdout-path = &main_uart0;
+ };
+
+ memory@80000000 {
+ /* 8G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000001 0x80000000>;
+ device_type = "memory";
+ bootph-pre-ram;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_tfa_ddr: tfa@9e780000 {
+ reg = <0x00 0x9e780000 0x00 0x80000>;
+ no-map;
+ };
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ };
+
+ vmain_pd: regulator-0 {
+ /* TPS65988 PD CONTROLLER OUTPUT */
+ compatible = "regulator-fixed";
+ regulator-name = "vmain_pd";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ bootph-all;
+ };
+
+ vsys_5v0: regulator-vsys5v0 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vmain_pd>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: regulator-mmc1 {
+ /* TPS22918DBVR */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&exp1 15 GPIO_ACTIVE_HIGH>;
+ bootph-all;
+ };
+
+ vdd_sd_dv: regulator-TLV71033 {
+ compatible = "regulator-gpio";
+ regulator-name = "tlv71033";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ vsys_io_1v8: regulator-vsys-io-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_io_1v2: regulator-vsys-io-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_io_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&main_pmx0 {
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */
+ J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */
+ >;
+ bootph-all;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
+ J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
+ >;
+ bootph-all;
+ };
+
+ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */
+ >;
+ bootph-all;
+ };
+
+ main_mmc1_pins_default: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */
+ J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */
+ J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */
+ J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */
+ J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */
+ J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */
+ J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */
+ >;
+ bootph-all;
+ };
+};
+
+&main_gpio1 {
+ status = "okay";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ status = "okay";
+ bootph-all;
+};
+
+&mcu_pmx0 {
+
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */
+ J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */
+ J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */
+ J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */
+ >;
+ bootph-all;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */
+ J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */
+ >;
+ bootph-all;
+ };
+};
+
+&wkup_uart0 {
+ /* WKUP UART0 is used by Device Manager firmware */
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "reserved";
+ bootph-all;
+};
+
+&wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+ bootph-all;
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+ bootph-all;
+
+ exp1: gpio@23 {
+ compatible = "ti,tca6424";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL",
+ "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#",
+ "CSI_VIO_SEL", "USB2.0_MUX_SEL",
+ "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2",
+ "LMK1_OE1", "LMK1_OE0",
+ "LMK2_OE0", "LMK2_OE1",
+ "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn",
+ "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN",
+ "USER_LED2", "MCAN0_STB",
+ "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
+ "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
+ "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+ };
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ no-1-8-v;
+ status = "okay";
+ bootph-all;
+};
--
2.34.1
The J722S is a family of application processors built for Automotive and
Linux Application development. J722S family of SoCs is a superset of the
AM62P SoC family and shares similar memory map, thus the nodes are being
reused from AM62P includes instead of duplicating the definitions.
Some highlights of J722S SoC (in addition to AM62P SoC features) are:
* Two Cortex-R5F for Functional Safety or general-purpose usage and
two C7x floating point vector DSP with Matrix Multiply Accelerator
for deep learning.
* Vision Processing Accelerator (VPAC) with image signal processor
and Depth and Motion Processing Accelerator (DMPAC).
* 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
ePWM, among other peripherals.
For those interested, more details about this SoC can be found in the
Technical Reference Manual here:
https://www.ti.com/lit/zip/sprujb3
Co-developed-by: Jayesh Choudhary <[email protected]>
Signed-off-by: Jayesh Choudhary <[email protected]>
Signed-off-by: Vaishnav Achath <[email protected]>
---
checkpatch error is ignored for arch/arm64/boot/dts/ti/k3-pinctrl.h:
ERROR: Macros with complex values should be enclosed in parentheses
However, we do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
done for other similar platforms.
V1->V2:
* Address feedback from Nishanth to reuse by including AM62P5 dtsi.
* Remove bootph-all from root nodes.
* Change License to GPL-2.0-only OR MIT as followed for other
K3 files.
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 89 ++++++++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +
2 files changed, 92 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
new file mode 100644
index 000000000000..c75744edb143
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree Source for J722S SoC Family
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-am62p5.dtsi"
+
+/ {
+ model = "Texas Instruments K3 J722S SoC";
+ compatible = "ti,j722s";
+
+ cbass_main: bus@f0000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
+ <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
+ <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
+ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */
+ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
+ <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */
+ <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */
+ <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
+ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
+ <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
+ <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
+ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
+ <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
+ <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */
+ <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */
+ <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */
+ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
+ <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
+ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
+ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
+ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
+ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+ <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */
+ <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */
+ <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */
+ <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */
+ <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */
+ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+ <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
+
+ /* MCU Domain Range */
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
+ <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
+ <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
+ <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
+ <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,
+
+ /* Wakeup Domain Range */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
+ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
+ <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
+ <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
+ };
+};
+
+/* Main domain overrides */
+
+&inta_main_dmss {
+ ti,interrupt-ranges = <7 71 21>;
+};
+
+&oc_sram {
+ reg = <0x00 0x70000000 0x00 0x40000>;
+ ranges = <0x00 0x00 0x70000000 0x40000>;
+};
diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
index 2a4e0e084d69..591be4489f37 100644
--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
+++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
@@ -59,6 +59,9 @@
#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J722S_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J722S_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
--
2.34.1
Add bindings for TI J722S family of devices.
Signed-off-by: Vaishnav Achath <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index c6506bccfe88..d52672348424 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -123,6 +123,12 @@ properties:
- ti,j721s2-evm
- const: ti,j721s2
+ - description: K3 J722S SoC and Boards
+ items:
+ - enum:
+ - ti,j722s-evm
+ - const: ti,j722s
+
- description: K3 J784s4 SoC
items:
- enum:
--
2.34.1
Hi all,
On 06/02/24 15:36, Vaishnav Achath wrote:
> This series adds basic support for J722S family of SoCs. Also add
> J722S EVM support with basic peripheral like MMC and UART.
>
> TRM: https://www.ti.com/lit/zip/sprujb3
> EVM Schematics: https://www.ti.com/lit/zip/sprr495
>
> Bootlog (6.8.0-rc3-next-20240206):
> https://gist.github.com/vaishnavachath/23d859925277df9ccd628190e7c23371
>
I missed to add link to V1 here, this a V2 of the below series with the
feedback addressed:
https://lore.kernel.org/all/[email protected]/
Thanks and Regards,
Vaishnav
> Changelog:
> V1->V2:
> * Address feedback from Nishanth to reuse from AM62P5 dtsi.
> * Remove bootph-all from root nodes.
> * Change License to GPL-2.0-only OR MIT as followed for other
> K3 files.
>
> Vaishnav Achath (3):
> dt-bindings: arm: ti: Add bindings for J722S SoCs
> arm64: dts: ti: Introduce J722S family of SoCs
> arm64: dts: ti: Add support for TI J722S Evaluation Module
>
> .../devicetree/bindings/arm/ti/k3.yaml | 6 +
> arch/arm64/boot/dts/ti/Makefile | 3 +
> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 251 ++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 89 +++++++
> arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +
> 5 files changed, 352 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> create mode 100644 arch/arm64/boot/dts/ti/k3-j722s.dtsi
>
Hi Vaishnav,
On 15:36-20240206, Vaishnav Achath wrote:
> This series adds basic support for J722S family of SoCs. Also add
> J722S EVM support with basic peripheral like MMC and UART.
>
> TRM: https://www.ti.com/lit/zip/sprujb3
> EVM Schematics: https://www.ti.com/lit/zip/sprr495
>
> Bootlog (6.8.0-rc3-next-20240206):
> https://gist.github.com/vaishnavachath/23d859925277df9ccd628190e7c23371
>
> Changelog:
> V1->V2:
> * Address feedback from Nishanth to reuse from AM62P5 dtsi.
> * Remove bootph-all from root nodes.
> * Change License to GPL-2.0-only OR MIT as followed for other
> K3 files.
>
> Vaishnav Achath (3):
> dt-bindings: arm: ti: Add bindings for J722S SoCs
> arm64: dts: ti: Introduce J722S family of SoCs
> arm64: dts: ti: Add support for TI J722S Evaluation Module
>
For the series,
Reviewed-by: Manorit Chawdhry <[email protected]>
Regards,
Manorit
> .../devicetree/bindings/arm/ti/k3.yaml | 6 +
> arch/arm64/boot/dts/ti/Makefile | 3 +
> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 251 ++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 89 +++++++
> arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +
> 5 files changed, 352 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> create mode 100644 arch/arm64/boot/dts/ti/k3-j722s.dtsi
>
> --
> 2.34.1
>
Hi,
On Tue Feb 6, 2024 at 11:06 AM CET, Vaishnav Achath wrote:
> +# Boards with J722s SoC
> +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
I'm a bit confused by your names. What are the new/correct ones now?
Some seem to use the amXX names and some the jXX ones. I've read [1]
and it appears it was suggested to use the am67 names for the device
trees. Esp. because there is already, am62, am64, am65, am68 and
am69 in as names for the device trees.
The TRM you've linked in the cover letter doesn't shed much light
either. It just lists both.
-michael
[1] https://lore.kernel.org/all/[email protected]/
Hi Michael,
On 12/02/24 21:32, Michael Walle wrote:
> Hi,
>
> On Tue Feb 6, 2024 at 11:06 AM CET, Vaishnav Achath wrote:
>> +# Boards with J722s SoC
>> +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
>
> I'm a bit confused by your names. What are the new/correct ones now?
> Some seem to use the amXX names and some the jXX ones. I've read [1]
> and it appears it was suggested to use the am67 names for the device
> trees. Esp. because there is already, am62, am64, am65, am68 and
> am69 in as names for the device trees.
>
> The TRM you've linked in the cover letter doesn't shed much light
> either. It just lists both.
>
Both names are correct, for other Jacinto devices J721S2 and J784S4, the
industrial variants (AM68, AM69 respectively) and those boards were
announced at a later point of time and since the automotive/J7 variants
were introduced first, the SoC dtsi and files have the J7XX names, for
AM62/AM64 there is no confusion in naming, in this case the initial TRM
itself mentions J722S and AM67 variants with similar capabilities, the
reasoning behind continuing with the J722S name is because the initial
support is being added for J722S EVM (the top marking on the SoC package
populated on the EVM say XJ722SAMW, this can be seen in the schematics
also), please let know if this clarifies the confusion.
Thanks and Regards,
Vaishnav
> -michael
>
> [1] https://lore.kernel.org/all/[email protected]/
On 14/02/24 13:13, Vaishnav Achath wrote:
> Hi Michael,
>
> On 12/02/24 21:32, Michael Walle wrote:
>> Hi,
>>
>> On Tue Feb 6, 2024 at 11:06 AM CET, Vaishnav Achath wrote:
>>> +# Boards with J722s SoC
>>> +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
>>
>> I'm a bit confused by your names. What are the new/correct ones now?
>> Some seem to use the amXX names and some the jXX ones. I've read [1]
>> and it appears it was suggested to use the am67 names for the device
>> trees. Esp. because there is already, am62, am64, am65, am68 and
>> am69 in as names for the device trees.
>>
>> The TRM you've linked in the cover letter doesn't shed much light
>> either. It just lists both.
>>
>
> Both names are correct, for other Jacinto devices J721S2 and J784S4, the
> industrial variants (AM68, AM69 respectively) and those boards were
> announced at a later point of time and since the automotive/J7 variants
> were introduced first, the SoC dtsi and files have the J7XX names, for
> AM62/AM64 there is no confusion in naming, in this case the initial TRM
> itself mentions J722S and AM67 variants with similar capabilities, the
> reasoning behind continuing with the J722S name is because the initial
> support is being added for J722S EVM (the top marking on the SoC package
> populated on the EVM say XJ722SAMW, this can be seen in the schematics
> also), please let know if this clarifies the confusion.
>
AM64,AM62x/A/P are from different product line (Sitara) and don't have
any other aliases.
On the other hand, Jacinto SoCs have both J7xx variant and AM6xx part
numbers. Its being really unpredictable wrt when AM6xx variants of
Jacinto devices come out. So as a general rule, we name the DTS files
based on the name of the first device that comes out in the market which
has consistently been J7xx.
--
Regards
Vignesh
Hi,
On Wed Feb 14, 2024 at 10:42 AM CET, Vignesh Raghavendra wrote:
> On 14/02/24 13:13, Vaishnav Achath wrote:
> > On 12/02/24 21:32, Michael Walle wrote:
> >> On Tue Feb 6, 2024 at 11:06 AM CET, Vaishnav Achath wrote:
> >>> +# Boards with J722s SoC
> >>> +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
> >>
> >> I'm a bit confused by your names. What are the new/correct ones now?
> >> Some seem to use the amXX names and some the jXX ones. I've read [1]
> >> and it appears it was suggested to use the am67 names for the device
> >> trees. Esp. because there is already, am62, am64, am65, am68 and
> >> am69 in as names for the device trees.
> >>
> >> The TRM you've linked in the cover letter doesn't shed much light
> >> either. It just lists both.
> >>
> >
> > Both names are correct, for other Jacinto devices J721S2 and J784S4, the
> > industrial variants (AM68, AM69 respectively) and those boards were
> > announced at a later point of time and since the automotive/J7 variants
> > were introduced first, the SoC dtsi and files have the J7XX names, for
> > AM62/AM64 there is no confusion in naming, in this case the initial TRM
> > itself mentions J722S and AM67 variants with similar capabilities, the
> > reasoning behind continuing with the J722S name is because the initial
> > support is being added for J722S EVM (the top marking on the SoC package
> > populated on the EVM say XJ722SAMW, this can be seen in the schematics
> > also), please let know if this clarifies the confusion.
> >
>
> AM64,AM62x/A/P are from different product line (Sitara) and don't have
> any other aliases.
>
> On the other hand, Jacinto SoCs have both J7xx variant and AM6xx part
> numbers. Its being really unpredictable wrt when AM6xx variants of
> Jacinto devices come out. So as a general rule, we name the DTS files
> based on the name of the first device that comes out in the market which
> has consistently been J7xx.
Thanks for the explanation. I just noticed that any k3-am6[89]*
device trees will include the j7xx SoC dtsi. That would have been my
next question: Boards with the AMxx will have the "correct" name
k3-amNN-*.
-michael
Hi Vaishnav Achath,
On Tue, 06 Feb 2024 15:36:05 +0530, Vaishnav Achath wrote:
> This series adds basic support for J722S family of SoCs. Also add
> J722S EVM support with basic peripheral like MMC and UART.
>
> TRM: https://www.ti.com/lit/zip/sprujb3
> EVM Schematics: https://www.ti.com/lit/zip/sprr495
>
> Bootlog (6.8.0-rc3-next-20240206):
> https://gist.github.com/vaishnavachath/23d859925277df9ccd628190e7c23371
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/3] dt-bindings: arm: ti: Add bindings for J722S SoCs
commit: de82585f62e08283572d385d0cd6b57893a99d1c
[2/3] arm64: dts: ti: Introduce J722S family of SoCs
commit: ea55b9335ad81e32f2833c71b2dcb591792e54dd
[3/3] arm64: dts: ti: Add support for TI J722S Evaluation Module
commit: 2f277dbe1a4ac40b1157ba3b2914d39f4040bbed
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh