Changes in v2:
- Use dp bridge to set psr entry/exit instead of dpu_enocder.
- Don't modify whitespaces.
- Set self refresh aware from atomic_check.
- Set self refresh aware only if psr is supported.
- Provide a stub for msm_dp_display_set_psr.
- Move dp functions to bridge code.
Changes in v3:
- Change callback names to reflect atomic interfaces.
- Move bridge callback change to separate patch as suggested by Dmitry.
- Remove psr function declaration from msm_drv.h.
- Set self_refresh_aware flag only if psr is supported.
- Modify the variable names to simpler form.
- Define bit fields for PSR settings.
- Add comments explaining the steps to enter/exit psr.
- Change DRM_INFO to drm_dbg_db.
Changes in v4:
- Move the get crtc functions to drm_atomic.
- Add atomic functions for DP bridge too.
- Add ternary operator to choose eDP or DP ops.
- Return true/false instead of 1/0.
- mode_valid missing in the eDP bridge ops.
- Move the functions to get crtc into drm_atomic.c.
- Fix compilation issues.
- Remove dpu_assign_crtc and get crtc from drm_enc instead of dpu_enc.
- Check for crtc state enable while reserving resources.
Changes in v5:
- Move the mode_valid changes into a different patch.
- Complete psr_op_comp only when isr is set.
- Move the DP atomic callback changes to a different patch.
- Get crtc from drm connector state crtc.
- Move to separate patch for check for crtc state enable while
reserving resources.
Changes in v6:
- Remove crtc from dpu_encoder_virt struct.
- fix crtc check during vblank toggle crtc.
- Misc changes.
Changes in v7:
- Add fix for underrun issue on kasan build.
Changes in v8:
- Drop the enc spinlock as it won't serve any purpose in
protetcing conn state.(Dmitry/Doug)
Changes in v9:
- Update commit message and fix alignment using spaces.(Marijn)
- Misc changes.(Marijn)
Changes in v10:
- Get crtc cached in dpu_enc during obj init.(Dmitry)
Changes in v11:
- Remove crtc cached in dpu_enc during obj init.
- Update dpu_enc crtc state on crtc enable/disable during self refresh.
Changes in v12:
- Update sc7180 intf mask to get intf timing gen status
based on DPU_INTF_STATUS_SUPPORTED bit.(Dmitry)
- Remove "clear active interface in the datapath cleanup" change
as it is already included.
- Move core changes to top of the series.(Dmitry)
Sankeerth Billakanti (1):
drm/msm/dp: disable self_refresh_aware after entering psr
Vinod Polimera (13):
drm/msm/disp/dpu: check for crtc enable rather than crtc active to
release shared resources
drm/msm/disp/dpu: get timing engine status from intf status register
drm/msm/disp/dpu: wait for extra vsync till timing engine status is
disabled
drm/msm/disp/dpu: reset the datapath after timing engine disable
drm: add helper functions to retrieve old and new crtc
drm/msm/dp: use atomic callbacks for DP bridge ops
drm/msm/dp: Add basic PSR support for eDP
drm/msm/dp: use the eDP bridge ops to validate eDP modes
drm/bridge: use atomic enable/disable callbacks for panel bridge
drm/bridge: add psr support for panel bridge callbacks
drm/msm/disp/dpu: use atomic enable/disable callbacks for encoder
functions
drm/msm/disp/dpu: add PSR support for eDP interface in dpu driver
drm/msm/disp/dpu: update dpu_enc crtc state on crtc enable/disable
during self refresh
drivers/gpu/drm/bridge/panel.c | 68 +++++++-
drivers/gpu/drm/drm_atomic.c | 60 +++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 40 ++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 ++-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 22 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/dp/dp_catalog.c | 80 +++++++++
drivers/gpu/drm/msm/dp/dp_catalog.h | 4 +
drivers/gpu/drm/msm/dp/dp_ctrl.c | 80 +++++++++
drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +
drivers/gpu/drm/msm/dp/dp_display.c | 36 ++--
drivers/gpu/drm/msm/dp/dp_display.h | 2 +
drivers/gpu/drm/msm/dp/dp_drm.c | 194 ++++++++++++++++++++-
drivers/gpu/drm/msm/dp/dp_drm.h | 9 +-
drivers/gpu/drm/msm/dp/dp_link.c | 36 ++++
drivers/gpu/drm/msm/dp/dp_panel.c | 22 +++
drivers/gpu/drm/msm/dp/dp_panel.h | 6 +
drivers/gpu/drm/msm/dp/dp_reg.h | 27 +++
include/drm/drm_atomic.h | 7 +
22 files changed, 706 insertions(+), 44 deletions(-)
--
2.7.4
According to KMS documentation, The driver must not release any shared
resources if active is set to false but enable still true.
Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset")
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 758261e..c237003 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -652,7 +652,7 @@ static int dpu_encoder_virt_atomic_check(
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
dpu_rm_release(global_state, drm_enc);
- if (!crtc_state->active_changed || crtc_state->active)
+ if (!crtc_state->active_changed || crtc_state->enable)
ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
drm_enc, crtc_state, topology);
}
--
2.7.4
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ++++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +++++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +++++++-
3 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index cf053e8..ce6e9e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -78,9 +78,11 @@
#define INTF_SDM845_MASK (0)
-#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
+#define INTF_SC7180_MASK \
+ (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED))
-#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
+#define INTF_SC7280_MASK \
+ (INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN))
#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index ddab9ca..08cd1a1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -213,17 +213,19 @@ enum {
/**
* INTF sub-blocks
- * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
- * pixel data arrives to this INTF
- * @DPU_INTF_TE INTF block has TE configuration support
- * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
- than video timing
+ * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
+ * pixel data arrives to this INTF
+ * @DPU_INTF_TE INTF block has TE configuration support
+ * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
+ * than video timing
+ * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
* @DPU_INTF_MAX
*/
enum {
DPU_INTF_INPUT_CTRL = 0x1,
DPU_INTF_TE,
DPU_DATA_HCTL_EN,
+ DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 7ce66bf..84ee2ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -62,6 +62,7 @@
#define INTF_LINE_COUNT 0x0B0
#define INTF_MUX 0x25C
+#define INTF_STATUS 0x26C
#define INTF_CFG_ACTIVE_H_EN BIT(29)
#define INTF_CFG_ACTIVE_V_EN BIT(30)
@@ -297,8 +298,13 @@ static void dpu_hw_intf_get_status(
struct intf_status *s)
{
struct dpu_hw_blk_reg_map *c = &intf->hw;
+ unsigned long cap = intf->cap->features;
+
+ if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))
+ s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);
+ else
+ s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
- s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31));
if (s->is_en) {
s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
--
2.7.4
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 48c4810..0396084 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -523,6 +523,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
{
unsigned long lock_flags;
int ret;
+ struct intf_status intf_status = {0};
if (!phys_enc->parent || !phys_enc->parent->dev) {
DPU_ERROR("invalid encoder/device\n");
@@ -567,6 +568,26 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
}
}
+ if (phys_enc->hw_intf && phys_enc->hw_intf->ops.get_status)
+ phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &intf_status);
+
+ /*
+ * Wait for a vsync if timing en status is on after timing engine
+ * is disabled.
+ */
+ if (intf_status.is_en && dpu_encoder_phys_vid_is_master(phys_enc)) {
+ spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
+ dpu_encoder_phys_inc_pending(phys_enc);
+ spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
+ ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
+ if (ret) {
+ atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+ DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
+ DRMID(phys_enc->parent),
+ phys_enc->hw_intf->idx - INTF_0, ret);
+ }
+ }
+
phys_enc->enable_state = DPU_ENC_DISABLED;
}
--
2.7.4
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 0396084..3a37429 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -588,6 +588,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
}
}
+ dpu_encoder_helper_phys_cleanup(phys_enc);
phys_enc->enable_state = DPU_ENC_DISABLED;
}
--
2.7.4
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti <[email protected]>
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Reviewed-by: Daniel Vetter <[email protected]>
---
drivers/gpu/drm/drm_atomic.c | 60 ++++++++++++++++++++++++++++++++++++++++++++
include/drm/drm_atomic.h | 7 ++++++
2 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 5457c02..7cc39f6 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -985,6 +985,66 @@ drm_atomic_get_new_connector_for_encoder(const struct drm_atomic_state *state,
EXPORT_SYMBOL(drm_atomic_get_new_connector_for_encoder);
/**
+ * drm_atomic_get_old_crtc_for_encoder - Get old crtc for an encoder
+ * @state: Atomic state
+ * @encoder: The encoder to fetch the crtc state for
+ *
+ * This function finds and returns the crtc that was connected to @encoder
+ * as specified by the @state.
+ *
+ * Returns: The old crtc connected to @encoder, or NULL if the encoder is
+ * not connected.
+ */
+struct drm_crtc *
+drm_atomic_get_old_crtc_for_encoder(struct drm_atomic_state *state,
+ struct drm_encoder *encoder)
+{
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state;
+
+ connector = drm_atomic_get_old_connector_for_encoder(state, encoder);
+ if (!connector)
+ return NULL;
+
+ conn_state = drm_atomic_get_old_connector_state(state, connector);
+ if (!conn_state)
+ return NULL;
+
+ return conn_state->crtc;
+}
+EXPORT_SYMBOL(drm_atomic_get_old_crtc_for_encoder);
+
+/**
+ * drm_atomic_get_new_crtc_for_encoder - Get new crtc for an encoder
+ * @state: Atomic state
+ * @encoder: The encoder to fetch the crtc state for
+ *
+ * This function finds and returns the crtc that will be connected to @encoder
+ * as specified by the @state.
+ *
+ * Returns: The new crtc connected to @encoder, or NULL if the encoder is
+ * not connected.
+ */
+struct drm_crtc *
+drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_state *state,
+ struct drm_encoder *encoder)
+{
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state;
+
+ connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
+ if (!connector)
+ return NULL;
+
+ conn_state = drm_atomic_get_new_connector_state(state, connector);
+ if (!conn_state)
+ return NULL;
+
+ return conn_state->crtc;
+}
+EXPORT_SYMBOL(drm_atomic_get_new_crtc_for_encoder);
+
+/**
* drm_atomic_get_connector_state - get connector state
* @state: global atomic state object
* @connector: connector to get state object for
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index 92586ab..9a022ca 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -528,6 +528,13 @@ struct drm_connector *
drm_atomic_get_new_connector_for_encoder(const struct drm_atomic_state *state,
struct drm_encoder *encoder);
+struct drm_crtc *
+drm_atomic_get_old_crtc_for_encoder(struct drm_atomic_state *state,
+ struct drm_encoder *encoder);
+struct drm_crtc *
+drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_state *state,
+ struct drm_encoder *encoder);
+
/**
* drm_atomic_get_existing_crtc_state - get CRTC state, if it exists
* @state: global atomic state object
--
2.7.4
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti <[email protected]>
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
---
drivers/gpu/drm/msm/dp/dp_display.c | 9 ++++++---
drivers/gpu/drm/msm/dp/dp_drm.c | 6 +++---
drivers/gpu/drm/msm/dp/dp_drm.h | 9 ++++++---
3 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index bde1a7c..985287e 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -1652,7 +1652,8 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
return 0;
}
-void dp_bridge_enable(struct drm_bridge *drm_bridge)
+void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
@@ -1707,7 +1708,8 @@ void dp_bridge_enable(struct drm_bridge *drm_bridge)
mutex_unlock(&dp_display->event_mutex);
}
-void dp_bridge_disable(struct drm_bridge *drm_bridge)
+void dp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
@@ -1718,7 +1720,8 @@ void dp_bridge_disable(struct drm_bridge *drm_bridge)
dp_ctrl_push_idle(dp_display->ctrl);
}
-void dp_bridge_post_disable(struct drm_bridge *drm_bridge)
+void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 275370f..3252d50 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -94,9 +94,9 @@ static const struct drm_bridge_funcs dp_bridge_ops = {
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
.atomic_reset = drm_atomic_helper_bridge_reset,
- .enable = dp_bridge_enable,
- .disable = dp_bridge_disable,
- .post_disable = dp_bridge_post_disable,
+ .atomic_enable = dp_bridge_atomic_enable,
+ .atomic_disable = dp_bridge_atomic_disable,
+ .atomic_post_disable = dp_bridge_atomic_post_disable,
.mode_set = dp_bridge_mode_set,
.mode_valid = dp_bridge_mode_valid,
.get_modes = dp_bridge_get_modes,
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h
index 250f7c6..afe79b8 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.h
+++ b/drivers/gpu/drm/msm/dp/dp_drm.h
@@ -23,9 +23,12 @@ struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct dr
struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
struct drm_encoder *encoder);
-void dp_bridge_enable(struct drm_bridge *drm_bridge);
-void dp_bridge_disable(struct drm_bridge *drm_bridge);
-void dp_bridge_post_disable(struct drm_bridge *drm_bridge);
+void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state);
+void dp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state);
+void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state);
enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge,
const struct drm_display_info *info,
const struct drm_display_mode *mode);
--
2.7.4
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti <[email protected]>
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 80 ++++++++++++++++++++++
drivers/gpu/drm/msm/dp/dp_catalog.h | 4 ++
drivers/gpu/drm/msm/dp/dp_ctrl.c | 80 ++++++++++++++++++++++
drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +
drivers/gpu/drm/msm/dp/dp_display.c | 19 ++++++
drivers/gpu/drm/msm/dp/dp_display.h | 2 +
drivers/gpu/drm/msm/dp/dp_drm.c | 133 +++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/msm/dp/dp_link.c | 36 ++++++++++
drivers/gpu/drm/msm/dp/dp_panel.c | 22 ++++++
drivers/gpu/drm/msm/dp/dp_panel.h | 6 ++
drivers/gpu/drm/msm/dp/dp_reg.h | 27 ++++++++
11 files changed, 411 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 676279d..c12a5d9 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -47,6 +47,14 @@
#define DP_INTERRUPT_STATUS2_MASK \
(DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT)
+#define DP_INTERRUPT_STATUS4 \
+ (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \
+ PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT)
+
+#define DP_INTERRUPT_MASK4 \
+ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \
+ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK)
+
struct dp_catalog_private {
struct device *dev;
struct drm_device *drm_dev;
@@ -359,6 +367,23 @@ void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog)
ln_mapping);
}
+void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog,
+ bool enable)
+{
+ u32 val;
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+
+ val = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
+
+ if (enable)
+ val |= DP_MAINLINK_CTRL_ENABLE;
+ else
+ val &= ~DP_MAINLINK_CTRL_ENABLE;
+
+ dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val);
+}
+
void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog,
bool enable)
{
@@ -610,6 +635,47 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog)
dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
}
+static void dp_catalog_enable_sdp(struct dp_catalog_private *catalog)
+{
+ /* trigger sdp */
+ dp_write_link(catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP);
+ dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0);
+}
+
+void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 config;
+
+ /* enable PSR1 function */
+ config = dp_read_link(catalog, REG_PSR_CONFIG);
+ config |= PSR1_SUPPORTED;
+ dp_write_link(catalog, REG_PSR_CONFIG, config);
+
+ dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4);
+ dp_catalog_enable_sdp(catalog);
+}
+
+void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 cmd;
+
+ cmd = dp_read_link(catalog, REG_PSR_CMD);
+
+ cmd &= ~(PSR_ENTER | PSR_EXIT);
+
+ if (enter)
+ cmd |= PSR_ENTER;
+ else
+ cmd |= PSR_EXIT;
+
+ dp_catalog_enable_sdp(catalog);
+ dp_write_link(catalog, REG_PSR_CMD, cmd);
+}
+
u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
@@ -645,6 +711,20 @@ u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
return isr & (mask | ~DP_DP_HPD_INT_MASK);
}
+u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 intr, intr_ack;
+
+ intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS4);
+ intr_ack = (intr & DP_INTERRUPT_STATUS4)
+ << DP_INTERRUPT_STATUS_ACK_SHIFT;
+ dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack);
+
+ return intr;
+}
+
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
index 1f717f4..2174bb5 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -93,6 +93,7 @@ void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config);
void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
+void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable);
void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
u32 stream_rate_khz, bool fixed_nvid);
@@ -104,12 +105,15 @@ void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);
void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
u32 intr_mask, bool en);
void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog);
+void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog);
+void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter);
u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog);
u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
u8 p_level);
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
+u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
u32 dp_tu, u32 valid_boundary,
u32 valid_boundary2);
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index dd26ca6..ea1c1f0 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -22,6 +22,7 @@
#define DP_KHZ_TO_HZ 1000
#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
+#define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */
#define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
#define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
@@ -80,6 +81,7 @@ struct dp_ctrl_private {
struct dp_catalog *catalog;
struct completion idle_comp;
+ struct completion psr_op_comp;
struct completion video_comp;
};
@@ -153,6 +155,9 @@ static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
+ if (ctrl->panel->psr_cap.version)
+ config |= DP_CONFIGURATION_CTRL_SEND_VSC;
+
dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
}
@@ -1375,6 +1380,64 @@ void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable)
dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
}
+void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl)
+{
+ u8 cfg;
+ struct dp_ctrl_private *ctrl = container_of(dp_ctrl,
+ struct dp_ctrl_private, dp_ctrl);
+
+ if (!ctrl->panel->psr_cap.version)
+ return;
+
+ dp_catalog_ctrl_config_psr(ctrl->catalog);
+
+ cfg = DP_PSR_ENABLE;
+ drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1);
+}
+
+void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter)
+{
+ struct dp_ctrl_private *ctrl = container_of(dp_ctrl,
+ struct dp_ctrl_private, dp_ctrl);
+
+ if (!ctrl->panel->psr_cap.version)
+ return;
+
+ /*
+ * When entering PSR,
+ * 1. Send PSR enter SDP and wait for the PSR_UPDATE_INT
+ * 2. Turn off video
+ * 3. Disable the mainlink
+ *
+ * When exiting PSR,
+ * 1. Enable the mainlink
+ * 2. Send the PSR exit SDP
+ */
+ if (enter) {
+ reinit_completion(&ctrl->psr_op_comp);
+ dp_catalog_ctrl_set_psr(ctrl->catalog, true);
+
+ if (!wait_for_completion_timeout(&ctrl->psr_op_comp,
+ PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) {
+ DRM_ERROR("PSR_ENTRY timedout\n");
+ dp_catalog_ctrl_set_psr(ctrl->catalog, false);
+ return;
+ }
+
+ dp_ctrl_push_idle(dp_ctrl);
+ dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
+
+ dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false);
+ } else {
+ dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true);
+
+ dp_catalog_ctrl_set_psr(ctrl->catalog, false);
+ dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
+ dp_ctrl_wait4video_ready(ctrl);
+ dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
+ }
+}
+
void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
{
struct dp_ctrl_private *ctrl;
@@ -1989,6 +2052,22 @@ void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+ if (ctrl->panel->psr_cap.version) {
+ isr = dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog);
+
+ if (isr)
+ complete(&ctrl->psr_op_comp);
+
+ if (isr & PSR_EXIT_INT)
+ drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n");
+
+ if (isr & PSR_UPDATE_INT)
+ drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n");
+
+ if (isr & PSR_CAPTURE_INT)
+ drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n");
+ }
+
isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
@@ -2035,6 +2114,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
dev_err(dev, "failed to add DP OPP table\n");
init_completion(&ctrl->idle_comp);
+ init_completion(&ctrl->psr_op_comp);
init_completion(&ctrl->video_comp);
/* in parameters */
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index 9f29734..b226683 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -37,4 +37,7 @@ void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl);
void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl);
void dp_ctrl_irq_phy_exit(struct dp_ctrl *dp_ctrl);
+void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enable);
+void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl);
+
#endif /* _DP_CTRL_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 985287e..86ed80c 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -406,6 +406,8 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp)
edid = dp->panel->edid;
+ dp->dp_display.psr_supported = dp->panel->psr_cap.version;
+
dp->audio_supported = drm_detect_monitor_audio(edid);
dp_panel_handle_sink_request(dp->panel);
@@ -910,6 +912,10 @@ static int dp_display_post_enable(struct msm_dp *dp_display)
/* signal the connect event late to synchronize video and display */
dp_display_handle_plugged_change(dp_display, true);
+
+ if (dp_display->psr_supported)
+ dp_ctrl_config_psr(dp->ctrl);
+
return 0;
}
@@ -1104,6 +1110,19 @@ static void dp_display_config_hpd(struct dp_display_private *dp)
enable_irq(dp->irq);
}
+void dp_display_set_psr(struct msm_dp *dp_display, bool enter)
+{
+ struct dp_display_private *dp;
+
+ if (!dp_display) {
+ DRM_ERROR("invalid params\n");
+ return;
+ }
+
+ dp = container_of(dp_display, struct dp_display_private, dp_display);
+ dp_ctrl_set_psr(dp->ctrl, enter);
+}
+
static int hpd_event_thread(void *data)
{
struct dp_display_private *dp_priv;
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h
index 371337d..1e9415a 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -29,6 +29,7 @@ struct msm_dp {
u32 max_dp_lanes;
struct dp_audio *dp_audio;
+ bool psr_supported;
};
int dp_display_set_plugged_cb(struct msm_dp *dp_display,
@@ -39,5 +40,6 @@ bool dp_display_check_video_test(struct msm_dp *dp_display);
int dp_display_get_test_bpp(struct msm_dp *dp_display);
void dp_display_signal_audio_start(struct msm_dp *dp_display);
void dp_display_signal_audio_complete(struct msm_dp *dp_display);
+void dp_display_set_psr(struct msm_dp *dp, bool enter);
#endif /* _DP_DISPLAY_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 3252d50..3b38bd9 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -107,6 +107,137 @@ static const struct drm_bridge_funcs dp_bridge_ops = {
.hpd_notify = dp_bridge_hpd_notify,
};
+static int edp_bridge_atomic_check(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct msm_dp *dp = to_dp_bridge(drm_bridge)->dp_display;
+
+ if (WARN_ON(!conn_state))
+ return -ENODEV;
+
+ if (!conn_state->crtc || !crtc_state)
+ return 0;
+
+ if (crtc_state->self_refresh_active && !dp->psr_supported)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void edp_bridge_atomic_enable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_crtc_state;
+ struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
+ struct msm_dp *dp = dp_bridge->dp_display;
+
+ /*
+ * Check the old state of the crtc to determine if the panel
+ * was put into psr state previously by the edp_bridge_atomic_disable.
+ * If the panel is in psr, just exit psr state and skip the full
+ * bridge enable sequence.
+ */
+ crtc = drm_atomic_get_new_crtc_for_encoder(atomic_state,
+ drm_bridge->encoder);
+ if (!crtc)
+ return;
+
+ old_crtc_state = drm_atomic_get_old_crtc_state(atomic_state, crtc);
+
+ if (old_crtc_state && old_crtc_state->self_refresh_active) {
+ dp_display_set_psr(dp, false);
+ return;
+ }
+
+ dp_bridge_atomic_enable(drm_bridge, old_bridge_state);
+}
+
+static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *new_crtc_state = NULL, *old_crtc_state = NULL;
+ struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
+ struct msm_dp *dp = dp_bridge->dp_display;
+
+ crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state,
+ drm_bridge->encoder);
+ if (!crtc)
+ goto out;
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(atomic_state, crtc);
+ if (!new_crtc_state)
+ goto out;
+
+ old_crtc_state = drm_atomic_get_old_crtc_state(atomic_state, crtc);
+ if (!old_crtc_state)
+ goto out;
+
+ /*
+ * Set self refresh mode if current crtc state is active.
+ *
+ * If old crtc state is active, then this is a display disable
+ * call while the sink is in psr state. So, exit psr here.
+ * The eDP controller will be disabled in the
+ * edp_bridge_atomic_post_disable function.
+ *
+ * We observed sink is stuck in self refresh if psr exit is skipped
+ * when display disable occurs while the sink is in psr state.
+ */
+ if (new_crtc_state->self_refresh_active) {
+ dp_display_set_psr(dp, true);
+ return;
+ } else if (old_crtc_state->self_refresh_active) {
+ dp_display_set_psr(dp, false);
+ return;
+ }
+
+out:
+ dp_bridge_atomic_disable(drm_bridge, old_bridge_state);
+}
+
+static void edp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *new_crtc_state = NULL;
+
+ crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state,
+ drm_bridge->encoder);
+ if (!crtc)
+ return;
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(atomic_state, crtc);
+ if (!new_crtc_state)
+ return;
+
+ /*
+ * Self refresh mode is already set in edp_bridge_atomic_disable.
+ */
+ if (new_crtc_state->self_refresh_active)
+ return;
+
+ dp_bridge_atomic_post_disable(drm_bridge, old_bridge_state);
+}
+
+static const struct drm_bridge_funcs edp_bridge_ops = {
+ .atomic_enable = edp_bridge_atomic_enable,
+ .atomic_disable = edp_bridge_atomic_disable,
+ .atomic_post_disable = edp_bridge_atomic_post_disable,
+ .mode_set = dp_bridge_mode_set,
+ .mode_valid = dp_bridge_mode_valid,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_check = edp_bridge_atomic_check,
+};
+
struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
struct drm_encoder *encoder)
{
@@ -121,7 +252,7 @@ struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *
dp_bridge->dp_display = dp_display;
bridge = &dp_bridge->bridge;
- bridge->funcs = &dp_bridge_ops;
+ bridge->funcs = dp_display->is_edp ? &edp_bridge_ops : &dp_bridge_ops;
bridge->type = dp_display->connector_type;
/*
diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
index f1f1d64..5a4817a 100644
--- a/drivers/gpu/drm/msm/dp/dp_link.c
+++ b/drivers/gpu/drm/msm/dp/dp_link.c
@@ -937,6 +937,38 @@ static int dp_link_process_phy_test_pattern_request(
return 0;
}
+static bool dp_link_read_psr_error_status(struct dp_link_private *link)
+{
+ u8 status;
+
+ drm_dp_dpcd_read(link->aux, DP_PSR_ERROR_STATUS, &status, 1);
+
+ if (status & DP_PSR_LINK_CRC_ERROR)
+ DRM_ERROR("PSR LINK CRC ERROR\n");
+ else if (status & DP_PSR_RFB_STORAGE_ERROR)
+ DRM_ERROR("PSR RFB STORAGE ERROR\n");
+ else if (status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
+ DRM_ERROR("PSR VSC SDP UNCORRECTABLE ERROR\n");
+ else
+ return false;
+
+ return true;
+}
+
+static bool dp_link_psr_capability_changed(struct dp_link_private *link)
+{
+ u8 status;
+
+ drm_dp_dpcd_read(link->aux, DP_PSR_ESI, &status, 1);
+
+ if (status & DP_PSR_CAPS_CHANGE) {
+ drm_dbg_dp(link->drm_dev, "PSR Capability Change\n");
+ return true;
+ }
+
+ return false;
+}
+
static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
{
return link_status[r - DP_LANE0_1_STATUS];
@@ -1055,6 +1087,10 @@ int dp_link_process_request(struct dp_link *dp_link)
dp_link->sink_request |= DP_TEST_LINK_TRAINING;
} else if (!dp_link_process_phy_test_pattern_request(link)) {
dp_link->sink_request |= DP_TEST_LINK_PHY_TEST_PATTERN;
+ } else if (dp_link_read_psr_error_status(link)) {
+ DRM_ERROR("PSR IRQ_HPD received\n");
+ } else if (dp_link_psr_capability_changed(link)) {
+ drm_dbg_dp(link->drm_dev, "PSR Capabiity changed");
} else {
ret = dp_link_process_link_status_update(link);
if (!ret) {
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index 1800d89..42d5251 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -20,6 +20,27 @@ struct dp_panel_private {
bool aux_cfg_update_done;
};
+static void dp_panel_read_psr_cap(struct dp_panel_private *panel)
+{
+ ssize_t rlen;
+ struct dp_panel *dp_panel;
+
+ dp_panel = &panel->dp_panel;
+
+ /* edp sink */
+ if (dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {
+ rlen = drm_dp_dpcd_read(panel->aux, DP_PSR_SUPPORT,
+ &dp_panel->psr_cap, sizeof(dp_panel->psr_cap));
+ if (rlen == sizeof(dp_panel->psr_cap)) {
+ drm_dbg_dp(panel->drm_dev,
+ "psr version: 0x%x, psr_cap: 0x%x\n",
+ dp_panel->psr_cap.version,
+ dp_panel->psr_cap.capabilities);
+ } else
+ DRM_ERROR("failed to read psr info, rlen=%zd\n", rlen);
+ }
+}
+
static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
{
int rc = 0;
@@ -107,6 +128,7 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
}
}
+ dp_panel_read_psr_cap(panel);
end:
return rc;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h
index f04d021..45208b4 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -34,6 +34,11 @@ struct dp_panel_in {
struct dp_catalog *catalog;
};
+struct dp_panel_psr {
+ u8 version;
+ u8 capabilities;
+};
+
struct dp_panel {
/* dpcd raw data */
u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
@@ -46,6 +51,7 @@ struct dp_panel {
struct edid *edid;
struct drm_connector *connector;
struct dp_display_mode dp_mode;
+ struct dp_panel_psr psr_cap;
bool video_test;
u32 vic;
diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
index 2686028..ea85a69 100644
--- a/drivers/gpu/drm/msm/dp/dp_reg.h
+++ b/drivers/gpu/drm/msm/dp/dp_reg.h
@@ -22,6 +22,20 @@
#define REG_DP_INTR_STATUS2 (0x00000024)
#define REG_DP_INTR_STATUS3 (0x00000028)
+#define REG_DP_INTR_STATUS4 (0x0000002C)
+#define PSR_UPDATE_INT (0x00000001)
+#define PSR_CAPTURE_INT (0x00000004)
+#define PSR_EXIT_INT (0x00000010)
+#define PSR_UPDATE_ERROR_INT (0x00000040)
+#define PSR_WAKE_ERROR_INT (0x00000100)
+
+#define REG_DP_INTR_MASK4 (0x00000030)
+#define PSR_UPDATE_MASK (0x00000001)
+#define PSR_CAPTURE_MASK (0x00000002)
+#define PSR_EXIT_MASK (0x00000004)
+#define PSR_UPDATE_ERROR_MASK (0x00000008)
+#define PSR_WAKE_ERROR_MASK (0x00000010)
+
#define REG_DP_DP_HPD_CTRL (0x00000000)
#define DP_DP_HPD_CTRL_HPD_EN (0x00000001)
@@ -164,6 +178,16 @@
#define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094)
#define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098)
+#define REG_PSR_CONFIG (0x00000100)
+#define DISABLE_PSR (0x00000000)
+#define PSR1_SUPPORTED (0x00000001)
+#define PSR2_WITHOUT_FRAMESYNC (0x00000002)
+#define PSR2_WITH_FRAMESYNC (0x00000003)
+
+#define REG_PSR_CMD (0x00000110)
+#define PSR_ENTER (0x00000001)
+#define PSR_EXIT (0x00000002)
+
#define MMSS_DP_PSR_CRC_RG (0x00000154)
#define MMSS_DP_PSR_CRC_B (0x00000158)
@@ -184,6 +208,9 @@
#define MMSS_DP_AUDIO_STREAM_0 (0x00000240)
#define MMSS_DP_AUDIO_STREAM_1 (0x00000244)
+#define MMSS_DP_SDP_CFG3 (0x0000024c)
+#define UPDATE_SDP (0x00000001)
+
#define MMSS_DP_EXTENSION_0 (0x00000250)
#define MMSS_DP_EXTENSION_1 (0x00000254)
#define MMSS_DP_EXTENSION_2 (0x00000258)
--
2.7.4
The eDP and DP interfaces shared the bridge operations and
the eDP specific changes were implemented under is_edp check.
To add psr support for eDP, we started using a new set of eDP
bridge ops. We are moving the eDP specific code in the
dp_bridge_mode_valid function to a new eDP function,
edp_bridge_mode_valid under the eDP bridge ops.
Signed-off-by: Sankeerth Billakanti <[email protected]>
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/dp/dp_display.c | 8 --------
drivers/gpu/drm/msm/dp/dp_drm.c | 34 +++++++++++++++++++++++++++++++++-
2 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 86ed80c..ffb21a6 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -996,14 +996,6 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge,
return -EINVAL;
}
- /*
- * The eDP controller currently does not have a reliable way of
- * enabling panel power to read sink capabilities. So, we rely
- * on the panel driver to populate only supported modes for now.
- */
- if (dp->is_edp)
- return MODE_OK;
-
if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
return MODE_CLOCK_HIGH;
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 3b38bd9..029e08c 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -226,12 +226,44 @@ static void edp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge,
dp_bridge_atomic_post_disable(drm_bridge, old_bridge_state);
}
+/**
+ * edp_bridge_mode_valid - callback to determine if specified mode is valid
+ * @bridge: Pointer to drm bridge structure
+ * @info: display info
+ * @mode: Pointer to drm mode structure
+ * Returns: Validity status for specified mode
+ */
+static enum drm_mode_status edp_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ struct msm_dp *dp;
+ int mode_pclk_khz = mode->clock;
+
+ dp = to_dp_bridge(bridge)->dp_display;
+
+ if (!dp || !mode_pclk_khz || !dp->connector) {
+ DRM_ERROR("invalid params\n");
+ return -EINVAL;
+ }
+
+ if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
+ return MODE_CLOCK_HIGH;
+
+ /*
+ * The eDP controller currently does not have a reliable way of
+ * enabling panel power to read sink capabilities. So, we rely
+ * on the panel driver to populate only supported modes for now.
+ */
+ return MODE_OK;
+}
+
static const struct drm_bridge_funcs edp_bridge_ops = {
.atomic_enable = edp_bridge_atomic_enable,
.atomic_disable = edp_bridge_atomic_disable,
.atomic_post_disable = edp_bridge_atomic_post_disable,
.mode_set = dp_bridge_mode_set,
- .mode_valid = dp_bridge_mode_valid,
+ .mode_valid = edp_bridge_mode_valid,
.atomic_reset = drm_atomic_helper_bridge_reset,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
--
2.7.4
From: Sankeerth Billakanti <[email protected]>
Updated frames get queued if self_refresh_aware is set when the
sink is in psr. To support bridge enable and avoid queuing of update
frames, reset the self_refresh_aware state after entering psr.
Signed-off-by: Sankeerth Billakanti <[email protected]>
Signed-off-by: Vinod Polimera <[email protected]>
---
drivers/gpu/drm/msm/dp/dp_drm.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 029e08c..01ca148b 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -134,6 +134,8 @@ static void edp_bridge_atomic_enable(struct drm_bridge *drm_bridge,
struct drm_crtc_state *old_crtc_state;
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state = NULL;
/*
* Check the old state of the crtc to determine if the panel
@@ -150,10 +152,20 @@ static void edp_bridge_atomic_enable(struct drm_bridge *drm_bridge,
if (old_crtc_state && old_crtc_state->self_refresh_active) {
dp_display_set_psr(dp, false);
- return;
+ goto psr_aware;
}
dp_bridge_atomic_enable(drm_bridge, old_bridge_state);
+
+psr_aware:
+ connector = drm_atomic_get_new_connector_for_encoder(atomic_state,
+ drm_bridge->encoder);
+ if (connector)
+ conn_state = drm_atomic_get_new_connector_state(atomic_state,
+ connector);
+
+ if (conn_state)
+ conn_state->self_refresh_aware = dp->psr_supported;
}
static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
@@ -164,6 +176,14 @@ static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
struct drm_crtc_state *new_crtc_state = NULL, *old_crtc_state = NULL;
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state = NULL;
+
+ connector = drm_atomic_get_old_connector_for_encoder(atomic_state,
+ drm_bridge->encoder);
+ if (connector)
+ conn_state = drm_atomic_get_new_connector_state(atomic_state,
+ connector);
crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state,
drm_bridge->encoder);
@@ -190,6 +210,9 @@ static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
* when display disable occurs while the sink is in psr state.
*/
if (new_crtc_state->self_refresh_active) {
+ if (conn_state)
+ conn_state->self_refresh_aware = false;
+
dp_display_set_psr(dp, true);
return;
} else if (old_crtc_state->self_refresh_active) {
--
2.7.4
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti <[email protected]>
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Daniel Vetter <[email protected]>
---
drivers/gpu/drm/bridge/panel.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index e8aae3c..04e9fb0 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -109,28 +109,32 @@ static void panel_bridge_detach(struct drm_bridge *bridge)
drm_connector_cleanup(connector);
}
-static void panel_bridge_pre_enable(struct drm_bridge *bridge)
+static void panel_bridge_atomic_pre_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
drm_panel_prepare(panel_bridge->panel);
}
-static void panel_bridge_enable(struct drm_bridge *bridge)
+static void panel_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
drm_panel_enable(panel_bridge->panel);
}
-static void panel_bridge_disable(struct drm_bridge *bridge)
+static void panel_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
drm_panel_disable(panel_bridge->panel);
}
-static void panel_bridge_post_disable(struct drm_bridge *bridge)
+static void panel_bridge_atomic_post_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
@@ -159,10 +163,10 @@ static void panel_bridge_debugfs_init(struct drm_bridge *bridge,
static const struct drm_bridge_funcs panel_bridge_bridge_funcs = {
.attach = panel_bridge_attach,
.detach = panel_bridge_detach,
- .pre_enable = panel_bridge_pre_enable,
- .enable = panel_bridge_enable,
- .disable = panel_bridge_disable,
- .post_disable = panel_bridge_post_disable,
+ .atomic_pre_enable = panel_bridge_atomic_pre_enable,
+ .atomic_enable = panel_bridge_atomic_enable,
+ .atomic_disable = panel_bridge_atomic_disable,
+ .atomic_post_disable = panel_bridge_atomic_post_disable,
.get_modes = panel_bridge_get_modes,
.atomic_reset = drm_atomic_helper_bridge_reset,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
--
2.7.4
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti <[email protected]>
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Daniel Vetter <[email protected]>
---
drivers/gpu/drm/bridge/panel.c | 48 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index 04e9fb0..a2c6f30 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -113,6 +113,18 @@ static void panel_bridge_atomic_pre_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_crtc_state;
+
+ crtc = drm_atomic_get_new_crtc_for_encoder(atomic_state, encoder);
+ if (!crtc)
+ return;
+
+ old_crtc_state = drm_atomic_get_old_crtc_state(atomic_state, crtc);
+ if (old_crtc_state && old_crtc_state->self_refresh_active)
+ return;
drm_panel_prepare(panel_bridge->panel);
}
@@ -121,6 +133,18 @@ static void panel_bridge_atomic_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_crtc_state;
+
+ crtc = drm_atomic_get_new_crtc_for_encoder(atomic_state, encoder);
+ if (!crtc)
+ return;
+
+ old_crtc_state = drm_atomic_get_old_crtc_state(atomic_state, crtc);
+ if (old_crtc_state && old_crtc_state->self_refresh_active)
+ return;
drm_panel_enable(panel_bridge->panel);
}
@@ -129,6 +153,18 @@ static void panel_bridge_atomic_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *new_crtc_state;
+
+ crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state, encoder);
+ if (!crtc)
+ return;
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(atomic_state, crtc);
+ if (new_crtc_state && new_crtc_state->self_refresh_active)
+ return;
drm_panel_disable(panel_bridge->panel);
}
@@ -137,6 +173,18 @@ static void panel_bridge_atomic_post_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *new_crtc_state;
+
+ crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state, encoder);
+ if (!crtc)
+ return;
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(atomic_state, crtc);
+ if (new_crtc_state && new_crtc_state->self_refresh_active)
+ return;
drm_panel_unprepare(panel_bridge->panel);
}
--
2.7.4
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota <[email protected]>
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index c237003..01b7509 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1171,7 +1171,8 @@ void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
mutex_unlock(&dpu_enc->enc_lock);
}
-static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
+static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
+ struct drm_atomic_state *state)
{
struct dpu_encoder_virt *dpu_enc = NULL;
int ret = 0;
@@ -1207,7 +1208,8 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
mutex_unlock(&dpu_enc->enc_lock);
}
-static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
+static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
+ struct drm_atomic_state *state)
{
struct dpu_encoder_virt *dpu_enc = NULL;
int i = 0;
@@ -2388,8 +2390,8 @@ static void dpu_encoder_frame_done_timeout(struct timer_list *t)
static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
.atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
- .disable = dpu_encoder_virt_disable,
- .enable = dpu_encoder_virt_enable,
+ .atomic_disable = dpu_encoder_virt_atomic_disable,
+ .atomic_enable = dpu_encoder_virt_atomic_enable,
.atomic_check = dpu_encoder_virt_atomic_check,
};
--
2.7.4
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota <[email protected]>
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 ++++++++++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
3 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index f29a339..60e5984 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -21,6 +21,7 @@
#include <drm/drm_probe_helper.h>
#include <drm/drm_rect.h>
#include <drm/drm_vblank.h>
+#include <drm/drm_self_refresh_helper.h>
#include "dpu_kms.h"
#include "dpu_hw_lm.h"
@@ -1021,6 +1022,9 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
+ if (old_crtc_state->self_refresh_active)
+ return;
+
/* Disable/save vblank irq handling */
drm_crtc_vblank_off(crtc);
@@ -1577,7 +1581,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
{
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
- int i;
+ int i, ret;
dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
if (!dpu_crtc)
@@ -1614,6 +1618,13 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
/* initialize event handling */
spin_lock_init(&dpu_crtc->event_lock);
+ ret = drm_self_refresh_helper_init(crtc);
+ if (ret) {
+ DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n",
+ crtc->name, ret);
+ return ERR_PTR(ret);
+ }
+
DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
return crtc;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 01b7509..450abb1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -12,6 +12,7 @@
#include <linux/kthread.h>
#include <linux/seq_file.h>
+#include <drm/drm_atomic.h>
#include <drm/drm_crtc.h>
#include <drm/drm_file.h>
#include <drm/drm_probe_helper.h>
@@ -1212,11 +1213,24 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
struct drm_atomic_state *state)
{
struct dpu_encoder_virt *dpu_enc = NULL;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_state = NULL;
int i = 0;
dpu_enc = to_dpu_encoder_virt(drm_enc);
DPU_DEBUG_ENC(dpu_enc, "\n");
+ crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
+ if (crtc)
+ old_state = drm_atomic_get_old_crtc_state(state, crtc);
+
+ /*
+ * The encoder is already disabled if self refresh mode was set earlier,
+ * in the old_state for the corresponding crtc.
+ */
+ if (old_state && old_state->self_refresh_active)
+ return;
+
mutex_lock(&dpu_enc->enc_lock);
dpu_enc->enabled = false;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index a683bd9..681dd2e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -491,7 +491,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
return;
}
- if (!crtc->state->active) {
+ if (!drm_atomic_crtc_effectively_active(crtc->state)) {
DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
return;
}
--
2.7.4
Populate the enocder software structure to reflect the updated
crtc appropriately during crtc enable/disable for a new commit
while taking care of the self refresh transitions when crtc
disable is triggered from the drm self refresh library.
Signed-off-by: Vinod Polimera <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 29 +++++++++++++++++++++++++----
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 60e5984..b1ec0c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1022,8 +1022,17 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
- if (old_crtc_state->self_refresh_active)
+ /* If disable is triggered while in self refresh mode,
+ * reset the encoder software state so that in enable
+ * it won't trigger a warn while assigning crtc.
+ */
+ if (old_crtc_state->self_refresh_active) {
+ drm_for_each_encoder_mask(encoder, crtc->dev,
+ old_crtc_state->encoder_mask) {
+ dpu_encoder_assign_crtc(encoder, NULL);
+ }
return;
+ }
/* Disable/save vblank irq handling */
drm_crtc_vblank_off(crtc);
@@ -1036,7 +1045,14 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
*/
if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
release_bandwidth = true;
- dpu_encoder_assign_crtc(encoder, NULL);
+
+ /*
+ * If disable is triggered during psr active(e.g: screen dim in PSR),
+ * we will need encoder->crtc connection to process the device sleep &
+ * preserve it during psr sequence.
+ */
+ if (!crtc->state->self_refresh_active)
+ dpu_encoder_assign_crtc(encoder, NULL);
}
/* wait for frame_event_done completion */
@@ -1084,6 +1100,9 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct drm_encoder *encoder;
bool request_bandwidth = false;
+ struct drm_crtc_state *old_crtc_state;
+
+ old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
pm_runtime_get_sync(crtc->dev->dev);
@@ -1106,8 +1125,10 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
dpu_crtc->enabled = true;
- drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
- dpu_encoder_assign_crtc(encoder, crtc);
+ if (!old_crtc_state->self_refresh_active) {
+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
+ dpu_encoder_assign_crtc(encoder, crtc);
+ }
/* Enable/restore vblank irq handling */
drm_crtc_vblank_on(crtc);
--
2.7.4
On 30/01/2023 17:11, Vinod Polimera wrote:
> Recommended way of reading the interface timing gen status is via
> status register. Timing gen status register will give a reliable status
> of the interface especially during ON/OFF transitions. This support was
> added from DPU version 5.0.0.
>
> Signed-off-by: Vinod Polimera <[email protected]>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ++++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +++++++-----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +++++++-
> 3 files changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index cf053e8..ce6e9e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -78,9 +78,11 @@
>
> #define INTF_SDM845_MASK (0)
>
> -#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
> +#define INTF_SC7180_MASK \
> + (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED))
>
> -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
> +#define INTF_SC7280_MASK \
> + (INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN))
Not necessary anymore.
With that fixed:
Reviewed-by: Dmitry Baryshkov <[email protected]>
>
> #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> BIT(MDP_SSPP_TOP0_INTR2) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index ddab9ca..08cd1a1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -213,17 +213,19 @@ enum {
>
> /**
> * INTF sub-blocks
> - * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
> - * pixel data arrives to this INTF
> - * @DPU_INTF_TE INTF block has TE configuration support
> - * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
> - than video timing
> + * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
> + * pixel data arrives to this INTF
> + * @DPU_INTF_TE INTF block has TE configuration support
> + * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
> + * than video timing
> + * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
> * @DPU_INTF_MAX
> */
> enum {
> DPU_INTF_INPUT_CTRL = 0x1,
> DPU_INTF_TE,
> DPU_DATA_HCTL_EN,
> + DPU_INTF_STATUS_SUPPORTED,
> DPU_INTF_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 7ce66bf..84ee2ef 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -62,6 +62,7 @@
> #define INTF_LINE_COUNT 0x0B0
>
> #define INTF_MUX 0x25C
> +#define INTF_STATUS 0x26C
>
> #define INTF_CFG_ACTIVE_H_EN BIT(29)
> #define INTF_CFG_ACTIVE_V_EN BIT(30)
> @@ -297,8 +298,13 @@ static void dpu_hw_intf_get_status(
> struct intf_status *s)
> {
> struct dpu_hw_blk_reg_map *c = &intf->hw;
> + unsigned long cap = intf->cap->features;
> +
> + if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))
> + s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);
> + else
> + s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
>
> - s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
> s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31));
> if (s->is_en) {
> s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
--
With best wishes
Dmitry
On 30/01/2023 17:11, Vinod Polimera wrote:
> Changes in v2:
> - Use dp bridge to set psr entry/exit instead of dpu_enocder.
> - Don't modify whitespaces.
> - Set self refresh aware from atomic_check.
> - Set self refresh aware only if psr is supported.
> - Provide a stub for msm_dp_display_set_psr.
> - Move dp functions to bridge code.
>
> Changes in v3:
> - Change callback names to reflect atomic interfaces.
> - Move bridge callback change to separate patch as suggested by Dmitry.
> - Remove psr function declaration from msm_drv.h.
> - Set self_refresh_aware flag only if psr is supported.
> - Modify the variable names to simpler form.
> - Define bit fields for PSR settings.
> - Add comments explaining the steps to enter/exit psr.
> - Change DRM_INFO to drm_dbg_db.
>
> Changes in v4:
> - Move the get crtc functions to drm_atomic.
> - Add atomic functions for DP bridge too.
> - Add ternary operator to choose eDP or DP ops.
> - Return true/false instead of 1/0.
> - mode_valid missing in the eDP bridge ops.
> - Move the functions to get crtc into drm_atomic.c.
> - Fix compilation issues.
> - Remove dpu_assign_crtc and get crtc from drm_enc instead of dpu_enc.
> - Check for crtc state enable while reserving resources.
>
> Changes in v5:
> - Move the mode_valid changes into a different patch.
> - Complete psr_op_comp only when isr is set.
> - Move the DP atomic callback changes to a different patch.
> - Get crtc from drm connector state crtc.
> - Move to separate patch for check for crtc state enable while
> reserving resources.
>
> Changes in v6:
> - Remove crtc from dpu_encoder_virt struct.
> - fix crtc check during vblank toggle crtc.
> - Misc changes.
>
> Changes in v7:
> - Add fix for underrun issue on kasan build.
>
> Changes in v8:
> - Drop the enc spinlock as it won't serve any purpose in
> protetcing conn state.(Dmitry/Doug)
>
> Changes in v9:
> - Update commit message and fix alignment using spaces.(Marijn)
> - Misc changes.(Marijn)
>
> Changes in v10:
> - Get crtc cached in dpu_enc during obj init.(Dmitry)
>
> Changes in v11:
> - Remove crtc cached in dpu_enc during obj init.
> - Update dpu_enc crtc state on crtc enable/disable during self refresh.
>
> Changes in v12:
> - Update sc7180 intf mask to get intf timing gen status
> based on DPU_INTF_STATUS_SUPPORTED bit.(Dmitry)
> - Remove "clear active interface in the datapath cleanup" change
> as it is already included.
> - Move core changes to top of the series.(Dmitry)
Unfortunately they still are not at the top.
>
> Sankeerth Billakanti (1):
> drm/msm/dp: disable self_refresh_aware after entering psr
>
> Vinod Polimera (13):
> drm/msm/disp/dpu: check for crtc enable rather than crtc active to
> release shared resources
> drm/msm/disp/dpu: get timing engine status from intf status register
> drm/msm/disp/dpu: wait for extra vsync till timing engine status is
> disabled
> drm/msm/disp/dpu: reset the datapath after timing engine disable
> drm: add helper functions to retrieve old and new crtc
> drm/msm/dp: use atomic callbacks for DP bridge ops
> drm/msm/dp: Add basic PSR support for eDP
> drm/msm/dp: use the eDP bridge ops to validate eDP modes
> drm/bridge: use atomic enable/disable callbacks for panel bridge
> drm/bridge: add psr support for panel bridge callbacks
> drm/msm/disp/dpu: use atomic enable/disable callbacks for encoder
> functions
> drm/msm/disp/dpu: add PSR support for eDP interface in dpu driver
> drm/msm/disp/dpu: update dpu_enc crtc state on crtc enable/disable
> during self refresh
>
> drivers/gpu/drm/bridge/panel.c | 68 +++++++-
> drivers/gpu/drm/drm_atomic.c | 60 +++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 40 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 ++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 22 +++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> drivers/gpu/drm/msm/dp/dp_catalog.c | 80 +++++++++
> drivers/gpu/drm/msm/dp/dp_catalog.h | 4 +
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 80 +++++++++
> drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +
> drivers/gpu/drm/msm/dp/dp_display.c | 36 ++--
> drivers/gpu/drm/msm/dp/dp_display.h | 2 +
> drivers/gpu/drm/msm/dp/dp_drm.c | 194 ++++++++++++++++++++-
> drivers/gpu/drm/msm/dp/dp_drm.h | 9 +-
> drivers/gpu/drm/msm/dp/dp_link.c | 36 ++++
> drivers/gpu/drm/msm/dp/dp_panel.c | 22 +++
> drivers/gpu/drm/msm/dp/dp_panel.h | 6 +
> drivers/gpu/drm/msm/dp/dp_reg.h | 27 +++
> include/drm/drm_atomic.h | 7 +
> 22 files changed, 706 insertions(+), 44 deletions(-)
>
--
With best wishes
Dmitry
On 30/01/2023 17:11, Vinod Polimera wrote:
> From: Sankeerth Billakanti <[email protected]>
>
> Updated frames get queued if self_refresh_aware is set when the
> sink is in psr. To support bridge enable and avoid queuing of update
> frames, reset the self_refresh_aware state after entering psr.
>
> Signed-off-by: Sankeerth Billakanti <[email protected]>
> Signed-off-by: Vinod Polimera <[email protected]>
> ---
> drivers/gpu/drm/msm/dp/dp_drm.c | 25 ++++++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
As I stated in v11's discussion, I do not like the way this change plays
with the self_refresh_aware. Please find another way to work around the
timing issue (let's probably continue the discussion back in v11).
--
With best wishes
Dmitry
On 30/01/2023 17:11, Vinod Polimera wrote:
> Enable PSR on eDP interface using drm self-refresh librabry.
> This patch uses a trigger from self-refresh library to enter/exit
> into PSR, when there are no updates from framework.
>
> Signed-off-by: Kalyan Thota <[email protected]>
> Signed-off-by: Vinod Polimera <[email protected]>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 ++++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> 3 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index f29a339..60e5984 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -21,6 +21,7 @@
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_rect.h>
> #include <drm/drm_vblank.h>
> +#include <drm/drm_self_refresh_helper.h>
>
> #include "dpu_kms.h"
> #include "dpu_hw_lm.h"
> @@ -1021,6 +1022,9 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
>
> DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
>
> + if (old_crtc_state->self_refresh_active)
> + return;
> +
I have been looking at the crtc_needs_disable(). It explicitly mentions
that 'We also need to run through the crtc_funcs->disable() function
[..] if it's transitioning to self refresh mode...'. Don't we need to
perform some cleanup here (like disabling the vblank irq handling,
freeing the bandwidth, etc)?
> /* Disable/save vblank irq handling */
> drm_crtc_vblank_off(crtc);
>
> @@ -1577,7 +1581,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
> {
> struct drm_crtc *crtc = NULL;
> struct dpu_crtc *dpu_crtc = NULL;
> - int i;
> + int i, ret;
>
> dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
> if (!dpu_crtc)
> @@ -1614,6 +1618,13 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
> /* initialize event handling */
> spin_lock_init(&dpu_crtc->event_lock);
>
> + ret = drm_self_refresh_helper_init(crtc);
> + if (ret) {
> + DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n",
> + crtc->name, ret);
> + return ERR_PTR(ret);
> + }
> +
> DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
> return crtc;
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 01b7509..450abb1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -12,6 +12,7 @@
> #include <linux/kthread.h>
> #include <linux/seq_file.h>
>
> +#include <drm/drm_atomic.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_file.h>
> #include <drm/drm_probe_helper.h>
> @@ -1212,11 +1213,24 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
> struct drm_atomic_state *state)
> {
> struct dpu_encoder_virt *dpu_enc = NULL;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *old_state = NULL;
> int i = 0;
>
> dpu_enc = to_dpu_encoder_virt(drm_enc);
> DPU_DEBUG_ENC(dpu_enc, "\n");
>
> + crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
> + if (crtc)
> + old_state = drm_atomic_get_old_crtc_state(state, crtc);
> +
> + /*
> + * The encoder is already disabled if self refresh mode was set earlier,
> + * in the old_state for the corresponding crtc.
> + */
> + if (old_state && old_state->self_refresh_active)
> + return;
> +
Again the same question here, doesn't crtc_needs_disable() take care of
this clause? I might be missing something in the PSR state transitions.
Could you please add some explanation here?
> mutex_lock(&dpu_enc->enc_lock);
> dpu_enc->enabled = false;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index a683bd9..681dd2e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -491,7 +491,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
> return;
> }
>
> - if (!crtc->state->active) {
> + if (!drm_atomic_crtc_effectively_active(crtc->state)) {
> DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
> return;
> }
--
With best wishes
Dmitry
> -----Original Message-----
> From: Dmitry Baryshkov <[email protected]>
> Sent: Tuesday, January 31, 2023 6:29 PM
> To: Vinod Polimera (QUIC) <[email protected]>; dri-
> [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; Kalyan Thota (QUIC)
> <[email protected]>; Kuogee Hsieh (QUIC)
> <[email protected]>; Vishnuvardhan Prodduturi (QUIC)
> <[email protected]>; Bjorn Andersson (QUIC)
> <[email protected]>; Abhinav Kumar (QUIC)
> <[email protected]>; Sankeerth Billakanti (QUIC)
> <[email protected]>
> Subject: Re: [PATCH v12 13/14] drm/msm/disp/dpu: add PSR support for eDP
> interface in dpu driver
>
>
> On 30/01/2023 17:11, Vinod Polimera wrote:
> > Enable PSR on eDP interface using drm self-refresh librabry.
> > This patch uses a trigger from self-refresh library to enter/exit
> > into PSR, when there are no updates from framework.
> >
> > Signed-off-by: Kalyan Thota <[email protected]>
> > Signed-off-by: Vinod Polimera <[email protected]>
> > Reviewed-by: Dmitry Baryshkov <[email protected]>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 ++++++++++++-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> > 3 files changed, 27 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > index f29a339..60e5984 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > @@ -21,6 +21,7 @@
> > #include <drm/drm_probe_helper.h>
> > #include <drm/drm_rect.h>
> > #include <drm/drm_vblank.h>
> > +#include <drm/drm_self_refresh_helper.h>
> >
> > #include "dpu_kms.h"
> > #include "dpu_hw_lm.h"
> > @@ -1021,6 +1022,9 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
> >
> > DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
> >
> > + if (old_crtc_state->self_refresh_active)
> > + return;
> > +
>
> I have been looking at the crtc_needs_disable(). It explicitly mentions
> that 'We also need to run through the crtc_funcs->disable() function
> [..] if it's transitioning to self refresh mode...'. Don't we need to
> perform some cleanup here (like disabling the vblank irq handling,
> freeing the bandwidth, etc)?
When self refresh active is enabled, then we will clean up irq handling and bandwidth etc.
The above case is to handle display off commit triggered when we are in psr as all
the resources are already cleaned up . we just need to do an early return.
>
> > /* Disable/save vblank irq handling */
> > drm_crtc_vblank_off(crtc);
> >
> > @@ -1577,7 +1581,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device
> *dev, struct drm_plane *plane,
> > {
> > struct drm_crtc *crtc = NULL;
> > struct dpu_crtc *dpu_crtc = NULL;
> > - int i;
> > + int i, ret;
> >
> > dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
> > if (!dpu_crtc)
> > @@ -1614,6 +1618,13 @@ struct drm_crtc *dpu_crtc_init(struct
> drm_device *dev, struct drm_plane *plane,
> > /* initialize event handling */
> > spin_lock_init(&dpu_crtc->event_lock);
> >
> > + ret = drm_self_refresh_helper_init(crtc);
> > + if (ret) {
> > + DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n",
> > + crtc->name, ret);
> > + return ERR_PTR(ret);
> > + }
> > +
> > DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc-
> >name);
> > return crtc;
> > }
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 01b7509..450abb1 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -12,6 +12,7 @@
> > #include <linux/kthread.h>
> > #include <linux/seq_file.h>
> >
> > +#include <drm/drm_atomic.h>
> > #include <drm/drm_crtc.h>
> > #include <drm/drm_file.h>
> > #include <drm/drm_probe_helper.h>
> > @@ -1212,11 +1213,24 @@ static void
> dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
> > struct drm_atomic_state *state)
> > {
> > struct dpu_encoder_virt *dpu_enc = NULL;
> > + struct drm_crtc *crtc;
> > + struct drm_crtc_state *old_state = NULL;
> > int i = 0;
> >
> > dpu_enc = to_dpu_encoder_virt(drm_enc);
> > DPU_DEBUG_ENC(dpu_enc, "\n");
> >
> > + crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
> > + if (crtc)
> > + old_state = drm_atomic_get_old_crtc_state(state, crtc);
> > +
> > + /*
> > + * The encoder is already disabled if self refresh mode was set earlier,
> > + * in the old_state for the corresponding crtc.
> > + */
> > + if (old_state && old_state->self_refresh_active)
> > + return;
> > +
>
> Again the same question here, doesn't crtc_needs_disable() take care of
> this clause? I might be missing something in the PSR state transitions.
> Could you please add some explanation here?
Same usecase as above, applies to encoder disable also when triggered via disable commit
When driver is in psr state.
>
> > mutex_lock(&dpu_enc->enc_lock);
> > dpu_enc->enabled = false;
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > index a683bd9..681dd2e 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > @@ -491,7 +491,7 @@ static void dpu_kms_wait_for_commit_done(struct
> msm_kms *kms,
> > return;
> > }
> >
> > - if (!crtc->state->active) {
> > + if (!drm_atomic_crtc_effectively_active(crtc->state)) {
> > DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
> > return;
> > }
>
> --
> With best wishes
> Dmitry
Thanks,
Vinod P.
> -----Original Message-----
> From: Dmitry Baryshkov <[email protected]>
> Sent: Tuesday, January 31, 2023 6:19 PM
> To: Vinod Polimera (QUIC) <[email protected]>; dri-
> [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: Sankeerth Billakanti (QUIC) <[email protected]>; linux-
> [email protected]; [email protected]; [email protected];
> [email protected]; Kalyan Thota (QUIC) <[email protected]>;
> Kuogee Hsieh (QUIC) <[email protected]>; Vishnuvardhan
> Prodduturi (QUIC) <[email protected]>; Bjorn Andersson (QUIC)
> <[email protected]>; Abhinav Kumar (QUIC)
> <[email protected]>
> Subject: Re: [PATCH v12 09/14] drm/msm/dp: disable self_refresh_aware
> after entering psr
>
> On 30/01/2023 17:11, Vinod Polimera wrote:
> > From: Sankeerth Billakanti <[email protected]>
> >
> > Updated frames get queued if self_refresh_aware is set when the
> > sink is in psr. To support bridge enable and avoid queuing of update
> > frames, reset the self_refresh_aware state after entering psr.
> >
> > Signed-off-by: Sankeerth Billakanti <[email protected]>
> > Signed-off-by: Vinod Polimera <[email protected]>
> > ---
> > drivers/gpu/drm/msm/dp/dp_drm.c | 25 ++++++++++++++++++++++++-
> > 1 file changed, 24 insertions(+), 1 deletion(-)
>
> As I stated in v11's discussion, I do not like the way this change plays
> with the self_refresh_aware. Please find another way to work around the
> timing issue (let's probably continue the discussion back in v11).
>
Currently we are not able to reproduce the issue with KASAN enabled and minimum cpu frequency builds.
We can revisit this patch if it is reproduced in future. Meanwhile I think on handling it in a different way.
Can we not consider this patch for current merge?
> --
> With best wishes
> Dmitry
Thanks,
Vinod P.
On 07/02/2023 16:28, Vinod Polimera wrote:
>
>
>> -----Original Message-----
>> From: Dmitry Baryshkov <[email protected]>
>> Sent: Tuesday, January 31, 2023 6:19 PM
>> To: Vinod Polimera (QUIC) <[email protected]>; dri-
>> [email protected]; [email protected];
>> [email protected]; [email protected]
>> Cc: Sankeerth Billakanti (QUIC) <[email protected]>; linux-
>> [email protected]; [email protected]; [email protected];
>> [email protected]; Kalyan Thota (QUIC) <[email protected]>;
>> Kuogee Hsieh (QUIC) <[email protected]>; Vishnuvardhan
>> Prodduturi (QUIC) <[email protected]>; Bjorn Andersson (QUIC)
>> <[email protected]>; Abhinav Kumar (QUIC)
>> <[email protected]>
>> Subject: Re: [PATCH v12 09/14] drm/msm/dp: disable self_refresh_aware
>> after entering psr
Can we please get rid of this somehow?
>>
>> On 30/01/2023 17:11, Vinod Polimera wrote:
>>> From: Sankeerth Billakanti <[email protected]>
>>>
>>> Updated frames get queued if self_refresh_aware is set when the
>>> sink is in psr. To support bridge enable and avoid queuing of update
>>> frames, reset the self_refresh_aware state after entering psr.
>>>
>>> Signed-off-by: Sankeerth Billakanti <[email protected]>
>>> Signed-off-by: Vinod Polimera <[email protected]>
>>> ---
>>> drivers/gpu/drm/msm/dp/dp_drm.c | 25 ++++++++++++++++++++++++-
>>> 1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> As I stated in v11's discussion, I do not like the way this change plays
>> with the self_refresh_aware. Please find another way to work around the
>> timing issue (let's probably continue the discussion back in v11).
>>
> Currently we are not able to reproduce the issue with KASAN enabled and minimum cpu frequency builds.
> We can revisit this patch if it is reproduced in future. Meanwhile I think on handling it in a different way.
> Can we not consider this patch for current merge?
Ack.
--
With best wishes
Dmitry
On 07/02/2023 16:26, Vinod Polimera wrote:
>
>
>> -----Original Message-----
>> From: Dmitry Baryshkov <[email protected]>
>> Sent: Tuesday, January 31, 2023 6:29 PM
>> To: Vinod Polimera (QUIC) <[email protected]>; dri-
>> [email protected]; [email protected];
>> [email protected]; [email protected]
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected]; Kalyan Thota (QUIC)
>> <[email protected]>; Kuogee Hsieh (QUIC)
>> <[email protected]>; Vishnuvardhan Prodduturi (QUIC)
>> <[email protected]>; Bjorn Andersson (QUIC)
>> <[email protected]>; Abhinav Kumar (QUIC)
>> <[email protected]>; Sankeerth Billakanti (QUIC)
>> <[email protected]>
>> Subject: Re: [PATCH v12 13/14] drm/msm/disp/dpu: add PSR support for eDP
>> interface in dpu driver
>>
>>
>> On 30/01/2023 17:11, Vinod Polimera wrote:
>>> Enable PSR on eDP interface using drm self-refresh librabry.
>>> This patch uses a trigger from self-refresh library to enter/exit
>>> into PSR, when there are no updates from framework.
>>>
>>> Signed-off-by: Kalyan Thota <[email protected]>
>>> Signed-off-by: Vinod Polimera <[email protected]>
>>> Reviewed-by: Dmitry Baryshkov <[email protected]>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 ++++++++++++-
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++++++++++++++
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
>>> 3 files changed, 27 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> index f29a339..60e5984 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> @@ -21,6 +21,7 @@
>>> #include <drm/drm_probe_helper.h>
>>> #include <drm/drm_rect.h>
>>> #include <drm/drm_vblank.h>
>>> +#include <drm/drm_self_refresh_helper.h>
>>>
>>> #include "dpu_kms.h"
>>> #include "dpu_hw_lm.h"
>>> @@ -1021,6 +1022,9 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
>>>
>>> DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
>>>
>>> + if (old_crtc_state->self_refresh_active)
>>> + return;
>>> +
>>
>> I have been looking at the crtc_needs_disable(). It explicitly mentions
>> that 'We also need to run through the crtc_funcs->disable() function
>> [..] if it's transitioning to self refresh mode...'. Don't we need to
>> perform some cleanup here (like disabling the vblank irq handling,
>> freeing the bandwidth, etc)?
>
> When self refresh active is enabled, then we will clean up irq handling and bandwidth etc.
> The above case is to handle display off commit triggered when we are in psr as all
> the resources are already cleaned up . we just need to do an early return.
>>
>>> /* Disable/save vblank irq handling */
>>> drm_crtc_vblank_off(crtc);
>>>
>>> @@ -1577,7 +1581,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device
>> *dev, struct drm_plane *plane,
>>> {
>>> struct drm_crtc *crtc = NULL;
>>> struct dpu_crtc *dpu_crtc = NULL;
>>> - int i;
>>> + int i, ret;
>>>
>>> dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
>>> if (!dpu_crtc)
>>> @@ -1614,6 +1618,13 @@ struct drm_crtc *dpu_crtc_init(struct
>> drm_device *dev, struct drm_plane *plane,
>>> /* initialize event handling */
>>> spin_lock_init(&dpu_crtc->event_lock);
>>>
>>> + ret = drm_self_refresh_helper_init(crtc);
>>> + if (ret) {
>>> + DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n",
>>> + crtc->name, ret);
>>> + return ERR_PTR(ret);
>>> + }
>>> +
>>> DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc-
>>> name);
>>> return crtc;
>>> }
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>> index 01b7509..450abb1 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>> @@ -12,6 +12,7 @@
>>> #include <linux/kthread.h>
>>> #include <linux/seq_file.h>
>>>
>>> +#include <drm/drm_atomic.h>
>>> #include <drm/drm_crtc.h>
>>> #include <drm/drm_file.h>
>>> #include <drm/drm_probe_helper.h>
>>> @@ -1212,11 +1213,24 @@ static void
>> dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
>>> struct drm_atomic_state *state)
>>> {
>>> struct dpu_encoder_virt *dpu_enc = NULL;
>>> + struct drm_crtc *crtc;
>>> + struct drm_crtc_state *old_state = NULL;
>>> int i = 0;
>>>
>>> dpu_enc = to_dpu_encoder_virt(drm_enc);
>>> DPU_DEBUG_ENC(dpu_enc, "\n");
>>>
>>> + crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
>>> + if (crtc)
>>> + old_state = drm_atomic_get_old_crtc_state(state, crtc);
>>> +
>>> + /*
>>> + * The encoder is already disabled if self refresh mode was set earlier,
>>> + * in the old_state for the corresponding crtc.
>>> + */
>>> + if (old_state && old_state->self_refresh_active)
>>> + return;
>>> +
>>
>> Again the same question here, doesn't crtc_needs_disable() take care of
>> this clause? I might be missing something in the PSR state transitions.
>> Could you please add some explanation here?
> Same usecase as above, applies to encoder disable also when triggered via disable commit
> When driver is in psr state.
Ack, thank you for the explanations. I'd like to take another glance
later today, but generally it look good to me.
--
With best wishes
Dmitry
On 07/02/2023 17:25, Dmitry Baryshkov wrote:
> On 07/02/2023 16:26, Vinod Polimera wrote:
>>
>>
>>> -----Original Message-----
>>> From: Dmitry Baryshkov <[email protected]>
>>> Sent: Tuesday, January 31, 2023 6:29 PM
>>> To: Vinod Polimera (QUIC) <[email protected]>; dri-
>>> [email protected]; [email protected];
>>> [email protected]; [email protected]
>>> Cc: [email protected]; [email protected];
>>> [email protected]; [email protected]; Kalyan Thota (QUIC)
>>> <[email protected]>; Kuogee Hsieh (QUIC)
>>> <[email protected]>; Vishnuvardhan Prodduturi (QUIC)
>>> <[email protected]>; Bjorn Andersson (QUIC)
>>> <[email protected]>; Abhinav Kumar (QUIC)
>>> <[email protected]>; Sankeerth Billakanti (QUIC)
>>> <[email protected]>
>>> Subject: Re: [PATCH v12 13/14] drm/msm/disp/dpu: add PSR support for eDP
>>> interface in dpu driver
>>>
>>>
>>> On 30/01/2023 17:11, Vinod Polimera wrote:
>>>> Enable PSR on eDP interface using drm self-refresh librabry.
>>>> This patch uses a trigger from self-refresh library to enter/exit
>>>> into PSR, when there are no updates from framework.
>>>>
>>>> Signed-off-by: Kalyan Thota <[email protected]>
>>>> Signed-off-by: Vinod Polimera <[email protected]>
>>>> Reviewed-by: Dmitry Baryshkov <[email protected]>
>>>> ---
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 ++++++++++++-
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++++++++++++++
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
>>>> 3 files changed, 27 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> index f29a339..60e5984 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> @@ -21,6 +21,7 @@
>>>> #include <drm/drm_probe_helper.h>
>>>> #include <drm/drm_rect.h>
>>>> #include <drm/drm_vblank.h>
>>>> +#include <drm/drm_self_refresh_helper.h>
>>>>
>>>> #include "dpu_kms.h"
>>>> #include "dpu_hw_lm.h"
>>>> @@ -1021,6 +1022,9 @@ static void dpu_crtc_disable(struct drm_crtc
>>>> *crtc,
>>>>
>>>> DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
>>>>
>>>> + if (old_crtc_state->self_refresh_active)
>>>> + return;
>>>> +
>>>
>>> I have been looking at the crtc_needs_disable(). It explicitly mentions
>>> that 'We also need to run through the crtc_funcs->disable() function
>>> [..] if it's transitioning to self refresh mode...'. Don't we need to
>>> perform some cleanup here (like disabling the vblank irq handling,
>>> freeing the bandwidth, etc)?
>>
>> When self refresh active is enabled, then we will clean up irq
>> handling and bandwidth etc.
>> The above case is to handle display off commit triggered when we are
>> in psr as all
>> the resources are already cleaned up . we just need to do an early
>> return.
>>>
>>>> /* Disable/save vblank irq handling */
>>>> drm_crtc_vblank_off(crtc);
>>>>
>>>> @@ -1577,7 +1581,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device
>>> *dev, struct drm_plane *plane,
>>>> {
>>>> struct drm_crtc *crtc = NULL;
>>>> struct dpu_crtc *dpu_crtc = NULL;
>>>> - int i;
>>>> + int i, ret;
>>>>
>>>> dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
>>>> if (!dpu_crtc)
>>>> @@ -1614,6 +1618,13 @@ struct drm_crtc *dpu_crtc_init(struct
>>> drm_device *dev, struct drm_plane *plane,
>>>> /* initialize event handling */
>>>> spin_lock_init(&dpu_crtc->event_lock);
>>>>
>>>> + ret = drm_self_refresh_helper_init(crtc);
>>>> + if (ret) {
>>>> + DPU_ERROR("Failed to initialize %s with self-refresh
>>>> helpers %d\n",
>>>> + crtc->name, ret);
>>>> + return ERR_PTR(ret);
>>>> + }
>>>> +
>>>> DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc-
>>>> name);
>>>> return crtc;
>>>> }
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>>> index 01b7509..450abb1 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>>> @@ -12,6 +12,7 @@
>>>> #include <linux/kthread.h>
>>>> #include <linux/seq_file.h>
>>>>
>>>> +#include <drm/drm_atomic.h>
>>>> #include <drm/drm_crtc.h>
>>>> #include <drm/drm_file.h>
>>>> #include <drm/drm_probe_helper.h>
>>>> @@ -1212,11 +1213,24 @@ static void
>>> dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
>>>> struct drm_atomic_state *state)
>>>> {
>>>> struct dpu_encoder_virt *dpu_enc = NULL;
>>>> + struct drm_crtc *crtc;
>>>> + struct drm_crtc_state *old_state = NULL;
>>>> int i = 0;
>>>>
>>>> dpu_enc = to_dpu_encoder_virt(drm_enc);
>>>> DPU_DEBUG_ENC(dpu_enc, "\n");
>>>>
>>>> + crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
>>>> + if (crtc)
>>>> + old_state = drm_atomic_get_old_crtc_state(state, crtc);
>>>> +
>>>> + /*
>>>> + * The encoder is already disabled if self refresh mode was
>>>> set earlier,
>>>> + * in the old_state for the corresponding crtc.
>>>> + */
>>>> + if (old_state && old_state->self_refresh_active)
>>>> + return;
>>>> +
>>>
>>> Again the same question here, doesn't crtc_needs_disable() take care of
>>> this clause? I might be missing something in the PSR state transitions.
>>> Could you please add some explanation here?
>> Same usecase as above, applies to encoder disable also when triggered
>> via disable commit
>> When driver is in psr state.
>
> Ack, thank you for the explanations. I'd like to take another glance
> later today, but generally it look good to me.
After another glance it still looks good to me. Please send the last
iteration of the series:
- moving all core patches to the first place, as it was asked
previously. This will help us get them merged to drm core repo first
- dropping the patch 09 as agreed.
--
With best wishes
Dmitry