On 11/14/23 14:56, Bibek Kumar Patro wrote:
> Context caching is re-enabled in the prefetch buffer for Qualcomm SoCs
> through SoC specific reset ops, which is disabled in the default MMU-500
> reset ops, but is expected for context banks using ACTLR register to
> retain the prefetch value during reset and runtime suspend.
>
> Signed-off-by: Bibek Kumar Patro <[email protected]>
> ---
And I assume that goes for all SMMU500 implementations?
Looking at the 8550 ACTRL array from patch 2, CPRE is not enabled
at all times.. Is that because of performance, or some other
technical reason?
Will this regress platforms without ACTRL tables?
Konrad
On 11/15/2023 10:13 PM, Konrad Dybcio wrote:
>
>
> On 11/14/23 14:56, Bibek Kumar Patro wrote:
>> Context caching is re-enabled in the prefetch buffer for Qualcomm SoCs
>> through SoC specific reset ops, which is disabled in the default MMU-500
>> reset ops, but is expected for context banks using ACTLR register to
>> retain the prefetch value during reset and runtime suspend.
>>
>> Signed-off-by: Bibek Kumar Patro <[email protected]>
>> ---
> And I assume that goes for all SMMU500 implementations?
>
Right, for all SMMU500 implementation for Qualcomm SoCs.
Hence implemented this enablement with Qualcomm specific reset operation.
> Looking at the 8550 ACTRL array from patch 2, CPRE is not enabled
> at all times.. Is that because of performance, or some other
> technical reason?
>
> Will this regress platforms without ACTRL tables?
>
It should not regress, If you check my recent reply on Dimitry's
response, the Corelink revision is r2p4 and it can be enabled.
On the Robin's mentioned errata workarounds, let me check once.
Thanks & regards,
Bibek
> Konrad