This series enables eMMC support on AM62a SK.
Change Log:
V1 -> V2:
- Updated commit message in 2nd patch of series.
- Moved alias changes to 2nd patch of series.
v1: https://lore.kernel.org/all/[email protected]/
Nitin Yadav (2):
arm64: dts: ti: k3-am62a-main: Add sdhci0 instance
arm64: dts: ti: k3-am62a7-sk: Enable eMMC support
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 25 +++++++++++++++++++++++
2 files changed, 44 insertions(+)
--
2.25.1
Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
ITAP values as they are NA in datasheet[0] for lower speed modes.
[0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)
Signed-off-by: Nitin Yadav <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
index de36abb243f1..89b8b7d302cd 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
@@ -488,6 +488,25 @@ main_gpio1: gpio@601000 {
status = "disabled";
};
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&k3_clks 57 6>;
+ assigned-clock-parents = <&k3_clks 57 8>;
+ mmc-hs200-1_8v;
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-hs200 = <0x6>;
+ bus-width = <8>;
+ ti,clkbuf-sel = <0x7>;
+ status = "disabled";
+ };
+
sdhci1: mmc@fa00000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
--
2.25.1
Add support for 32GB eMMC card on AM62A7 SK. Includes adding mmc0
pins settings. Add mmc0 alias for sdhci0 in k3-am62a7-sk.dts.
Signed-off-by: Nitin Yadav <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
index cff283c75f8e..c6f144d91734 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
@@ -20,6 +20,7 @@ aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
+ mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
@@ -172,6 +173,22 @@ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
+ main_mmc0_pins_default: main-mmc0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
+ AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
+ AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
+ AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
+ AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
+ AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
+ AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
+ AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
+ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
+ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
+ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
+ >;
+ };
+
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@@ -361,3 +378,11 @@ cpsw3g_phy0: ethernet-phy@0 {
ti,min-output-impedance;
};
};
+
+&sdhci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc0_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
--
2.25.1
On 10/30/23 1:31 AM, Nitin Yadav wrote:
> Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
> ITAP values as they are NA in datasheet[0] for lower speed modes.
>
> [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)
>
Minor comment below. All else looks good to me.
Reviewed by: Judith Mendez <[email protected]>
> Signed-off-by: Nitin Yadav <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> index de36abb243f1..89b8b7d302cd 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 {
> status = "disabled";
> };
>
> + sdhci0: mmc@fa10000 {
> + compatible = "ti,am62-sdhci";
> + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
> + clock-names = "clk_ahb", "clk_xin";
> + assigned-clocks = <&k3_clks 57 6>;
> + assigned-clock-parents = <&k3_clks 57 8>;
> + mmc-hs200-1_8v;
> + ti,trm-icp = <0x2>;
> + ti,otap-del-sel-legacy = <0x0>;
> + ti,otap-del-sel-mmc-hs = <0x0>;
> + ti,otap-del-sel-hs200 = <0x6>;
I am wondering why DDR52 speed mode was not added?
> + bus-width = <8>;
> + ti,clkbuf-sel = <0x7>;
> + status = "disabled";
> + };
> +
> sdhci1: mmc@fa00000 {
> compatible = "ti,am62-sdhci";
> reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
~ Judith
On 11/28/2023 3:11 AM, Judith Mendez wrote:
> On 10/30/23 1:31 AM, Nitin Yadav wrote:
>> Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
>> ITAP values as they are NA in datasheet[0] for lower speed modes.
>>
>> [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)
>>
>
> Minor comment below. All else looks good to me.
>
> Reviewed by: Judith Mendez <[email protected]>
>
>> Signed-off-by: Nitin Yadav <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>> index de36abb243f1..89b8b7d302cd 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>> @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 {
>> status = "disabled";
>> };
>> + sdhci0: mmc@fa10000 {
>> + compatible = "ti,am62-sdhci";
>> + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
>> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
>> + clock-names = "clk_ahb", "clk_xin";
>> + assigned-clocks = <&k3_clks 57 6>;
>> + assigned-clock-parents = <&k3_clks 57 8>;
>> + mmc-hs200-1_8v;
>> + ti,trm-icp = <0x2>;
>> + ti,otap-del-sel-legacy = <0x0>;
>> + ti,otap-del-sel-mmc-hs = <0x0>;
>> + ti,otap-del-sel-hs200 = <0x6>;
>
> I am wondering why DDR52 speed mode was not added?
plz refer datasheet. No mention of DDR52 in this revised addition.
>
>> + bus-width = <8>;
>> + ti,clkbuf-sel = <0x7>;
>> + status = "disabled";
>> + };
>> +
>> sdhci1: mmc@fa00000 {
>> compatible = "ti,am62-sdhci";
>> reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
>
> ~ Judith
Hi Nitin,
On 11/27/23 10:39 PM, Nitin Yadav wrote:
>
>
> On 11/28/2023 3:11 AM, Judith Mendez wrote:
>> On 10/30/23 1:31 AM, Nitin Yadav wrote:
>>> Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
>>> ITAP values as they are NA in datasheet[0] for lower speed modes.
>>>
>>> [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)
>>>
>>
>> Minor comment below. All else looks good to me.
>>
>> Reviewed by: Judith Mendez <[email protected]>
>>
>>> Signed-off-by: Nitin Yadav <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
>>> 1 file changed, 19 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>>> index de36abb243f1..89b8b7d302cd 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>>> @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 {
>>> status = "disabled";
>>> };
>>> + sdhci0: mmc@fa10000 {
>>> + compatible = "ti,am62-sdhci";
>>> + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
>>> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>>> + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
>>> + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
>>> + clock-names = "clk_ahb", "clk_xin";
>>> + assigned-clocks = <&k3_clks 57 6>;
>>> + assigned-clock-parents = <&k3_clks 57 8>;
>>> + mmc-hs200-1_8v;
>>> + ti,trm-icp = <0x2>;
>>> + ti,otap-del-sel-legacy = <0x0>;
>>> + ti,otap-del-sel-mmc-hs = <0x0>;
>>> + ti,otap-del-sel-hs200 = <0x6>;
>>
>> I am wondering why DDR52 speed mode was not added?
> plz refer datasheet. No mention of DDR52 in this revised addition.
I believe it is mentioned in the RIOT, not datasheet.
>>
>>> + bus-width = <8>;
>>> + ti,clkbuf-sel = <0x7>;
>>> + status = "disabled";
>>> + };
>>> +
>>> sdhci1: mmc@fa00000 {
>>> compatible = "ti,am62-sdhci";
>>> reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
>>
>> ~ Judith
On 10/30/23 1:31 AM, Nitin Yadav wrote:
> Add support for 32GB eMMC card on AM62A7 SK. Includes adding mmc0
> pins settings. Add mmc0 alias for sdhci0 in k3-am62a7-sk.dts.
>
This looks good to me. Although should it be explained why we are
including pinmux for MMC0?
Reviewed-by: Judith Mendez <[email protected]>
> Signed-off-by: Nitin Yadav <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> index cff283c75f8e..c6f144d91734 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> @@ -20,6 +20,7 @@ aliases {
> serial0 = &wkup_uart0;
> serial2 = &main_uart0;
> serial3 = &main_uart1;
> + mmc0 = &sdhci0;
> mmc1 = &sdhci1;
> };
>
> @@ -172,6 +173,22 @@ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
> >;
> };
>
> + main_mmc0_pins_default: main-mmc0-default-pins {
> + pinctrl-single,pins = <
> + AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
> + AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
> + AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
> + AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
> + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
> + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
> + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
> + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
> + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
> + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
> + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
> + >;
> + };
> +
> main_mmc1_pins_default: main-mmc1-default-pins {
> pinctrl-single,pins = <
> AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
> @@ -361,3 +378,11 @@ cpsw3g_phy0: ethernet-phy@0 {
> ti,min-output-impedance;
> };
> };
> +
> +&sdhci0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mmc0_pins_default>;
> + ti,driver-strength-ohm = <50>;
> + disable-wp;
> +};