On Tue, Aug 15, 2023 at 05:56:47PM +0530, Krishna chaitanya chundru wrote:
> PCIe needs to choose the appropriate performance state of RPMH power
> domain based upon the PCIe gen speed.
>
> So, let's add the OPP table support to specify RPMH performance states.
>
> Signed-off-by: Krishna chaitanya chundru <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 595533a..681ea9c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -381,6 +381,49 @@
> };
> };
>
> + pcie0_opp_table: opp-table-pcie0 {
> + compatible = "operating-points-v2";
> +
> + opp-2500000 {
> + opp-hz = /bits/ 64 <2500000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + opp-5000000 {
> + opp-hz = /bits/ 64 <5000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + opp-8000000 {
> + opp-hz = /bits/ 64 <8000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> + };
> +
> + pcie1_opp_table: opp-table-pcie1 {
> + compatible = "operating-points-v2";
> +
> + opp-2500000 {
> + opp-hz = /bits/ 64 <2500000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + opp-5000000 {
> + opp-hz = /bits/ 64 <5000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + opp-8000000 {
> + opp-hz = /bits/ 64 <8000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + opp-16000000 {
> + opp-hz = /bits/ 64 <16000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> + };
> +
Should not we using required-opps property to pass the
rpmhpd_opp_xxx phandle so that when this OPP is selected based on your
clock rate, the appropriate OPP (voltage) would be selected on the RPMH side?
Please see SDHCI/MMC voting (sdhc2_opp_table) as an example.
Thanks,
Pavan