2019-11-13 07:23:25

by Dilip Kota

Subject: [PATCH v6 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file

Intel PCIe is Synopsys based controller. Intel PCIe driver uses
DesignWare PCIe framework for host initialization and register
configurations.

Changes on v6:
Add Reviewed by tags for all the patches.
Address review comments for all the patches.

Dilip Kota (3):
dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
dwc: PCI: intel: PCIe RC controller driver
PCI: artpec6: Configure FTS with dwc helper function

.../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 ++++++
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-
drivers/pci/controller/dwc/pcie-designware.c | 57 +++
drivers/pci/controller/dwc/pcie-designware.h | 12 +
drivers/pci/controller/dwc/pcie-intel-gw.c | 546 +++++++++++++++++
include/uapi/linux/pci_regs.h | 1 +
8 files changed, 766 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c

--
2.11.0

2019-11-13 07:23:51

by Dilip Kota

Subject: [PATCH v6 3/3] PCI: artpec6: Configure FTS with dwc helper function

Use DesignWare helper functions to configure Fast Training
Sequence. Drop the respective code in the driver.

Signed-off-by: Dilip Kota <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
---
Changes on v6:
Typo fix:s/DesugnWare/DesignWare
Update 'Utilize DesignWare' --> 'Use DesignWare'
Add Reviewed-by: Andrew Murray <[email protected]>
---
drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index d00252bd8fae..02d93b8c7942 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[];
#define ACK_N_FTS_MASK GENMASK(15, 8)
#define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK)

-#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0)
-#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK)
-
/* ARTPEC-6 specific registers */
#define PCIECFG 0x18
#define PCIECFG_DBG_OEN BIT(24)
@@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
* Set the Number of Fast Training Sequences that the core
* advertises as its N_FTS during Gen2 or Gen3 link training.
*/
- val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
- val &= ~FAST_TRAINING_SEQ_MASK;
- val |= FAST_TRAINING_SEQ(180);
- dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+ dw_pcie_link_set_n_fts(pci, 180);
}

static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
--
2.11.0