Add coherency_max_size variable to record the maximum cache line size
for different cache levels. We will synchronize it with CTR_EL0.CWG
reporting in cache_line_size() for arm64.
Cc: Greg Kroah-Hartman <[email protected]>
Cc: "Rafael J. Wysocki" <[email protected]>
Cc: Sudeep Holla <[email protected]>
Cc: Catalin Marinas <[email protected]>
Cc: Jeremy Linton <[email protected]>
Cc: Will Deacon <[email protected]>
Signed-off-by: Shaokun Zhang <[email protected]>
---
ChangeLog since v2:
-- Rebase to 5.2-rc2
-- Export cache_line_size for I/O driver
ChangeLog since v1:
-- Move coherency_max_size to drivers/base/cacheinfo.c
-- Address Catalin's comments
Link: https://www.spinics.net/lists/arm-kernel/msg723615.html
drivers/base/cacheinfo.c | 5 +++++
include/linux/cacheinfo.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index a7359535caf5..8827c60f51e2 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -213,6 +213,8 @@ int __weak cache_setup_acpi(unsigned int cpu)
return -ENOTSUPP;
}
+unsigned int coherency_max_size;
+
static int cache_shared_cpu_map_setup(unsigned int cpu)
{
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
@@ -251,6 +253,9 @@ static int cache_shared_cpu_map_setup(unsigned int cpu)
cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
}
}
+ /* record the maximum cache line size */
+ if (this_leaf->coherency_line_size > coherency_max_size)
+ coherency_max_size = this_leaf->coherency_line_size;
}
return 0;
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 70e19bc6cc9f..46b92cd61d0c 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -17,6 +17,8 @@ enum cache_type {
CACHE_TYPE_UNIFIED = BIT(2),
};
+extern unsigned int coherency_max_size;
+
/**
* struct cacheinfo - represent a cache leaf node
* @id: This cache's id. It is unique among caches with the same (type, level).
--
2.7.4
cache_line_size is derived from CTR_EL0.CWG field and is called mostly
for I/O device drivers. For HiSilicon certain plantform, like the
Kunpeng920 server SoC, cache line sizes are different between L1/2
cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte,
but CTR_EL0.CWG is misreporting using L1 cache line size.
We shall correct the right value which is important for I/O performance.
Let's update the cache line size if it is detected from DT or PPTT
information.
Cc: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Sudeep Holla <[email protected]>
Cc: Jeremy Linton <[email protected]>
Cc: Zhenfa Qiu <[email protected]>
Reported-by: Zhenfa Qiu <[email protected]>
Suggested-by: Catalin Marinas <[email protected]>
Signed-off-by: Shaokun Zhang <[email protected]>
---
arch/arm64/include/asm/cache.h | 6 +-----
arch/arm64/kernel/cacheinfo.c | 11 +++++++++++
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 926434f413fa..758af6340314 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void)
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
-static inline int cache_line_size(void)
-{
- u32 cwg = cache_type_cwg();
- return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
-}
+int cache_line_size(void);
/*
* Read the effective value of CTR_EL0.
diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
index 0bf0a835122f..3d54b0024246 100644
--- a/arch/arm64/kernel/cacheinfo.c
+++ b/arch/arm64/kernel/cacheinfo.c
@@ -28,6 +28,17 @@
#define CLIDR_CTYPE(clidr, level) \
(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
+int cache_line_size(void)
+{
+ u32 cwg = cache_type_cwg();
+
+ if (coherency_max_size != 0)
+ return coherency_max_size;
+
+ return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
+}
+EXPORT_SYMBOL(cache_line_size);
+
static inline enum cache_type get_cache_type(int level)
{
u64 clidr;
--
2.7.4
On Mon, May 27, 2019 at 10:06:07AM +0800, Shaokun Zhang wrote:
> Add coherency_max_size variable to record the maximum cache line size
> for different cache levels. We will synchronize it with CTR_EL0.CWG
> reporting in cache_line_size() for arm64.
>
> Cc: Greg Kroah-Hartman <[email protected]>
> Cc: "Rafael J. Wysocki" <[email protected]>
> Cc: Sudeep Holla <[email protected]>
> Cc: Catalin Marinas <[email protected]>
> Cc: Jeremy Linton <[email protected]>
> Cc: Will Deacon <[email protected]>
> Signed-off-by: Shaokun Zhang <[email protected]>
> ---
> ChangeLog since v2:
> -- Rebase to 5.2-rc2
> -- Export cache_line_size for I/O driver
> ChangeLog since v1:
> -- Move coherency_max_size to drivers/base/cacheinfo.c
> -- Address Catalin's comments
> Link: https://www.spinics.net/lists/arm-kernel/msg723615.html
>
> drivers/base/cacheinfo.c | 5 +++++
> include/linux/cacheinfo.h | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
> index a7359535caf5..8827c60f51e2 100644
> --- a/drivers/base/cacheinfo.c
> +++ b/drivers/base/cacheinfo.c
> @@ -213,6 +213,8 @@ int __weak cache_setup_acpi(unsigned int cpu)
> return -ENOTSUPP;
> }
>
> +unsigned int coherency_max_size;
Why are you creating a global variable?
Where are the other patches in this series?
thanks,
greg k-h
On Mon, May 27, 2019 at 10:06:08AM +0800, Shaokun Zhang wrote:
> cache_line_size is derived from CTR_EL0.CWG field and is called mostly
> for I/O device drivers. For HiSilicon certain plantform, like the
> Kunpeng920 server SoC, cache line sizes are different between L1/2
> cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte,
> but CTR_EL0.CWG is misreporting using L1 cache line size.
>
> We shall correct the right value which is important for I/O performance.
> Let's update the cache line size if it is detected from DT or PPTT
> information.
>
> Cc: Catalin Marinas <[email protected]>
> Cc: Will Deacon <[email protected]>
> Cc: Sudeep Holla <[email protected]>
> Cc: Jeremy Linton <[email protected]>
> Cc: Zhenfa Qiu <[email protected]>
> Reported-by: Zhenfa Qiu <[email protected]>
> Suggested-by: Catalin Marinas <[email protected]>
> Signed-off-by: Shaokun Zhang <[email protected]>
> ---
> arch/arm64/include/asm/cache.h | 6 +-----
> arch/arm64/kernel/cacheinfo.c | 11 +++++++++++
> 2 files changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
> index 926434f413fa..758af6340314 100644
> --- a/arch/arm64/include/asm/cache.h
> +++ b/arch/arm64/include/asm/cache.h
> @@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void)
>
> #define __read_mostly __attribute__((__section__(".data..read_mostly")))
>
> -static inline int cache_line_size(void)
> -{
> - u32 cwg = cache_type_cwg();
> - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
> -}
> +int cache_line_size(void);
>
> /*
> * Read the effective value of CTR_EL0.
> diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
> index 0bf0a835122f..3d54b0024246 100644
> --- a/arch/arm64/kernel/cacheinfo.c
> +++ b/arch/arm64/kernel/cacheinfo.c
> @@ -28,6 +28,17 @@
> #define CLIDR_CTYPE(clidr, level) \
> (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
>
> +int cache_line_size(void)
> +{
> + u32 cwg = cache_type_cwg();
> +
> + if (coherency_max_size != 0)
> + return coherency_max_size;
Ah, you use it here.
> +
> + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
Shouldn't you set the variable if it is 0 here as well?
> +}
> +EXPORT_SYMBOL(cache_line_size);
EXPORT_SYMBOL_GPL()?
thanks,
greg k-h
Hi Greg,
On 2019/5/27 14:08, Greg KH wrote:
> On Mon, May 27, 2019 at 10:06:08AM +0800, Shaokun Zhang wrote:
>> cache_line_size is derived from CTR_EL0.CWG field and is called mostly
>> for I/O device drivers. For HiSilicon certain plantform, like the
>> Kunpeng920 server SoC, cache line sizes are different between L1/2
>> cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte,
>> but CTR_EL0.CWG is misreporting using L1 cache line size.
>>
>> We shall correct the right value which is important for I/O performance.
>> Let's update the cache line size if it is detected from DT or PPTT
>> information.
>>
>> Cc: Catalin Marinas <[email protected]>
>> Cc: Will Deacon <[email protected]>
>> Cc: Sudeep Holla <[email protected]>
>> Cc: Jeremy Linton <[email protected]>
>> Cc: Zhenfa Qiu <[email protected]>
>> Reported-by: Zhenfa Qiu <[email protected]>
>> Suggested-by: Catalin Marinas <[email protected]>
>> Signed-off-by: Shaokun Zhang <[email protected]>
>> ---
>> arch/arm64/include/asm/cache.h | 6 +-----
>> arch/arm64/kernel/cacheinfo.c | 11 +++++++++++
>> 2 files changed, 12 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
>> index 926434f413fa..758af6340314 100644
>> --- a/arch/arm64/include/asm/cache.h
>> +++ b/arch/arm64/include/asm/cache.h
>> @@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void)
>>
>> #define __read_mostly __attribute__((__section__(".data..read_mostly")))
>>
>> -static inline int cache_line_size(void)
>> -{
>> - u32 cwg = cache_type_cwg();
>> - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
>> -}
>> +int cache_line_size(void);
>>
>> /*
>> * Read the effective value of CTR_EL0.
>> diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
>> index 0bf0a835122f..3d54b0024246 100644
>> --- a/arch/arm64/kernel/cacheinfo.c
>> +++ b/arch/arm64/kernel/cacheinfo.c
>> @@ -28,6 +28,17 @@
>> #define CLIDR_CTYPE(clidr, level) \
>> (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
>>
>> +int cache_line_size(void)
>> +{
>> + u32 cwg = cache_type_cwg();
>> +
>> + if (coherency_max_size != 0)
>> + return coherency_max_size;
>
> Ah, you use it here.
>
Yeah, we check it here.
>> +
>> + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
>
> Shouldn't you set the variable if it is 0 here as well?
>
As discussed this with Catalin,
https://www.spinics.net/lists/arm-kernel/msg723848.html
I think it is unnecessary, if coherency_max_size is not detected from firmware,
We will return the cpu core reporting value as the cache line size and
coherency_max_size won't be used in other place.
>> +}
>> +EXPORT_SYMBOL(cache_line_size);
>
> EXPORT_SYMBOL_GPL()?
>
Ok.
Thanks,
Shaokun
> thanks,
>
> greg k-h
>
> .
>