2023-03-17 06:54:24

by Rohit Agarwal

Subject: [PATCH v4 5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

Enable PCIe Endpoint controller on the SDX65 MTP board based
on Qualcomm SDX65 platform.

Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 70720e6..afe970a 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -245,6 +245,17 @@
status = "okay";
};

+&pcie_ep {
+ pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
+ &pcie_ep_wake_default>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
&pcie_phy {
vdda-phy-supply = <&vreg_l1b_1p2>;
vdda-pll-supply = <&vreg_l4b_0p88>;
@@ -277,6 +288,29 @@
status = "okay";
};

+&tlmm {
+ pcie_ep_clkreq_default: pcie-ep-clkreq-default-state {
+ pins = "gpio56";
+ function = "pcie_clkreq";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie_ep_perst_default: pcie-ep-perst-default-state {
+ pins = "gpio57";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ pcie_ep_wake_default: pcie-ep-wake-default-state {
+ pins = "gpio53";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
&usb {
status = "okay";
};
--
2.7.4

2023-03-28 13:33:14

by Konrad Dybcio

Subject: Re: [PATCH v4 5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

On 17.03.2023 07:53, Rohit Agarwal wrote:
> Enable PCIe Endpoint controller on the SDX65 MTP board based
> on Qualcomm SDX65 platform.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
> arch/arm/boot/dts/qcom-sdx65-mtp.dts | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> index 70720e6..afe970a 100644
> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> @@ -245,6 +245,17 @@
> status = "okay";
> };
>
> +&pcie_ep {
> + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
> + &pcie_ep_wake_default>;
This seems misaligned, the &s should be one below another

But other than that:

Reviewed-by: Konrad Dybcio <[email protected]>

Konrad
> + pinctrl-names = "default";
> +
> + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
> +
> + status = "okay";
> +};
> +
> &pcie_phy {
> vdda-phy-supply = <&vreg_l1b_1p2>;
> vdda-pll-supply = <&vreg_l4b_0p88>;
> @@ -277,6 +288,29 @@
> status = "okay";
> };
>
> +&tlmm {
> + pcie_ep_clkreq_default: pcie-ep-clkreq-default-state {
> + pins = "gpio56";
> + function = "pcie_clkreq";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + pcie_ep_perst_default: pcie-ep-perst-default-state {
> + pins = "gpio57";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + pcie_ep_wake_default: pcie-ep-wake-default-state {
> + pins = "gpio53";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +};
> +
> &usb {
> status = "okay";
> };