This series adds hyperflash support for J721E. J721E SoC has HyperBus
and OSPI controller muxed within the FSS subsystem and the J721E SoM
has a 64 MiB S28 OSPI flash and a 64 MiB Hyperflash present which is
muxed externally also.
* Patch 1/4 adds the hyperbus controller nodes and fixes DT compile
warnings.
* Patch 2/4 adds the hyperflash support in the SoM DTS.
* Patch 3 and 4/4 enables the pinmux for external mux that selects
between hyperflash or OSPI NOR flash, this is done for J7200 and
J721E platforms since it is required in U-Boot and helps keep the
DT in sync.
Patch 1/4 depends on the following patch:
https://lore.kernel.org/all/[email protected]/
Patch 3 depends on the below fix for pinmux offsets in J7200:
https://lore.kernel.org/all/[email protected]/
Bootlog and basic hyperflash erase-write-read test:
https://gist.github.com/vaishnavachath/be652108f3e360f1e2d41b499df844ef
Thanks and Regards,
Vaishnav
Vaishnav Achath (4):
arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node
arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node
arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select
pinmux
arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select
pinmux
.../dts/ti/k3-j7200-common-proc-board.dts | 11 ++++++
.../dts/ti/k3-j721e-common-proc-board.dts | 11 ++++++
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 25 +++++++++++--
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 35 +++++++++++++++++++
4 files changed, 80 insertions(+), 2 deletions(-)
--
2.17.1
J7200 common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 63633e4f6c59..f5cbb4b7a9fb 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -98,6 +98,12 @@
>;
};
+ wkup_gpio_pins_default: wkup-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
+ >;
+ };
+
mcu_mdio_pins_default: mcu-mdio1-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
@@ -187,6 +193,11 @@
status = "disabled";
};
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
&wkup_gpio1 {
status = "disabled";
};
--
2.17.1
J721E common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 7db0603125aa..b7a2f23b2c67 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -363,6 +363,12 @@
J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
>;
};
+
+ wkup_gpio_pins_default: wkup-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
+ >;
+ };
};
&wkup_uart0 {
@@ -420,6 +426,11 @@
status = "disabled";
};
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
&wkup_gpio1 {
status = "disabled";
};
--
2.17.1
Hi,
On 05/05/23 19:44, Vaishnav Achath wrote:
> This series adds hyperflash support for J721E. J721E SoC has HyperBus
> and OSPI controller muxed within the FSS subsystem and the J721E SoM
> has a 64 MiB S28 OSPI flash and a 64 MiB Hyperflash present which is
> muxed externally also.
I have sent a v2 of this series with feedback addressed from a similar
series and also adding the hyperflash partitions:
https://lore.kernel.org/all/[email protected]/
Thanks and Regards,
Vaishnav
>
> * Patch 1/4 adds the hyperbus controller nodes and fixes DT compile
> warnings.
> * Patch 2/4 adds the hyperflash support in the SoM DTS.
> * Patch 3 and 4/4 enables the pinmux for external mux that selects
> between hyperflash or OSPI NOR flash, this is done for J7200 and
> J721E platforms since it is required in U-Boot and helps keep the
> DT in sync.
>
> Patch 1/4 depends on the following patch:
> https://lore.kernel.org/all/[email protected]/
>
> Patch 3 depends on the below fix for pinmux offsets in J7200:
> https://lore.kernel.org/all/[email protected]/
>
> Bootlog and basic hyperflash erase-write-read test:
> https://gist.github.com/vaishnavachath/be652108f3e360f1e2d41b499df844ef
>
> Thanks and Regards,
> Vaishnav
>
> Vaishnav Achath (4):
> arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node
> arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node
> arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select
> pinmux
> arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select
> pinmux
>
> .../dts/ti/k3-j7200-common-proc-board.dts | 11 ++++++
> .../dts/ti/k3-j721e-common-proc-board.dts | 11 ++++++
> .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 25 +++++++++++--
> arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 35 +++++++++++++++++++
> 4 files changed, 80 insertions(+), 2 deletions(-)
>