This series adds support for the AXI PWM GEN subsystem found on FPGA IP
cores. It can be used to generate configurable PWM outputs, and includes
options for external synchronization and clock signals. The work is
being done on behalf of, and therefore lists maintainers from Analog
Devices, Inc.
The series has been tested on actual hardware using an EVAL-AD7985FMCZ
evaluation board. An oscilloscope was used to validate that the
generated PWM signal matched the requested one.
There was previously a follow-up series
(https://lore.kernel.org/linux-pwm/[email protected]/)
that enabled support for two different versions of the AXI PWM GEN IP.
Since issues were identified with the v1 IP functionality and v2's
regmap is the one listed on the device wiki
(https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen), the driver
was changed to support only the v2 IP after squashing those additions.
As a result, the overall driver is simpler as it no longer uses an
axi_pwm_variant struct. Support for v1 IP can be added back later in the
event that it is required.
---
v5 changes:
* Address feedback for driver in v4:
* Clarify device behavior in frontmatter
* Include register name in bitfield definitions
* Use devm_clk_rate_exclusive_get() and handle error
* Squash v2 IP patches into series from: https://lore.kernel.org/linux-pwm/[email protected]/
* Refactor driver code to support only v2 IP
* Issues were identified with v1 IP implementation, so only v2 will be
supported
* Remove axi_pwm_variant struct and usage
* Version check in axi_pwmgen_setup() left as-is to limit usage to
* only v2 IP
* Adjust dt bindings to use adi,axi-pwmgen-2.00.a
v4 changes:
* Address feedback for driver in v3:
* Update to use devm_pwmchip_alloc() function
* Simplify use of dev symbol in axi_pwmgen_probe
* Remove unnecessary axi_pwmgen_from_chip function and use
pwmchip_get_drvdata directly
Link to v3: https://lore.kernel.org/linux-pwm/[email protected]/
v3 changes:
* Address feedback for driver in v2:
* Remove unnecessary blank line in axi_pwmgen_apply
* Use macros already defined in <linux/fpga/adi-axi-common.h> for
version checking
Link to v2: https://lore.kernel.org/linux-pwm/[email protected]/
v2 changes:
* Address feedback for driver and device tree in v1:
* Use more reasonable Kconfig approach
* Use common prefixes for all functions
* Rename axi_pwmgen struct to axi_pwmgen_ddata
* Change use of "pwm" to "ddata"
* Set and check state->polarity
* Multiply safely with mul_u64_u64_div_u64()
* Improve handling of max and zero periods
* Error if clk_rate_hz > NSEC_PER_SEC
* Add "Limitations" section at top of pwm-axi-pwmgen.c
* Don't disable outputs by default
* Remove unnecessary macros for period, duty, offset
* Fix axi_pwmgen_ddata alignment
* Don't artificially limit npwm to four
* Use clk_rate_exclusive_get(), balance with clk_rate_exclusive_put()
* Cache clk rate in axi_pwmgen_ddata
* Don't assign pwm->chip.base, do assign pwm->chip.atomic
* Relocate "unevaluatedProperties" in device tree binding
* Remove redundant calls to clk_get_rate
* Test contents of AXI_PWMGEN_REG_CORE_MAGIC instead of
arbitrary AXI_PWMGEN_TEST_DATA in AXI_PWMGEN_REG_SCRATCHPAD
* Remove redundant clk struct from axi_pwmgen_ddata
* Add self as module author
* Add major version check for IP core
Link to v1: https://lore.kernel.org/linux-pwm/[email protected]/
Drew Fustini (2):
dt-bindings: pwm: Add AXI PWM generator
pwm: Add driver for AXI PWM generator
.../bindings/pwm/adi,axi-pwmgen.yaml | 48 ++++
MAINTAINERS | 9 +
drivers/pwm/Kconfig | 13 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-axi-pwmgen.c | 248 ++++++++++++++++++
5 files changed, 319 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
create mode 100644 drivers/pwm/pwm-axi-pwmgen.c
--
2.44.0
From: Drew Fustini <[email protected]>
Add support for the Analog Devices AXI PWM Generator. This device is an
FPGA-implemented peripheral used as PWM signal generator and can be
interfaced with AXI4. The register map of this peripheral makes it
possible to configure the period and duty cycle of the output signal.
Link: https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
Co-developed-by: Sergiu Cuciurean <[email protected]>
Signed-off-by: Sergiu Cuciurean <[email protected]>
Co-developed-by: David Lechner <[email protected]>
Signed-off-by: David Lechner <[email protected]>
Signed-off-by: Drew Fustini <[email protected]>
Acked-by: Nuno Sa <[email protected]>
Co-developed-by: Trevor Gamblin <[email protected]>
Signed-off-by: Trevor Gamblin <[email protected]>
---
v5 changes:
* Address feedback for driver in v5:
* Clarify device behavior in frontmatter
* Include register name in bitfield definitions
* Use devm_clk_rate_exclusive_get() and handle error
* Squash v2 IP support from: https://lore.kernel.org/linux-pwm/[email protected]/
* Refactor driver code to support only v2 IP
* Issues were identified with v1 IP implementation, so only v2 will be
supported
* Remove axi_pwm_variant struct and usage
* Version check in axi_pwmgen_setup() left as-is to limit usage to
* only v2 IP
v4 changes:
* Address feedback for driver in v3:
* Update to use devm_pwmchip_alloc() function
* Simplify use of dev symbol in axi_pwmgen_probe
* Remove unnecessary axi_pwmgen_from_chip function and use
pwmchip_get_drvdata directly
v3 changes:
* Address feedback for driver in v2:
* Remove unnecessary blank line in axi_pwmgen_apply
* Use macros already defined in <linux/fpga/adi-axi-common.h> for
version checking
v2 changes:
* Address feedback for driver and device tree in v1:
* Use more reasonable Kconfig approach
* Use common prefixes for all functions
* Rename axi_pwmgen struct to axi_pwmgen_ddata
* Change use of "pwm" to "ddata"
* Set and check state->polarity
* Multiply safely with mul_u64_u64_div_u64()
* Improve handling of max and zero periods
* Error if clk_rate_hz > NSEC_PER_SEC
* Add "Limitations" section at top of pwm-axi-pwmgen.c
* Don't disable outputs by default
* Remove unnecessary macros for period, duty, offset
* Fix axi_pwmgen_ddata alignment
* Don't artificially limit npwm to four
* Use clk_rate_exclusive_get(), balance with clk_rate_exclusive_put()
* Cache clk rate in axi_pwmgen_ddata
* Don't assign pwm->chip.base, do assign pwm->chip.atomic
* Remove redundant calls to clk_get_rate
* Test contents of AXI_PWMGEN_REG_CORE_MAGIC instead of
arbitrary AXI_PWMGEN_TEST_DATA in AXI_PWMGEN_REG_SCRATCHPAD
* Remove redundant clk struct from axi_pwmgen_ddata
* Add self as module author
* Add major version check for IP core
---
MAINTAINERS | 1 +
drivers/pwm/Kconfig | 13 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-axi-pwmgen.c | 248 +++++++++++++++++++++++++++++++++++
4 files changed, 263 insertions(+)
create mode 100644 drivers/pwm/pwm-axi-pwmgen.c
diff --git a/MAINTAINERS b/MAINTAINERS
index d02ece54ccf6..0281ed059718 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3472,6 +3472,7 @@ L: [email protected]
S: Supported
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
+F: drivers/pwm/pwm-axi-pwmgen.c
AXXIA I2C CONTROLLER
M: Krzysztof Adamski <[email protected]>
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 1dd7921194f5..00a543de8f82 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -94,6 +94,19 @@ config PWM_ATMEL_TCB
To compile this driver as a module, choose M here: the module
will be called pwm-atmel-tcb.
+config PWM_AXI_PWMGEN
+ tristate "Analog Devices AXI PWM generator"
+ depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ This enables support for the Analog Devices AXI PWM generator.
+
+ This is a configurable PWM generator with variable pulse width and
+ period.
+
+ To compile this driver as a module, choose M here: the module will be
+ called pwm-axi-pwmgen.
+
config PWM_BCM_IPROC
tristate "iProc PWM support"
depends on ARCH_BCM_IPROC || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 90913519f11a..6964ba45c795 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_PWM_APPLE) += pwm-apple.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
+obj-$(CONFIG_PWM_AXI_PWMGEN) += pwm-axi-pwmgen.o
obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o
obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o
diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c
new file mode 100644
index 000000000000..e0bf90cc2ba3
--- /dev/null
+++ b/drivers/pwm/pwm-axi-pwmgen.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Analog Devices AXI PWM generator
+ *
+ * Copyright 2024 Analog Devices Inc.
+ * Copyright 2024 Baylibre SAS
+ *
+ * Limitations:
+ * - The writes to registers for period and duty are shadowed until
+ * LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG, at which point
+ * they take effect.
+ * - Reconfiguring a channel doesn't complete the currently running
+ * period and resets the counters of all other channels, and so very
+ * likely introduces glitches on these unrelated outputs.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - On disable, the PWM output becomes low (inactive).
+ */
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/fpga/adi-axi-common.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#define AXI_PWMGEN_REG_CORE_VERSION 0x00
+#define AXI_PWMGEN_REG_ID 0x04
+#define AXI_PWMGEN_REG_SCRATCHPAD 0x08
+#define AXI_PWMGEN_REG_CORE_MAGIC 0x0C
+#define AXI_PWMGEN_REG_CONFIG 0x10
+#define AXI_PWMGEN_REG_NPWM 0x14
+#define AXI_PWMGEN_CHX_PERIOD(ch) (0x40 + (4 * (ch)))
+#define AXI_PWMGEN_CHX_DUTY(ch) (0x80 + (4 * (ch)))
+#define AXI_PWMGEN_CHX_OFFSET(ch) (0xC0 + (4 * (ch)))
+#define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number to test during setup */
+#define AXI_PWMGEN_LOAD_CONFIG BIT(1)
+#define AXI_PWMGEN_REG_CONFIG_RESET BIT(0)
+
+struct axi_pwmgen_ddata {
+ struct regmap *regmap;
+ unsigned long clk_rate_hz;
+};
+
+static const struct regmap_config axi_pwmgen_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+};
+
+static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
+ unsigned int ch = pwm->hwpwm;
+ struct regmap *regmap = ddata->regmap;
+ u64 period_cnt, duty_cnt;
+ int ret;
+
+ if (state->polarity != PWM_POLARITY_NORMAL)
+ return -EINVAL;
+
+ if (state->enabled) {
+ period_cnt = mul_u64_u64_div_u64(state->period, ddata->clk_rate_hz, NSEC_PER_SEC);
+ if (period_cnt > UINT_MAX)
+ period_cnt = UINT_MAX;
+
+ if (period_cnt == 0)
+ return -EINVAL;
+
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), period_cnt);
+ if (ret)
+ return ret;
+
+ duty_cnt = mul_u64_u64_div_u64(state->duty_cycle, ddata->clk_rate_hz, NSEC_PER_SEC);
+ if (duty_cnt > UINT_MAX)
+ duty_cnt = UINT_MAX;
+
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0);
+ if (ret)
+ return ret;
+ }
+
+ return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG);
+}
+
+static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
+ struct regmap *regmap = ddata->regmap;
+ unsigned int ch = pwm->hwpwm;
+ u32 cnt;
+ int ret;
+
+ ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &cnt);
+ if (ret)
+ return ret;
+
+ state->enabled = cnt != 0;
+
+ state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);
+
+ ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &cnt);
+ if (ret)
+ return ret;
+
+ state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);
+
+ state->polarity = PWM_POLARITY_NORMAL;
+
+ return 0;
+}
+
+static const struct pwm_ops axi_pwmgen_pwm_ops = {
+ .apply = axi_pwmgen_apply,
+ .get_state = axi_pwmgen_get_state,
+};
+
+static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)
+{
+ int ret;
+ u32 val;
+
+ ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_MAGIC, &val);
+ if (ret)
+ return ret;
+
+ if (val != AXI_PWMGEN_REG_CORE_MAGIC_VAL)
+ return dev_err_probe(dev, -ENODEV,
+ "failed to read expected value from register: got %08x, expected %08x\n",
+ val,
+ AXI_PWMGEN_REG_CORE_MAGIC_VAL);
+
+ ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_VERSION, &val);
+ if (ret)
+ return ret;
+
+ if (ADI_AXI_PCORE_VER_MAJOR(val) != 2) {
+ return dev_err_probe(dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n",
+ ADI_AXI_PCORE_VER_MAJOR(val),
+ ADI_AXI_PCORE_VER_MINOR(val),
+ ADI_AXI_PCORE_VER_PATCH(val));
+ }
+
+ /* Enable the core */
+ ret = regmap_update_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_REG_CONFIG_RESET, 0);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(regmap, AXI_PWMGEN_REG_NPWM, &val);
+ if (ret)
+ return ret;
+
+ /* Return the number of PWMs */
+ return val;
+}
+
+static void axi_pwmgen_clk_rate_exclusive_put(void *data)
+{
+ clk_rate_exclusive_put(data);
+}
+
+static int axi_pwmgen_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
+ struct pwm_chip *chip;
+ struct axi_pwmgen_ddata *ddata;
+ struct clk *clk;
+ void __iomem *io_base;
+ int ret;
+
+ io_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(io_base))
+ return PTR_ERR(io_base);
+
+ regmap = devm_regmap_init_mmio(dev, io_base, &axi_pwmgen_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap),
+ "failed to init register map\n");
+
+ ret = axi_pwmgen_setup(regmap, dev);
+ if (ret < 0)
+ return ret;
+
+ chip = devm_pwmchip_alloc(dev, ret, sizeof(*ddata));
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+ ddata = pwmchip_get_drvdata(chip);
+ ddata->regmap = regmap;
+
+ clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
+
+ ret = devm_clk_rate_exclusive_get(dev, clk);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get exclusive rate\n");
+
+ ret = devm_add_action_or_reset(dev, axi_pwmgen_clk_rate_exclusive_put, clk);
+ if (ret)
+ return ret;
+
+ ddata->clk_rate_hz = clk_get_rate(clk);
+ if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid clock rate: %lu\n", ddata->clk_rate_hz);
+
+ chip->ops = &axi_pwmgen_pwm_ops;
+ chip->atomic = true;
+
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not add PWM chip\n");
+
+ return 0;
+}
+
+static const struct of_device_id axi_pwmgen_ids[] = {
+ { .compatible = "adi,axi-pwmgen-2.00.a" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, axi_pwmgen_ids);
+
+static struct platform_driver axi_pwmgen_driver = {
+ .driver = {
+ .name = "axi-pwmgen",
+ .of_match_table = axi_pwmgen_ids,
+ },
+ .probe = axi_pwmgen_probe,
+};
+module_platform_driver(axi_pwmgen_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Sergiu Cuciurean <[email protected]>");
+MODULE_AUTHOR("Trevor Gamblin <[email protected]>");
+MODULE_DESCRIPTION("Driver for the Analog Devices AXI PWM generator");
--
2.44.0
Hello Trevor,
thanks for your patience waiting for me to come around looking at your
patch. I only found some trivial stuff to fix this time around.
On Wed, Apr 24, 2024 at 08:58:48AM -0400, Trevor Gamblin wrote:
> diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c
> new file mode 100644
> index 000000000000..e0bf90cc2ba3
> --- /dev/null
> +++ b/drivers/pwm/pwm-axi-pwmgen.c
> @@ -0,0 +1,248 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Analog Devices AXI PWM generator
> + *
> + * Copyright 2024 Analog Devices Inc.
> + * Copyright 2024 Baylibre SAS
If there is public documentation available for the device, extra points
for a link to it here.
> [...]
> +static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)
> +{
> + int ret;
> + u32 val;
> +
> + ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_MAGIC, &val);
> + if (ret)
> + return ret;
> +
> + if (val != AXI_PWMGEN_REG_CORE_MAGIC_VAL)
> + return dev_err_probe(dev, -ENODEV,
> + "failed to read expected value from register: got %08x, expected %08x\n",
> + val,
> + AXI_PWMGEN_REG_CORE_MAGIC_VAL);
Join these two lines, please.
> + ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_VERSION, &val);
> + if (ret)
> + return ret;
> +
> + if (ADI_AXI_PCORE_VER_MAJOR(val) != 2) {
> + return dev_err_probe(dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n",
> + ADI_AXI_PCORE_VER_MAJOR(val),
> + ADI_AXI_PCORE_VER_MINOR(val),
> + ADI_AXI_PCORE_VER_PATCH(val));
> + }
> +
> + /* Enable the core */
> + ret = regmap_update_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_REG_CONFIG_RESET, 0);
> + if (ret)
> + return ret;
> +
> + ret = regmap_read(regmap, AXI_PWMGEN_REG_NPWM, &val);
> + if (ret)
> + return ret;
> +
> + /* Return the number of PWMs */
> + return val;
If the AXI_PWMGEN_REG_NPWM register contains a value >= 0x80000000, the
return value is considered a negative error code. Not sure how necessary
it is to check for this case. I'll leave that to you.
> +}
> [...]
> +static int axi_pwmgen_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct regmap *regmap;
> + struct pwm_chip *chip;
> + struct axi_pwmgen_ddata *ddata;
> + struct clk *clk;
> + void __iomem *io_base;
> + int ret;
> +
> + io_base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(io_base))
> + return PTR_ERR(io_base);
> +
> + regmap = devm_regmap_init_mmio(dev, io_base, &axi_pwmgen_regmap_config);
> + if (IS_ERR(regmap))
> + return dev_err_probe(dev, PTR_ERR(regmap),
> + "failed to init register map\n");
> +
> + ret = axi_pwmgen_setup(regmap, dev);
> + if (ret < 0)
> + return ret;
> +
> + chip = devm_pwmchip_alloc(dev, ret, sizeof(*ddata));
> + if (IS_ERR(chip))
> + return PTR_ERR(chip);
> + ddata = pwmchip_get_drvdata(chip);
> + ddata->regmap = regmap;
> +
> + clk = devm_clk_get_enabled(dev, NULL);
> + if (IS_ERR(clk))
> + return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
> +
> + ret = devm_clk_rate_exclusive_get(dev, clk);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to get exclusive rate\n");
> +
> + ret = devm_add_action_or_reset(dev, axi_pwmgen_clk_rate_exclusive_put, clk);
> + if (ret)
> + return ret;
this should be dropped as devm_clk_rate_exclusive_get() already takes
care for calling clk_rate_exclusive_put().
> + ddata->clk_rate_hz = clk_get_rate(clk);
> + if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC)
> + return dev_err_probe(dev, -EINVAL,
> + "Invalid clock rate: %lu\n", ddata->clk_rate_hz);
> +
> + chip->ops = &axi_pwmgen_pwm_ops;
> + chip->atomic = true;
> +
> + ret = devm_pwmchip_add(dev, chip);
> + if (ret)
> + return dev_err_probe(dev, ret, "could not add PWM chip\n");
> +
> + return 0;
> +}
Best regards
Uwe