Due to the recent design changes, all the mem noc clocks will be
configured by the bootloaders and it will be access protected by the TZ
firmware. Also there are no comsumers for these clocks in the kernel. So
drop these clocks from the GCC driver.
With these clocks removal, remove the gcc_apss_axi_clk_src clock as well
since no clocks uses this as a parent.
Kathiravan T (2):
clk: qcom: ipq5332: drop the mem noc clocks
clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
drivers/clk/qcom/gcc-ipq5332.c | 206 +++++++--------------------------
1 file changed, 39 insertions(+), 167 deletions(-)
--
2.34.1
With the removal of the mem noc clocks in the commit e224dc703521 ("clk:
qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the
gcc_apss_axi_clk_src clock as well, since there are no clocks uses this
clock as a parent.
Signed-off-by: Kathiravan T <[email protected]>
---
drivers/clk/qcom/gcc-ipq5332.c | 111 ++++++++++++---------------------
1 file changed, 39 insertions(+), 72 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 939925baa9eb..40d8e8d5956f 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -224,38 +224,20 @@ static const struct clk_parent_data gcc_parent_data_4[] = {
};
static const struct parent_map gcc_parent_map_5[] = {
- { P_XO, 0 },
- { P_GPLL0_OUT_MAIN, 1 },
- { P_GPLL2_OUT_AUX, 2 },
- { P_GPLL4_OUT_AUX, 3 },
- { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
- { P_GPLL0_OUT_AUX, 5 },
-};
-
-static const struct clk_parent_data gcc_parent_data_5[] = {
- { .index = DT_XO },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll2.clkr.hw },
- { .hw = &gpll4.clkr.hw },
- { .hw = &gpll0_div2.hw },
- { .hw = &gpll0.clkr.hw },
-};
-
-static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_AUX, 2 },
{ P_SLEEP_CLK, 6 },
};
-static const struct clk_parent_data gcc_parent_data_6[] = {
+static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
-static const struct parent_map gcc_parent_map_7[] = {
+static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_AUX, 2 },
@@ -263,7 +245,7 @@ static const struct parent_map gcc_parent_map_7[] = {
{ P_SLEEP_CLK, 6 },
};
-static const struct clk_parent_data gcc_parent_data_7[] = {
+static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
@@ -271,74 +253,74 @@ static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_SLEEP_CLK },
};
-static const struct parent_map gcc_parent_map_8[] = {
+static const struct parent_map gcc_parent_map_7[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_AUX, 2 },
};
-static const struct clk_parent_data gcc_parent_data_8[] = {
+static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
-static const struct parent_map gcc_parent_map_9[] = {
+static const struct parent_map gcc_parent_map_8[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
};
-static const struct clk_parent_data gcc_parent_data_9[] = {
+static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_div2.hw },
};
-static const struct parent_map gcc_parent_map_10[] = {
+static const struct parent_map gcc_parent_map_9[] = {
{ P_SLEEP_CLK, 6 },
};
-static const struct clk_parent_data gcc_parent_data_10[] = {
+static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_SLEEP_CLK },
};
-static const struct parent_map gcc_parent_map_11[] = {
+static const struct parent_map gcc_parent_map_10[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
};
-static const struct clk_parent_data gcc_parent_data_11[] = {
+static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_div2.hw },
};
-static const struct parent_map gcc_parent_map_12[] = {
+static const struct parent_map gcc_parent_map_11[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_AUX, 2 },
{ P_SLEEP_CLK, 6 },
};
-static const struct clk_parent_data gcc_parent_data_12[] = {
+static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
-static const struct parent_map gcc_parent_map_13[] = {
+static const struct parent_map gcc_parent_map_12[] = {
{ P_XO, 0 },
{ P_GPLL4_OUT_AUX, 1 },
{ P_GPLL0_OUT_MAIN, 3 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
};
-static const struct clk_parent_data gcc_parent_data_13[] = {
+static const struct clk_parent_data gcc_parent_data_12[] = {
{ .index = DT_XO },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0.clkr.hw },
@@ -371,20 +353,6 @@ static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
{ }
};
-static struct clk_rcg2 gcc_apss_axi_clk_src = {
- .cmd_rcgr = 0x24004,
- .mnd_width = 0,
- .hid_width = 5,
- .parent_map = gcc_parent_map_5,
- .freq_tbl = ftbl_gcc_apss_axi_clk_src,
- .clkr.hw.init = &(const struct clk_init_data) {
- .name = "gcc_apss_axi_clk_src",
- .parent_data = gcc_parent_data_5,
- .num_parents = ARRAY_SIZE(gcc_parent_data_5),
- .ops = &clk_rcg2_ops,
- },
-};
-
static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 1, 1, 25),
F(4800000, P_XO, 5, 0, 0),
@@ -733,12 +701,12 @@ static struct clk_rcg2 gcc_pcie_aux_clk_src = {
.cmd_rcgr = 0x28004,
.mnd_width = 16,
.hid_width = 5,
- .parent_map = gcc_parent_map_6,
+ .parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_aux_clk_src",
- .parent_data = gcc_parent_data_6,
- .num_parents = ARRAY_SIZE(gcc_parent_data_6),
+ .parent_data = gcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
@@ -810,12 +778,12 @@ static struct clk_rcg2 gcc_q6_axim_clk_src = {
.cmd_rcgr = 0x25004,
.mnd_width = 0,
.hid_width = 5,
- .parent_map = gcc_parent_map_7,
+ .parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_apss_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_axim_clk_src",
- .parent_data = gcc_parent_data_7,
- .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .parent_data = gcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
@@ -931,12 +899,12 @@ static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
.cmd_rcgr = 0x32004,
.mnd_width = 0,
.hid_width = 5,
- .parent_map = gcc_parent_map_8,
+ .parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qpic_io_macro_clk_src",
- .parent_data = gcc_parent_data_8,
- .num_parents = ARRAY_SIZE(gcc_parent_data_8),
+ .parent_data = gcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
@@ -957,12 +925,12 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x33004,
.mnd_width = 8,
.hid_width = 5,
- .parent_map = gcc_parent_map_9,
+ .parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk_src",
- .parent_data = gcc_parent_data_9,
- .num_parents = ARRAY_SIZE(gcc_parent_data_9),
+ .parent_data = gcc_parent_data_8,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -976,12 +944,12 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
.cmd_rcgr = 0x3400c,
.mnd_width = 0,
.hid_width = 5,
- .parent_map = gcc_parent_map_10,
+ .parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sleep_clk_src",
- .parent_data = gcc_parent_data_10,
- .num_parents = ARRAY_SIZE(gcc_parent_data_10),
+ .parent_data = gcc_parent_data_9,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_ops,
},
};
@@ -998,12 +966,12 @@ static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x2e004,
.mnd_width = 0,
.hid_width = 5,
- .parent_map = gcc_parent_map_11,
+ .parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_system_noc_bfdcd_clk_src",
- .parent_data = gcc_parent_data_11,
- .num_parents = ARRAY_SIZE(gcc_parent_data_11),
+ .parent_data = gcc_parent_data_10,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_ops,
},
};
@@ -1039,12 +1007,12 @@ static struct clk_rcg2 gcc_usb0_aux_clk_src = {
.cmd_rcgr = 0x2c018,
.mnd_width = 16,
.hid_width = 5,
- .parent_map = gcc_parent_map_12,
+ .parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_aux_clk_src",
- .parent_data = gcc_parent_data_12,
- .num_parents = ARRAY_SIZE(gcc_parent_data_12),
+ .parent_data = gcc_parent_data_11,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_ops,
},
};
@@ -1091,12 +1059,12 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x2c02c,
.mnd_width = 8,
.hid_width = 5,
- .parent_map = gcc_parent_map_13,
+ .parent_map = gcc_parent_map_12,
.freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_mock_utmi_clk_src",
- .parent_data = gcc_parent_data_13,
- .num_parents = ARRAY_SIZE(gcc_parent_data_13),
+ .parent_data = gcc_parent_data_12,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_rcg2_ops,
},
};
@@ -3328,7 +3296,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
[GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
- [GCC_APSS_AXI_CLK_SRC] = &gcc_apss_axi_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
--
2.34.1
On 7/10/2023 3:58 PM, Kathiravan T wrote:
> Due to the recent design changes, all the mem noc clocks will be
> configured by the bootloaders and it will be access protected by the TZ
> firmware. Also there are no comsumers for these clocks in the kernel. So
> drop these clocks from the GCC driver.
>
> With these clocks removal, remove the gcc_apss_axi_clk_src clock as well
> since no clocks uses this as a parent.
Gentle Reminder...
>
> Kathiravan T (2):
> clk: qcom: ipq5332: drop the mem noc clocks
> clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
>
> drivers/clk/qcom/gcc-ipq5332.c | 206 +++++++--------------------------
> 1 file changed, 39 insertions(+), 167 deletions(-)
>
On Mon, 10 Jul 2023 15:58:05 +0530, Kathiravan T wrote:
> Due to the recent design changes, all the mem noc clocks will be
> configured by the bootloaders and it will be access protected by the TZ
> firmware. Also there are no comsumers for these clocks in the kernel. So
> drop these clocks from the GCC driver.
>
> With these clocks removal, remove the gcc_apss_axi_clk_src clock as well
> since no clocks uses this as a parent.
>
> [...]
Applied, thanks!
[1/2] clk: qcom: ipq5332: drop the mem noc clocks
commit: 1784d031ef1f329bd362343a8fe1c083116160af
[2/2] clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
commit: 90d5c043dda7901065e9da4b23967903640fd2ea
Best regards,
--
Bjorn Andersson <[email protected]>