2022-11-19 04:48:51

by Matt Ranostay

Subject: [PATCH v6 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI

From: Aswath Govindraju <[email protected]>

Add support for two instance of OSPI in J721S2 SoC.

Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
---
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 0af242aa9816..46b3aab93c4b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -306,4 +306,44 @@ cpts@3d000 {
ti,cpts-periodic-outputs = <2>;
};
};
+
+ fss: syscon@47000000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x47000000 0x00 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47040000 0x00 0x100>,
+ <0x5 0x0000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 109 5>;
+ assigned-clocks = <&k3_clks 109 5>;
+ assigned-clock-parents = <&k3_clks 109 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47050000 0x00 0x100>,
+ <0x7 0x0000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 110 5>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ };
};
--
2.38.GIT

2022-11-21 17:21:35

by Andrew Davis

Subject: Re: [PATCH v6 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI

On 11/18/22 10:09 PM, Matt Ranostay wrote:
> From: Aswath Govindraju <[email protected]>
>
> Add support for two instance of OSPI in J721S2 SoC.
>
> Signed-off-by: Aswath Govindraju <[email protected]>
> Signed-off-by: Matt Ranostay <[email protected]>
> ---
> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> index 0af242aa9816..46b3aab93c4b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> @@ -306,4 +306,44 @@ cpts@3d000 {
> ti,cpts-periodic-outputs = <2>;
> };
> };
> +
> + fss: syscon@47000000 {
> + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";

This node is not the "ti,j721e-system-controller", and those don't have
SPI nodes in the binding, so this will have failed the dtbs_check anyway..

Should be just a "simple-bus".

Andrew

> + reg = <0x00 0x47000000 0x00 0x100>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ospi0: spi@47040000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47040000 0x00 0x100>,
> + <0x5 0x0000000 0x1 0x0000000>;
> + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 109 5>;
> + assigned-clocks = <&k3_clks 109 5>;
> + assigned-clock-parents = <&k3_clks 109 7>;
> + assigned-clock-rates = <166666666>;
> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + ospi1: spi@47050000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47050000 0x00 0x100>,
> + <0x7 0x0000000 0x1 0x0000000>;
> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 110 5>;
> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + };
> };

2022-11-22 03:26:12

by Matt Ranostay

Subject: Re: [PATCH v6 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI

On Mon, Nov 21, 2022 at 10:53:03AM -0600, Andrew Davis wrote:
> On 11/18/22 10:09 PM, Matt Ranostay wrote:
> > From: Aswath Govindraju <[email protected]>
> >
> > Add support for two instance of OSPI in J721S2 SoC.
> >
> > Signed-off-by: Aswath Govindraju <[email protected]>
> > Signed-off-by: Matt Ranostay <[email protected]>
> > ---
> > .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
> > 1 file changed, 40 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > index 0af242aa9816..46b3aab93c4b 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > @@ -306,4 +306,44 @@ cpts@3d000 {
> > ti,cpts-periodic-outputs = <2>;
> > };
> > };
> > +
> > + fss: syscon@47000000 {
> > + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
>
> This node is not the "ti,j721e-system-controller", and those don't have
> SPI nodes in the binding, so this will have failed the dtbs_check anyway..
>
> Should be just a "simple-bus".
>
> Andrew
>

Noted for next revision.

Thanks,

Matt

> > + reg = <0x00 0x47000000 0x00 0x100>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + ospi0: spi@47040000 {
> > + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> > + reg = <0x00 0x47040000 0x00 0x100>,
> > + <0x5 0x0000000 0x1 0x0000000>;
> > + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
> > + cdns,fifo-depth = <256>;
> > + cdns,fifo-width = <4>;
> > + cdns,trigger-address = <0x0>;
> > + clocks = <&k3_clks 109 5>;
> > + assigned-clocks = <&k3_clks 109 5>;
> > + assigned-clock-parents = <&k3_clks 109 7>;
> > + assigned-clock-rates = <166666666>;
> > + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + ospi1: spi@47050000 {
> > + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> > + reg = <0x00 0x47050000 0x00 0x100>,
> > + <0x7 0x0000000 0x1 0x0000000>;
> > + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
> > + cdns,fifo-depth = <256>;
> > + cdns,fifo-width = <4>;
> > + cdns,trigger-address = <0x0>;
> > + clocks = <&k3_clks 110 5>;
> > + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + };
> > };