This contains multiple fix for PCIe qcom driver.
Some optional reset and clocks were missing.
Fix a problem with no PARF programming that cause kernel lock on load.
Add support to force gen 1 speed if needed. (due to hardware limitation)
Add ipq8064 rev 2 support that use a different tx termination offset.
v5:
* Split PCI: qcom: Add ipq8064 rev2 variant and set tx term offset
v4:
* Fix grammar error across all patch subject
* Use bulk api for clks
* Program PARF only in ipq8064 SoC
* Program tx term only in ipq8064 SoC
* Drop configurable tx-dempth rx-eq
* Make added clk optional
v3:
* Fix check reported by checkpatch --strict
* Rename force_gen1 to gen
v2:
* Drop iATU programming (already done in pcie init)
* Use max-link-speed instead of force-gen1 custom definition
* Drop MRRS to 256B (Can't find a realy reason why this was suggested)
* Introduce a new variant for different revision of ipq8064
Abhishek Sahu (1):
PCI: qcom: Change duplicate PCI reset to phy reset
Ansuel Smith (9):
PCI: qcom: Add missing ipq806x clocks in PCIe driver
dt-bindings: PCI: qcom: Add missing clks
PCI: qcom: Add missing reset for ipq806x
dt-bindings: PCI: qcom: Add ext reset
PCI: qcom: Use bulk clk api and assert on error
PCI: qcom: Define some PARF params needed for ipq8064 SoC
PCI: qcom: Add support for tx term offset for rev 2.1.0
PCI: qcom: Add ipq8064 rev2 variant
dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant
Sham Muthayyan (1):
PCI: qcom: Add Force GEN1 support
.../devicetree/bindings/pci/qcom,pcie.txt | 15 +-
drivers/pci/controller/dwc/pcie-qcom.c | 171 ++++++++++++------
2 files changed, 123 insertions(+), 63 deletions(-)
--
2.25.1
Aux and Ref clk are missing in PCIe qcom driver. Add support for this
optional clks for ipq8064/apq8064 SoC.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <[email protected]>
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++----
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 5ea527a6bd9f..4bf93ab8c7a7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
struct clk *phy_clk;
+ struct clk *aux_clk;
+ struct clk *ref_clk;
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->phy_clk))
return PTR_ERR(res->phy_clk);
+ res->aux_clk = devm_clk_get_optional(dev, "aux");
+ if (IS_ERR(res->aux_clk))
+ return PTR_ERR(res->aux_clk);
+
+ res->ref_clk = devm_clk_get_optional(dev, "ref");
+ if (IS_ERR(res->ref_clk))
+ return PTR_ERR(res->ref_clk);
+
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
if (IS_ERR(res->pci_reset))
return PTR_ERR(res->pci_reset);
@@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
clk_disable_unprepare(res->phy_clk);
+ clk_disable_unprepare(res->aux_clk);
+ clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
@@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_assert_ahb;
}
+ ret = clk_prepare_enable(res->core_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable core clock\n");
+ goto err_clk_core;
+ }
+
ret = clk_prepare_enable(res->phy_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable phy clock\n");
goto err_clk_phy;
}
- ret = clk_prepare_enable(res->core_clk);
+ ret = clk_prepare_enable(res->aux_clk);
if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+ goto err_clk_aux;
+ }
+
+ ret = clk_prepare_enable(res->ref_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable ref clock\n");
+ goto err_clk_ref;
}
ret = reset_control_deassert(res->ahb_reset);
@@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return 0;
err_deassert_ahb:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
+ clk_disable_unprepare(res->ref_clk);
+err_clk_ref:
+ clk_disable_unprepare(res->aux_clk);
+err_clk_aux:
clk_disable_unprepare(res->phy_clk);
err_clk_phy:
+ clk_disable_unprepare(res->core_clk);
+err_clk_core:
clk_disable_unprepare(res->iface_clk);
err_assert_ahb:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
--
2.25.1
Document missing clks used in ipq8064 SoC.
Signed-off-by: Ansuel Smith <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 981b4de12807..becdbdc0fffa 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -90,6 +90,8 @@
Definition: Should contain the following entries
- "core" Clocks the pcie hw block
- "phy" Clocks the pcie PHY block
+ - "aux" Clocks the pcie AUX block
+ - "ref" Clocks the pcie ref block
- clock-names:
Usage: required for apq8084/ipq4019
Value type: <stringlist>
@@ -277,8 +279,10 @@
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc PCIE_A_CLK>,
<&gcc PCIE_H_CLK>,
- <&gcc PCIE_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_PHY_CLK>,
+ <&gcc PCIE_AUX_CLK>,
+ <&gcc PCIE_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
resets = <&gcc PCIE_ACLK_RESET>,
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
--
2.25.1
Rework 2.1.0 revision to use bulk clk api and fix missing assert on
reset_control_deassert error.
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 131 +++++++++----------------
1 file changed, 46 insertions(+), 85 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4dab5ef630cc..f2ea1ab6f584 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -84,12 +84,9 @@
#define DEVICE_TYPE_RC 0x4
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
+#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
struct qcom_pcie_resources_2_1_0 {
- struct clk *iface_clk;
- struct clk *core_clk;
- struct clk *phy_clk;
- struct clk *aux_clk;
- struct clk *ref_clk;
+ struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -237,25 +234,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (ret)
return ret;
- res->iface_clk = devm_clk_get(dev, "iface");
- if (IS_ERR(res->iface_clk))
- return PTR_ERR(res->iface_clk);
-
- res->core_clk = devm_clk_get(dev, "core");
- if (IS_ERR(res->core_clk))
- return PTR_ERR(res->core_clk);
-
- res->phy_clk = devm_clk_get(dev, "phy");
- if (IS_ERR(res->phy_clk))
- return PTR_ERR(res->phy_clk);
+ res->clks[0].id = "iface";
+ res->clks[1].id = "core";
+ res->clks[2].id = "phy";
+ res->clks[3].id = "aux";
+ res->clks[4].id = "ref";
- res->aux_clk = devm_clk_get_optional(dev, "aux");
- if (IS_ERR(res->aux_clk))
- return PTR_ERR(res->aux_clk);
+ /* iface, core, phy are required */
+ ret = devm_clk_bulk_get(dev, 3, res->clks);
+ if (ret < 0)
+ return ret;
- res->ref_clk = devm_clk_get_optional(dev, "ref");
- if (IS_ERR(res->ref_clk))
- return PTR_ERR(res->ref_clk);
+ /* aux, ref are optional */
+ ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
+ if (ret < 0)
+ return ret;
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
if (IS_ERR(res->pci_reset))
@@ -285,17 +278,13 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
- clk_disable_unprepare(res->phy_clk);
+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
- clk_disable_unprepare(res->iface_clk);
- clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->aux_clk);
- clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
@@ -313,36 +302,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return ret;
}
- ret = reset_control_assert(res->ahb_reset);
- if (ret) {
- dev_err(dev, "cannot assert ahb reset\n");
- goto err_assert_ahb;
- }
-
- ret = clk_prepare_enable(res->iface_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable iface clock\n");
- goto err_assert_ahb;
- }
-
- ret = clk_prepare_enable(res->core_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
- }
-
- ret = clk_prepare_enable(res->aux_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable aux clock\n");
- goto err_clk_aux;
- }
-
- ret = clk_prepare_enable(res->ref_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable ref clock\n");
- goto err_clk_ref;
- }
-
ret = reset_control_deassert(res->ahb_reset);
if (ret) {
dev_err(dev, "cannot deassert ahb reset\n");
@@ -352,48 +311,46 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
ret = reset_control_deassert(res->ext_reset);
if (ret) {
dev_err(dev, "cannot deassert ext reset\n");
- goto err_deassert_ahb;
+ goto err_deassert_ext;
}
- /* enable PCIe clocks and resets */
- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
- val &= ~BIT(0);
- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
-
- /* enable external reference clock */
- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
- val |= BIT(16);
- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
-
ret = reset_control_deassert(res->phy_reset);
if (ret) {
dev_err(dev, "cannot deassert phy reset\n");
- return ret;
+ goto err_deassert_phy;
}
ret = reset_control_deassert(res->pci_reset);
if (ret) {
dev_err(dev, "cannot deassert pci reset\n");
- return ret;
+ goto err_deassert_pci;
}
ret = reset_control_deassert(res->por_reset);
if (ret) {
dev_err(dev, "cannot deassert por reset\n");
- return ret;
+ goto err_deassert_por;
}
ret = reset_control_deassert(res->axi_reset);
if (ret) {
dev_err(dev, "cannot deassert axi reset\n");
- return ret;
+ goto err_deassert_axi;
}
- ret = clk_prepare_enable(res->phy_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable phy clock\n");
- goto err_deassert_ahb;
- }
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+ if (ret)
+ goto err_clks;
+
+ /* enable PCIe clocks and resets */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+ /* enable external reference clock */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
+ val |= BIT(16);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
/* wait for clock acquisition */
usleep_range(1000, 1500);
@@ -407,15 +364,19 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return 0;
+err_clks:
+ reset_control_assert(res->axi_reset);
+err_deassert_axi:
+ reset_control_assert(res->por_reset);
+err_deassert_por:
+ reset_control_assert(res->pci_reset);
+err_deassert_pci:
+ reset_control_assert(res->phy_reset);
+err_deassert_phy:
+ reset_control_assert(res->ext_reset);
+err_deassert_ext:
+ reset_control_assert(res->ahb_reset);
err_deassert_ahb:
- clk_disable_unprepare(res->ref_clk);
-err_clk_ref:
- clk_disable_unprepare(res->aux_clk);
-err_clk_aux:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
- clk_disable_unprepare(res->iface_clk);
-err_assert_ahb:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
return ret;
--
2.25.1
Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
needed on some ipq8064 based device (Netgear R7800 for example). Without
this the system locks on kernel load.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Ansuel Smith <[email protected]>
Cc: [email protected] # v4.5+
Reviewed-by: Rob Herring <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f2ea1ab6f584..f5398b0d270c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -46,6 +46,9 @@
#define PCIE20_PARF_PHY_CTRL 0x40
#define PCIE20_PARF_PHY_REFCLK 0x4C
+#define PHY_REFCLK_SSP_EN BIT(16)
+#define PHY_REFCLK_USE_PAD BIT(12)
+
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
@@ -77,6 +80,18 @@
#define DBI_RO_WR_EN 1
#define PERST_DELAY_US 1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH 0x34
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
+
+#define PCIE20_PARF_PCS_SWING 0x38
+#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
+#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
+
+#define PCIE20_PARF_CONFIG_BITS 0x50
+#define PHY_RX0_EQ(x) ((x) << 24)
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
@@ -293,6 +308,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
+ struct device_node *node = dev->of_node;
u32 val;
int ret;
@@ -347,6 +363,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
val &= ~BIT(0);
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
+ writel(PCS_SWING_TX_SWING_FULL(120) |
+ PCS_SWING_TX_SWING_LOW(120),
+ pcie->parf + PCIE20_PARF_PCS_SWING);
+ writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
+ }
+
/* enable external reference clock */
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
val |= BIT(16);
--
2.25.1
Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit
different offset based on the revision.
Signed-off-by: Ansuel Smith <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 2cd6d1456210..259b627bf890 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -366,7 +366,8 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
val &= ~BIT(0);
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
- if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
+ of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
@@ -1464,6 +1465,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
--
2.25.1
From: Sham Muthayyan <[email protected]>
Add Force GEN1 support needed in some ipq8064 board that needs to limit
some PCIe line to gen1 for some hardware limitation. This is set by the
max-link-speed binding and needed by some soc based on ipq8064. (for
example Netgear R7800 router)
Signed-off-by: Sham Muthayyan <[email protected]>
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 259b627bf890..0ce15d53c46e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -27,6 +27,7 @@
#include <linux/slab.h>
#include <linux/types.h>
+#include "../../pci.h"
#include "pcie-designware.h"
#define PCIE20_PARF_SYS_CTRL 0x00
@@ -99,6 +100,8 @@
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
+
#define DEVICE_TYPE_RC 0x4
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
@@ -195,6 +198,7 @@ struct qcom_pcie {
struct phy *phy;
struct gpio_desc *reset;
const struct qcom_pcie_ops *ops;
+ int gen;
};
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
@@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
/* wait for clock acquisition */
usleep_range(1000, 1500);
+ if (pcie->gen == 1) {
+ val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+ val |= 1;
+ writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+ }
/* Set the Max TLP size to 2K, instead of using default of 4K */
writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
@@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
goto err_pm_runtime_put;
}
+ pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
+ if (pcie->gen < 0)
+ pcie->gen = 2;
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
pcie->parf = devm_ioremap_resource(dev, res);
if (IS_ERR(pcie->parf)) {
--
2.25.1
From: Abhishek Sahu <[email protected]>
The deinit issues reset_control_assert for PCI twice and does not contain
phy reset.
Signed-off-by: Abhishek Sahu <[email protected]>
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4bf93ab8c7a7..4512c2c5f61c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -280,14 +280,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
+ clk_disable_unprepare(res->phy_clk);
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
- reset_control_assert(res->pci_reset);
+ reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->phy_clk);
clk_disable_unprepare(res->aux_clk);
clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
@@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_clk_core;
}
- ret = clk_prepare_enable(res->phy_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable phy clock\n");
- goto err_clk_phy;
- }
-
ret = clk_prepare_enable(res->aux_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable aux clock\n");
@@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return ret;
}
+ ret = clk_prepare_enable(res->phy_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable phy clock\n");
+ goto err_deassert_ahb;
+ }
+
/* wait for clock acquisition */
usleep_range(1000, 1500);
@@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
err_clk_ref:
clk_disable_unprepare(res->aux_clk);
err_clk_aux:
- clk_disable_unprepare(res->phy_clk);
-err_clk_phy:
clk_disable_unprepare(res->core_clk);
err_clk_core:
clk_disable_unprepare(res->iface_clk);
--
2.25.1
Add tx term offset support to pcie qcom driver need in some revision of
the ipq806x SoC. Ipq8064 needs tx term offset set to 7.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <[email protected]>
Signed-off-by: Ansuel Smith <[email protected]>
Cc: [email protected] # v4.5+
---
drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f5398b0d270c..2cd6d1456210 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -45,6 +45,9 @@
#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
#define PCIE20_PARF_PHY_CTRL 0x40
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
+
#define PCIE20_PARF_PHY_REFCLK 0x4C
#define PHY_REFCLK_SSP_EN BIT(16)
#define PHY_REFCLK_USE_PAD BIT(12)
@@ -374,9 +377,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
}
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ /* set TX termination offset */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
+ val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ }
+
/* enable external reference clock */
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
- val |= BIT(16);
+ val &= ~PHY_REFCLK_USE_PAD;
+ val |= PHY_REFCLK_SSP_EN;
writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
/* wait for clock acquisition */
--
2.25.1
Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset.
In ipq8064 phy_tx0_term_offset is 7. In ipq8064 v2 other SoC it's set to 0
by default.
Signed-off-by: Ansuel Smith <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 6efcef040741..02bc81bb8b2d 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -5,6 +5,7 @@
Value type: <stringlist>
Definition: Value should contain
- "qcom,pcie-ipq8064" for ipq8064
+ - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
- "qcom,pcie-apq8064" for apq8064
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
--
2.25.1
Document ext reset used in ipq8064 SoC by qcom PCIe driver.
Signed-off-by: Ansuel Smith <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index becdbdc0fffa..6efcef040741 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -179,6 +179,7 @@
- "pwr" PWR reset
- "ahb" AHB reset
- "phy_ahb" PHY AHB reset
+ - "ext" EXT reset
- reset-names:
Usage: required for ipq8074
@@ -287,8 +288,9 @@
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
<&gcc PCIE_PCI_RESET>,
- <&gcc PCIE_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_PHY_RESET>,
+ <&gcc PCIE_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
pinctrl-0 = <&pcie_pins_default>;
pinctrl-names = "default";
};
--
2.25.1
Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <[email protected]>
Signed-off-by: Ansuel Smith <[email protected]>
Cc: [email protected] # v4.5+
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4512c2c5f61c..4dab5ef630cc 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 {
struct reset_control *ahb_reset;
struct reset_control *por_reset;
struct reset_control *phy_reset;
+ struct reset_control *ext_reset;
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
};
@@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->por_reset))
return PTR_ERR(res->por_reset);
+ res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
+ if (IS_ERR(res->ext_reset))
+ return PTR_ERR(res->ext_reset);
+
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
return PTR_ERR_OR_ZERO(res->phy_reset);
}
@@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
+ reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
@@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_deassert_ahb;
}
+ ret = reset_control_deassert(res->ext_reset);
+ if (ret) {
+ dev_err(dev, "cannot deassert ext reset\n");
+ goto err_deassert_ahb;
+ }
+
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
val &= ~BIT(0);
--
2.25.1
On Tue, Jun 02, 2020 at 01:53:52PM +0200, Ansuel Smith wrote:
> From: Sham Muthayyan <[email protected]>
>
> Add Force GEN1 support needed in some ipq8064 board that needs to limit
> some PCIe line to gen1 for some hardware limitation. This is set by the
> max-link-speed binding and needed by some soc based on ipq8064. (for
> example Netgear R7800 router)
>
> Signed-off-by: Sham Muthayyan <[email protected]>
> Signed-off-by: Ansuel Smith <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 259b627bf890..0ce15d53c46e 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -27,6 +27,7 @@
> #include <linux/slab.h>
> #include <linux/types.h>
>
> +#include "../../pci.h"
> #include "pcie-designware.h"
>
> #define PCIE20_PARF_SYS_CTRL 0x00
> @@ -99,6 +100,8 @@
> #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
> #define SLV_ADDR_SPACE_SZ 0x10000000
>
> +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
> +
> #define DEVICE_TYPE_RC 0x4
>
> #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
> @@ -195,6 +198,7 @@ struct qcom_pcie {
> struct phy *phy;
> struct gpio_desc *reset;
> const struct qcom_pcie_ops *ops;
> + int gen;
> };
>
> #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
> @@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> /* wait for clock acquisition */
> usleep_range(1000, 1500);
>
> + if (pcie->gen == 1) {
> + val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
> + val |= 1;
Is this the same bit that's visible in config space as
PCI_EXP_LNKSTA_CLS_2_5GB? Why not use that #define?
There are a bunch of other #defines in this file that look like
redefinitions of standard things:
#define PCIE20_COMMAND_STATUS 0x04
Looks like PCI_COMMAND
#define CMD_BME_VAL 0x4
Looks like PCI_COMMAND_MASTER
#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
Looks like (PCIE20_CAP + PCI_EXP_DEVCTL2)
#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
Looks like PCI_EXP_DEVCTL2_COMP_TMOUT_DIS
#define PCIE20_CAP 0x70
This one is obviously device-specific
#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
Looks like (PCIE20_CAP + PCI_EXP_LNKCAP)
#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11))
Looks like PCI_EXP_LNKCAP_ASPMS
#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
#define PCIE_CAP_LINK1_VAL 0x2FD7F
This looks like PCIE20_CAP_LINK_1 should be (PCIE20_CAP +
PCI_EXP_SLTCAP), but "CAP_LINK_1" doesn't sound like the Slot
Capabilities register, and I don't know what PCIE_CAP_LINK1_VAL
means.
> + writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
> + }
>
> /* Set the Max TLP size to 2K, instead of using default of 4K */
> writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
> @@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> goto err_pm_runtime_put;
> }
>
> + pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
> + if (pcie->gen < 0)
> + pcie->gen = 2;
> +
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
> pcie->parf = devm_ioremap_resource(dev, res);
> if (IS_ERR(pcie->parf)) {
> --
> 2.25.1
>
> On Tue, Jun 02, 2020 at 01:53:52PM +0200, Ansuel Smith wrote:
> > From: Sham Muthayyan <[email protected]>
> >
> > Add Force GEN1 support needed in some ipq8064 board that needs to
> limit
> > some PCIe line to gen1 for some hardware limitation. This is set by the
> > max-link-speed binding and needed by some soc based on ipq8064. (for
> > example Netgear R7800 router)
> >
> > Signed-off-by: Sham Muthayyan <[email protected]>
> > Signed-off-by: Ansuel Smith <[email protected]>
> > Reviewed-by: Rob Herring <[email protected]>
> > ---
> > drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
> b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 259b627bf890..0ce15d53c46e 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -27,6 +27,7 @@
> > #include <linux/slab.h>
> > #include <linux/types.h>
> >
> > +#include "../../pci.h"
> > #include "pcie-designware.h"
> >
> > #define PCIE20_PARF_SYS_CTRL 0x00
> > @@ -99,6 +100,8 @@
> > #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
> > #define SLV_ADDR_SPACE_SZ 0x10000000
> >
> > +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
> > +
> > #define DEVICE_TYPE_RC 0x4
> >
> > #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
> > @@ -195,6 +198,7 @@ struct qcom_pcie {
> > struct phy *phy;
> > struct gpio_desc *reset;
> > const struct qcom_pcie_ops *ops;
> > + int gen;
> > };
> >
> > #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
> > @@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct
> qcom_pcie *pcie)
> > /* wait for clock acquisition */
> > usleep_range(1000, 1500);
> >
> > + if (pcie->gen == 1) {
> > + val = readl(pci->dbi_base +
> PCIE20_LNK_CONTROL2_LINK_STATUS2);
> > + val |= 1;
>
> Is this the same bit that's visible in config space as
> PCI_EXP_LNKSTA_CLS_2_5GB? Why not use that #define?
>
> There are a bunch of other #defines in this file that look like
> redefinitions of standard things:
>
> #define PCIE20_COMMAND_STATUS 0x04
> Looks like PCI_COMMAND
>
> #define CMD_BME_VAL 0x4
> Looks like PCI_COMMAND_MASTER
>
> #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
> Looks like (PCIE20_CAP + PCI_EXP_DEVCTL2)
>
> #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
> Looks like PCI_EXP_DEVCTL2_COMP_TMOUT_DIS
>
> #define PCIE20_CAP 0x70
> This one is obviously device-specific
>
> #define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
> Looks like (PCIE20_CAP + PCI_EXP_LNKCAP)
>
> #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) |
> BIT(11))
> Looks like PCI_EXP_LNKCAP_ASPMS
>
> #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
> #define PCIE_CAP_LINK1_VAL 0x2FD7F
> This looks like PCIE20_CAP_LINK_1 should be (PCIE20_CAP +
> PCI_EXP_SLTCAP), but "CAP_LINK_1" doesn't sound like the Slot
> Capabilities register, and I don't know what PCIE_CAP_LINK1_VAL
> means.
>
The define are used by ipq8074 and I really can't test the changes. Anyway
it shouldn't make a difference use the define instead of the custom value so
a patch should not harm anything... Problem is the last 2 define that we
really
don't know what they are about... How should I proceed? Change only the
value related to PCI_EXP_LNKSTA_CLS_2_5GB or change all the other except the
last 2?
> > + writel(val, pci->dbi_base +
> PCIE20_LNK_CONTROL2_LINK_STATUS2);
> > + }
> >
> > /* Set the Max TLP size to 2K, instead of using default of 4K */
> > writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
> > @@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct
> platform_device *pdev)
> > goto err_pm_runtime_put;
> > }
> >
> > + pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
> > + if (pcie->gen < 0)
> > + pcie->gen = 2;
> > +
> > res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "parf");
> > pcie->parf = devm_ioremap_resource(dev, res);
> > if (IS_ERR(pcie->parf)) {
> > --
> > 2.25.1
> >
[+cc Varada]
On Tue, Jun 02, 2020 at 07:07:27PM +0200, [email protected] wrote:
> > On Tue, Jun 02, 2020 at 01:53:52PM +0200, Ansuel Smith wrote:
> > > From: Sham Muthayyan <[email protected]>
> > >
> > > Add Force GEN1 support needed in some ipq8064 board that needs to
> > limit
> > > some PCIe line to gen1 for some hardware limitation. This is set by the
> > > max-link-speed binding and needed by some soc based on ipq8064. (for
> > > example Netgear R7800 router)
> > >
> > > Signed-off-by: Sham Muthayyan <[email protected]>
> > > Signed-off-by: Ansuel Smith <[email protected]>
> > > Reviewed-by: Rob Herring <[email protected]>
> > > ---
> > > drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
> > > 1 file changed, 13 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
> > b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 259b627bf890..0ce15d53c46e 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -27,6 +27,7 @@
> > > #include <linux/slab.h>
> > > #include <linux/types.h>
> > >
> > > +#include "../../pci.h"
> > > #include "pcie-designware.h"
> > >
> > > #define PCIE20_PARF_SYS_CTRL 0x00
> > > @@ -99,6 +100,8 @@
> > > #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
> > > #define SLV_ADDR_SPACE_SZ 0x10000000
> > >
> > > +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
> > > +
> > > #define DEVICE_TYPE_RC 0x4
> > >
> > > #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
> > > @@ -195,6 +198,7 @@ struct qcom_pcie {
> > > struct phy *phy;
> > > struct gpio_desc *reset;
> > > const struct qcom_pcie_ops *ops;
> > > + int gen;
> > > };
> > >
> > > #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
> > > @@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct
> > qcom_pcie *pcie)
> > > /* wait for clock acquisition */
> > > usleep_range(1000, 1500);
> > >
> > > + if (pcie->gen == 1) {
> > > + val = readl(pci->dbi_base +
> > PCIE20_LNK_CONTROL2_LINK_STATUS2);
> > > + val |= 1;
> >
> > Is this the same bit that's visible in config space as
> > PCI_EXP_LNKSTA_CLS_2_5GB? Why not use that #define?
> >
> > There are a bunch of other #defines in this file that look like
> > redefinitions of standard things:
> >
> > #define PCIE20_COMMAND_STATUS 0x04
> > Looks like PCI_COMMAND
> >
> > #define CMD_BME_VAL 0x4
> > Looks like PCI_COMMAND_MASTER
> >
> > #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
> > Looks like (PCIE20_CAP + PCI_EXP_DEVCTL2)
> >
> > #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
> > Looks like PCI_EXP_DEVCTL2_COMP_TMOUT_DIS
> >
> > #define PCIE20_CAP 0x70
> > This one is obviously device-specific
> >
> > #define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
> > Looks like (PCIE20_CAP + PCI_EXP_LNKCAP)
> >
> > #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) |
> > BIT(11))
> > Looks like PCI_EXP_LNKCAP_ASPMS
> >
> > #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
> > #define PCIE_CAP_LINK1_VAL 0x2FD7F
> > This looks like PCIE20_CAP_LINK_1 should be (PCIE20_CAP +
> > PCI_EXP_SLTCAP), but "CAP_LINK_1" doesn't sound like the Slot
> > Capabilities register, and I don't know what PCIE_CAP_LINK1_VAL
> > means.
>
> The define are used by ipq8074 and I really can't test the changes.
> Anyway it shouldn't make a difference use the define instead of the
> custom value so a patch should not harm anything... Problem is the
> last 2 define that we really don't know what they are about... How
> should I proceed? Change only the value related to
> PCI_EXP_LNKSTA_CLS_2_5GB or change all the other except the last 2?
I personally would change all the ones I mentioned above (in a
separate patch from the one that adds "max-link-speed" support).
Testing isn't a big deal because changing the #defines shouldn't
change the generated code at all.
PCIE20_CAP_LINK_1 / PCIE_CAP_LINK1_VAL looks like a potential bug or
at least a very misleading name. I wouldn't touch it unless we can
figure out what's going on.
Looks like most of this was added by 5d76117f070d ("PCI: qcom: Add
support for IPQ8074 PCIe controller"). Shame on me for not asking
these questions at the time.
Sham, Varada, can you shed any light on PCIE20_CAP_LINK_1 and
PCIE_CAP_LINK1_VAL?
> > > + writel(val, pci->dbi_base +
> > PCIE20_LNK_CONTROL2_LINK_STATUS2);
> > > + }
> > >
> > > /* Set the Max TLP size to 2K, instead of using default of 4K */
> > > writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
> > > @@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct
> > platform_device *pdev)
> > > goto err_pm_runtime_put;
> > > }
> > >
> > > + pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
> > > + if (pcie->gen < 0)
> > > + pcie->gen = 2;
> > > +
> > > res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > "parf");
> > > pcie->parf = devm_ioremap_resource(dev, res);
> > > if (IS_ERR(pcie->parf)) {
> > > --
> > > 2.25.1
> > >
>
Hi,
On 6/2/20 2:53 PM, Ansuel Smith wrote:
> Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
> needed on some ipq8064 based device (Netgear R7800 for example). Without
> this the system locks on kernel load.
>
> Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
> Signed-off-by: Ansuel Smith <[email protected]>
> Cc: [email protected] # v4.5+
> Reviewed-by: Rob Herring <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index f2ea1ab6f584..f5398b0d270c 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -46,6 +46,9 @@
>
> #define PCIE20_PARF_PHY_CTRL 0x40
> #define PCIE20_PARF_PHY_REFCLK 0x4C
> +#define PHY_REFCLK_SSP_EN BIT(16)
> +#define PHY_REFCLK_USE_PAD BIT(12)
These two are not used in the patch, please move it in 08/11.
> +
> #define PCIE20_PARF_DBI_BASE_ADDR 0x168
> #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
> #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
> @@ -77,6 +80,18 @@
> #define DBI_RO_WR_EN 1
>
> #define PERST_DELAY_US 1000
> +/* PARF registers */
> +#define PCIE20_PARF_PCS_DEEMPH 0x34
> +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
> +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
> +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
> +
> +#define PCIE20_PARF_PCS_SWING 0x38
> +#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
> +#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
> +
> +#define PCIE20_PARF_CONFIG_BITS 0x50
> +#define PHY_RX0_EQ(x) ((x) << 24)
>
> #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
> #define SLV_ADDR_SPACE_SZ 0x10000000
> @@ -293,6 +308,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
> struct dw_pcie *pci = pcie->pci;
> struct device *dev = pci->dev;
> + struct device_node *node = dev->of_node;
> u32 val;
> int ret;
>
> @@ -347,6 +363,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> val &= ~BIT(0);
> writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>
> + if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
> + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
> + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
> + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
> + pcie->parf + PCIE20_PARF_PCS_DEEMPH);
> + writel(PCS_SWING_TX_SWING_FULL(120) |
> + PCS_SWING_TX_SWING_LOW(120),
> + pcie->parf + PCIE20_PARF_PCS_SWING);
Please fix the indentations above.
> + writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
> + }
> +
> /* enable external reference clock */
> val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
> val |= BIT(16);
>
--
regards,
Stan
> -----Messaggio originale-----
> Da: Bjorn Helgaas <[email protected]>
> Inviato: marted? 2 giugno 2020 19:28
> A: [email protected]
> Cc: 'Rob Herring' <[email protected]>; 'Sham Muthayyan'
> <[email protected]>; 'Rob Herring' <[email protected]>; 'Andy
> Gross' <[email protected]>; 'Bjorn Andersson'
> <[email protected]>; 'Bjorn Helgaas' <[email protected]>;
> 'Mark Rutland' <[email protected]>; 'Stanimir Varbanov'
> <[email protected]>; 'Lorenzo Pieralisi'
> <[email protected]>; 'Andrew Murray'
> <[email protected]>; 'Philipp Zabel'
> <[email protected]>; [email protected]; linux-
> [email protected]; [email protected]; linux-
> [email protected]; Varadarajan Narayanan <[email protected]>
> Oggetto: Re: R: [PATCH v5 11/11] PCI: qcom: Add Force GEN1 support
>
> [+cc Varada]
>
> On Tue, Jun 02, 2020 at 07:07:27PM +0200, [email protected]
> wrote:
> > > On Tue, Jun 02, 2020 at 01:53:52PM +0200, Ansuel Smith wrote:
> > > > From: Sham Muthayyan <[email protected]>
> > > >
> > > > Add Force GEN1 support needed in some ipq8064 board that needs to
> > > limit
> > > > some PCIe line to gen1 for some hardware limitation. This is set by
the
> > > > max-link-speed binding and needed by some soc based on ipq8064.
> (for
> > > > example Netgear R7800 router)
> > > >
> > > > Signed-off-by: Sham Muthayyan <[email protected]>
> > > > Signed-off-by: Ansuel Smith <[email protected]>
> > > > Reviewed-by: Rob Herring <[email protected]>
> > > > ---
> > > > drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
> > > > 1 file changed, 13 insertions(+)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
> > > b/drivers/pci/controller/dwc/pcie-qcom.c
> > > > index 259b627bf890..0ce15d53c46e 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > > @@ -27,6 +27,7 @@
> > > > #include <linux/slab.h>
> > > > #include <linux/types.h>
> > > >
> > > > +#include "../../pci.h"
> > > > #include "pcie-designware.h"
> > > >
> > > > #define PCIE20_PARF_SYS_CTRL 0x00
> > > > @@ -99,6 +100,8 @@
> > > > #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
> > > > #define SLV_ADDR_SPACE_SZ 0x10000000
> > > >
> > > > +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
> > > > +
> > > > #define DEVICE_TYPE_RC 0x4
> > > >
> > > > #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
> > > > @@ -195,6 +198,7 @@ struct qcom_pcie {
> > > > struct phy *phy;
> > > > struct gpio_desc *reset;
> > > > const struct qcom_pcie_ops *ops;
> > > > + int gen;
> > > > };
> > > >
> > > > #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
> > > > @@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct
> > > qcom_pcie *pcie)
> > > > /* wait for clock acquisition */
> > > > usleep_range(1000, 1500);
> > > >
> > > > + if (pcie->gen == 1) {
> > > > + val = readl(pci->dbi_base +
> > > PCIE20_LNK_CONTROL2_LINK_STATUS2);
> > > > + val |= 1;
> > >
> > > Is this the same bit that's visible in config space as
> > > PCI_EXP_LNKSTA_CLS_2_5GB? Why not use that #define?
> > >
> > > There are a bunch of other #defines in this file that look like
> > > redefinitions of standard things:
> > >
> > > #define PCIE20_COMMAND_STATUS 0x04
> > > Looks like PCI_COMMAND
> > >
> > > #define CMD_BME_VAL 0x4
> > > Looks like PCI_COMMAND_MASTER
> > >
> > > #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
> > > Looks like (PCIE20_CAP + PCI_EXP_DEVCTL2)
> > >
> > > #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
> > > Looks like PCI_EXP_DEVCTL2_COMP_TMOUT_DIS
> > >
> > > #define PCIE20_CAP 0x70
> > > This one is obviously device-specific
> > >
> > > #define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
> > > Looks like (PCIE20_CAP + PCI_EXP_LNKCAP)
> > >
> > > #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) |
> > > BIT(11))
> > > Looks like PCI_EXP_LNKCAP_ASPMS
> > >
> > > #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
> > > #define PCIE_CAP_LINK1_VAL 0x2FD7F
> > > This looks like PCIE20_CAP_LINK_1 should be (PCIE20_CAP +
> > > PCI_EXP_SLTCAP), but "CAP_LINK_1" doesn't sound like the Slot
> > > Capabilities register, and I don't know what PCIE_CAP_LINK1_VAL
> > > means.
> >
> > The define are used by ipq8074 and I really can't test the changes.
> > Anyway it shouldn't make a difference use the define instead of the
> > custom value so a patch should not harm anything... Problem is the
> > last 2 define that we really don't know what they are about... How
> > should I proceed? Change only the value related to
> > PCI_EXP_LNKSTA_CLS_2_5GB or change all the other except the last 2?
>
> I personally would change all the ones I mentioned above (in a
> separate patch from the one that adds "max-link-speed" support).
> Testing isn't a big deal because changing the #defines shouldn't
> change the generated code at all.
>
> PCIE20_CAP_LINK_1 / PCIE_CAP_LINK1_VAL looks like a potential bug or
> at least a very misleading name. I wouldn't touch it unless we can
> figure out what's going on.
>
> Looks like most of this was added by 5d76117f070d ("PCI: qcom: Add
> support for IPQ8074 PCIe controller"). Shame on me for not asking
> these questions at the time.
>
> Sham, Varada, can you shed any light on PCIE20_CAP_LINK_1 and
> PCIE_CAP_LINK1_VAL?
>
Still no response. Should I push a v6 with this fix and leave the unknown
params
as they are?
> > > > + writel(val, pci->dbi_base +
> > > PCIE20_LNK_CONTROL2_LINK_STATUS2);
> > > > + }
> > > >
> > > > /* Set the Max TLP size to 2K, instead of using default of
4K */
> > > > writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
> > > > @@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct
> > > platform_device *pdev)
> > > > goto err_pm_runtime_put;
> > > > }
> > > >
> > > > + pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
> > > > + if (pcie->gen < 0)
> > > > + pcie->gen = 2;
> > > > +
> > > > res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > "parf");
> > > > pcie->parf = devm_ioremap_resource(dev, res);
> > > > if (IS_ERR(pcie->parf)) {
> > > > --
> > > > 2.25.1
> > > >
> >
On Tue, Jun 09, 2020 at 04:48:51PM +0200, [email protected] wrote:
> > -----Messaggio originale-----
> > Da: Bjorn Helgaas <[email protected]>
> > Inviato: marted? 2 giugno 2020 19:28
> > A: [email protected]
> > Cc: 'Rob Herring' <[email protected]>; 'Sham Muthayyan'
> > <[email protected]>; 'Rob Herring' <[email protected]>; 'Andy
> > Gross' <[email protected]>; 'Bjorn Andersson'
> > <[email protected]>; 'Bjorn Helgaas' <[email protected]>;
> > 'Mark Rutland' <[email protected]>; 'Stanimir Varbanov'
> > <[email protected]>; 'Lorenzo Pieralisi'
> > <[email protected]>; 'Andrew Murray'
> > <[email protected]>; 'Philipp Zabel'
> > <[email protected]>; [email protected]; linux-
> > [email protected]; [email protected]; linux-
> > [email protected]; Varadarajan Narayanan <[email protected]>
> > Oggetto: Re: R: [PATCH v5 11/11] PCI: qcom: Add Force GEN1 support
> >
> > [+cc Varada]
> >
> > On Tue, Jun 02, 2020 at 07:07:27PM +0200, [email protected]
> > wrote:
> > > > On Tue, Jun 02, 2020 at 01:53:52PM +0200, Ansuel Smith wrote:
> > > > > From: Sham Muthayyan <[email protected]>
> > > > >
> > > > > Add Force GEN1 support needed in some ipq8064 board that needs to
> > > > limit
> > > > > some PCIe line to gen1 for some hardware limitation. This is set by
> the
> > > > > max-link-speed binding and needed by some soc based on ipq8064.
> > (for
> > > > > example Netgear R7800 router)
> > > > >
> > > > > Signed-off-by: Sham Muthayyan <[email protected]>
> > > > > Signed-off-by: Ansuel Smith <[email protected]>
> > > > > Reviewed-by: Rob Herring <[email protected]>
> > > > > ---
> > > > > drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
> > > > > 1 file changed, 13 insertions(+)
> > > > >
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
> > > > b/drivers/pci/controller/dwc/pcie-qcom.c
> > > > > index 259b627bf890..0ce15d53c46e 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > > > @@ -27,6 +27,7 @@
> > > > > #include <linux/slab.h>
> > > > > #include <linux/types.h>
> > > > >
> > > > > +#include "../../pci.h"
> > > > > #include "pcie-designware.h"
> > > > >
> > > > > #define PCIE20_PARF_SYS_CTRL 0x00
> > > > > @@ -99,6 +100,8 @@
> > > > > #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
> > > > > #define SLV_ADDR_SPACE_SZ 0x10000000
> > > > >
> > > > > +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
> > > > > +
> > > > > #define DEVICE_TYPE_RC 0x4
> > > > >
> > > > > #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
> > > > > @@ -195,6 +198,7 @@ struct qcom_pcie {
> > > > > struct phy *phy;
> > > > > struct gpio_desc *reset;
> > > > > const struct qcom_pcie_ops *ops;
> > > > > + int gen;
> > > > > };
> > > > >
> > > > > #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
> > > > > @@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct
> > > > qcom_pcie *pcie)
> > > > > /* wait for clock acquisition */
> > > > > usleep_range(1000, 1500);
> > > > >
> > > > > + if (pcie->gen == 1) {
> > > > > + val = readl(pci->dbi_base +
> > > > PCIE20_LNK_CONTROL2_LINK_STATUS2);
> > > > > + val |= 1;
> > > >
> > > > Is this the same bit that's visible in config space as
> > > > PCI_EXP_LNKSTA_CLS_2_5GB? Why not use that #define?
> > > >
> > > > There are a bunch of other #defines in this file that look like
> > > > redefinitions of standard things:
> > > >
> > > > #define PCIE20_COMMAND_STATUS 0x04
> > > > Looks like PCI_COMMAND
> > > >
> > > > #define CMD_BME_VAL 0x4
> > > > Looks like PCI_COMMAND_MASTER
> > > >
> > > > #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
> > > > Looks like (PCIE20_CAP + PCI_EXP_DEVCTL2)
> > > >
> > > > #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
> > > > Looks like PCI_EXP_DEVCTL2_COMP_TMOUT_DIS
> > > >
> > > > #define PCIE20_CAP 0x70
> > > > This one is obviously device-specific
> > > >
> > > > #define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
> > > > Looks like (PCIE20_CAP + PCI_EXP_LNKCAP)
> > > >
> > > > #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) |
> > > > BIT(11))
> > > > Looks like PCI_EXP_LNKCAP_ASPMS
> > > >
> > > > #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
> > > > #define PCIE_CAP_LINK1_VAL 0x2FD7F
> > > > This looks like PCIE20_CAP_LINK_1 should be (PCIE20_CAP +
> > > > PCI_EXP_SLTCAP), but "CAP_LINK_1" doesn't sound like the Slot
> > > > Capabilities register, and I don't know what PCIE_CAP_LINK1_VAL
> > > > means.
> > >
> > > The define are used by ipq8074 and I really can't test the changes.
> > > Anyway it shouldn't make a difference use the define instead of the
> > > custom value so a patch should not harm anything... Problem is the
> > > last 2 define that we really don't know what they are about... How
> > > should I proceed? Change only the value related to
> > > PCI_EXP_LNKSTA_CLS_2_5GB or change all the other except the last 2?
> >
> > I personally would change all the ones I mentioned above (in a
> > separate patch from the one that adds "max-link-speed" support).
> > Testing isn't a big deal because changing the #defines shouldn't
> > change the generated code at all.
> >
> > PCIE20_CAP_LINK_1 / PCIE_CAP_LINK1_VAL looks like a potential bug or
> > at least a very misleading name. I wouldn't touch it unless we can
> > figure out what's going on.
> >
> > Looks like most of this was added by 5d76117f070d ("PCI: qcom: Add
> > support for IPQ8074 PCIe controller"). Shame on me for not asking
> > these questions at the time.
> >
> > Sham, Varada, can you shed any light on PCIE20_CAP_LINK_1 and
> > PCIE_CAP_LINK1_VAL?
> >
>
> Still no response. Should I push a v6 with this fix and leave the
> unknown params as they are?
Yep, that sounds good to me.