Add documentation to describe StarFive System Controller Registers.
Signed-off-by: William Qiu <[email protected]>
---
.../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
MAINTAINERS | 5 +++
2 files changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
new file mode 100644
index 000000000000..ae7f1d6916af
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC system controller
+
+maintainers:
+ - William Qiu <[email protected]>
+
+description: |
+ The StarFive JH7110 SoC system controller provides register information such
+ as offset, mask and shift to configure related modules such as MMC and PCIe.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - starfive,jh7110-aon-syscon
+ - starfive,jh7110-stg-syscon
+ - starfive,jh7110-sys-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x10240000 0x1000>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 958b7ec118b4..fdad60cc9f2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19964,6 +19964,11 @@ S: Supported
F: Documentation/devicetree/bindings/rng/starfive*
F: drivers/char/hw_random/jh7110-trng.c
+STARFIVE JH7110 SYSCON
+M: William Qiu <[email protected]>
+S: Supported
+F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+
STATIC BRANCH/CALL
M: Peter Zijlstra <[email protected]>
M: Josh Poimboeuf <[email protected]>
--
2.34.1
On Wed, Mar 15, 2023 at 01:58:12PM +0800, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
>
> Signed-off-by: William Qiu <[email protected]>
I thought I'd already left an R-b tag against this, but w/e, here it is
again:
Reviewed-by: Conor Dooley <[email protected]>
I'll pick this one up once either Krzysztof or Rob have reviewed it.
Cheers,
Conor.
> ---
> .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
> MAINTAINERS | 5 +++
> 2 files changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..ae7f1d6916af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
> +
> +maintainers:
> + - William Qiu <[email protected]>
> +
> +description: |
> + The StarFive JH7110 SoC system controller provides register information such
> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - starfive,jh7110-aon-syscon
> + - starfive,jh7110-stg-syscon
> + - starfive,jh7110-sys-syscon
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + syscon@10240000 {
> + compatible = "starfive,jh7110-stg-syscon", "syscon";
> + reg = <0x10240000 0x1000>;
> + };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 958b7ec118b4..fdad60cc9f2e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19964,6 +19964,11 @@ S: Supported
> F: Documentation/devicetree/bindings/rng/starfive*
> F: drivers/char/hw_random/jh7110-trng.c
>
> +STARFIVE JH7110 SYSCON
> +M: William Qiu <[email protected]>
> +S: Supported
> +F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> +
> STATIC BRANCH/CALL
> M: Peter Zijlstra <[email protected]>
> M: Josh Poimboeuf <[email protected]>
> --
> 2.34.1
>
On 15/03/2023 06:58, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
>
> Signed-off-by: William Qiu <[email protected]>
> ---
> .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
> MAINTAINERS | 5 +++
> 2 files changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..ae7f1d6916af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
> +
> +maintainers:
> + - William Qiu <[email protected]>
> +
> +description: |
> + The StarFive JH7110 SoC system controller provides register information such
> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - starfive,jh7110-aon-syscon
> + - starfive,jh7110-stg-syscon
> + - starfive,jh7110-sys-syscon
> + - const: syscon
Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
... or your PLL clock controller was not tested.
Best regards,
Krzysztof
On 15/03/2023 06:58, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
>
> Signed-off-by: William Qiu <[email protected]>
> ---
> .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
> MAINTAINERS | 5 +++
> 2 files changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..ae7f1d6916af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
OK, I found the patch changing this. So basically you add knowingly
incomplete bindings and a second later you fix them.
Add complete bindings.
Best regards,
Krzysztof
On 2023/3/19 20:27, Krzysztof Kozlowski wrote:
> On 15/03/2023 06:58, William Qiu wrote:
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Signed-off-by: William Qiu <[email protected]>
>> ---
>> .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
>> MAINTAINERS | 5 +++
>> 2 files changed, 46 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> new file mode 100644
>> index 000000000000..ae7f1d6916af
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> @@ -0,0 +1,41 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SoC system controller
>> +
>> +maintainers:
>> + - William Qiu <[email protected]>
>> +
>> +description: |
>> + The StarFive JH7110 SoC system controller provides register information such
>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - starfive,jh7110-aon-syscon
>> + - starfive,jh7110-stg-syscon
>> + - starfive,jh7110-sys-syscon
>> + - const: syscon
>
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>
> ... or your PLL clock controller was not tested.
>
> Best regards,
> Krzysztof
>
Hi Krzysztof,
I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
was not tested which I didn't add in this patch series. And PLL clock controller belongs
to Xingyu Wu, I would tell him.
Best regards
William
On 2023/3/19 20:29, Krzysztof Kozlowski wrote:
> On 15/03/2023 06:58, William Qiu wrote:
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Signed-off-by: William Qiu <[email protected]>
>> ---
>> .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
>> MAINTAINERS | 5 +++
>> 2 files changed, 46 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> new file mode 100644
>> index 000000000000..ae7f1d6916af
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> @@ -0,0 +1,41 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SoC system controller
>
> OK, I found the patch changing this. So basically you add knowingly
> incomplete bindings and a second later you fix them.
>
> Add complete bindings.
>
> Best regards,
> Krzysztof
>
Originally, I only wanted to add a base module, and the binding of other modules
was added as incremental updates by other related colleagues. So now I need to
add the complete binding, right?
Best regards,
William
On 20/03/2023 06:54, William Qiu wrote:
>
>
> On 2023/3/19 20:27, Krzysztof Kozlowski wrote:
>> On 15/03/2023 06:58, William Qiu wrote:
>>> Add documentation to describe StarFive System Controller Registers.
>>>
>>> Signed-off-by: William Qiu <[email protected]>
>>> ---
>>> .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
>>> MAINTAINERS | 5 +++
>>> 2 files changed, 46 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> new file mode 100644
>>> index 000000000000..ae7f1d6916af
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> @@ -0,0 +1,41 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: StarFive JH7110 SoC system controller
>>> +
>>> +maintainers:
>>> + - William Qiu <[email protected]>
>>> +
>>> +description: |
>>> + The StarFive JH7110 SoC system controller provides register information such
>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - starfive,jh7110-aon-syscon
>>> + - starfive,jh7110-stg-syscon
>>> + - starfive,jh7110-sys-syscon
>>> + - const: syscon
>>
>> Does not look like you tested the bindings. Please run `make
>> dt_binding_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>
>> ... or your PLL clock controller was not tested.
>>
>> Best regards,
>> Krzysztof
>>
> Hi Krzysztof,
>
> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
> was not tested which I didn't add in this patch series. And PLL clock controller belongs
> to Xingyu Wu, I would tell him.
What's confusing you do not allow here clock controller.
Best regards,
Krzysztof
On 20/03/2023 07:00, William Qiu wrote:
>>
> Originally, I only wanted to add a base module, and the binding of other modules
> was added as incremental updates by other related colleagues. So now I need to
> add the complete binding, right?
Binding should be complete.
Best regards,
Krzysztof
On 2023/3/20 14:38, Krzysztof Kozlowski wrote:
> On 20/03/2023 07:00, William Qiu wrote:
>>>
>> Originally, I only wanted to add a base module, and the binding of other modules
>> was added as incremental updates by other related colleagues. So now I need to
>> add the complete binding, right?
>
> Binding should be complete.
>
> Best regards,
> Krzysztof
>
I'll add it then.
Best regards
William
On 2023/3/20 14:38, Krzysztof Kozlowski wrote:
> On 20/03/2023 06:54, William Qiu wrote:
>>
>>
>> On 2023/3/19 20:27, Krzysztof Kozlowski wrote:
>>> On 15/03/2023 06:58, William Qiu wrote:
>>>> Add documentation to describe StarFive System Controller Registers.
>>>>
>>>> Signed-off-by: William Qiu <[email protected]>
>>>> ---
>>>> .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
>>>> MAINTAINERS | 5 +++
>>>> 2 files changed, 46 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> new file mode 100644
>>>> index 000000000000..ae7f1d6916af
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> @@ -0,0 +1,41 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: StarFive JH7110 SoC system controller
>>>> +
>>>> +maintainers:
>>>> + - William Qiu <[email protected]>
>>>> +
>>>> +description: |
>>>> + The StarFive JH7110 SoC system controller provides register information such
>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + items:
>>>> + - enum:
>>>> + - starfive,jh7110-aon-syscon
>>>> + - starfive,jh7110-stg-syscon
>>>> + - starfive,jh7110-sys-syscon
>>>> + - const: syscon
>>>
>>> Does not look like you tested the bindings. Please run `make
>>> dt_binding_check` (see
>>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>>
>>> ... or your PLL clock controller was not tested.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>> Hi Krzysztof,
>>
>> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
>> was not tested which I didn't add in this patch series. And PLL clock controller belongs
>> to Xingyu Wu, I would tell him.
>
> What's confusing you do not allow here clock controller.
>
> Best regards,
> Krzysztof
>
I'll add it then.
Best regards
William
On Mon, Mar 20, 2023 at 03:32:14PM +0800, William Qiu wrote:
> >>> Does not look like you tested the bindings. Please run `make
> >>> dt_binding_check` (see
> >>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> >>>
> >>> ... or your PLL clock controller was not tested.
> >>>
> >>> Best regards,
> >>> Krzysztof
> >>>
> >> Hi Krzysztof,
> >>
> >> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
> >> was not tested which I didn't add in this patch series. And PLL clock controller belongs
> >> to Xingyu Wu, I would tell him.
> >
> > What's confusing you do not allow here clock controller.
> I'll add it then.
What's the plan here William?
Can you sort something out with Xingyu Wu so that the dt-binding is
added in a complete manner?
In the meantime, gonna drop this series as "Changes Requested" from
patchwork.
Cheers,
Conor.
On 2023/4/6 0:38, Conor Dooley wrote:
> On Mon, Mar 20, 2023 at 03:32:14PM +0800, William Qiu wrote:
>
>> >>> Does not look like you tested the bindings. Please run `make
>> >>> dt_binding_check` (see
>> >>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>> >>>
>> >>> ... or your PLL clock controller was not tested.
>> >>>
>> >>> Best regards,
>> >>> Krzysztof
>> >>>
>> >> Hi Krzysztof,
>> >>
>> >> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
>> >> was not tested which I didn't add in this patch series. And PLL clock controller belongs
>> >> to Xingyu Wu, I would tell him.
>> >
>> > What's confusing you do not allow here clock controller.
>
>> I'll add it then.
>
> What's the plan here William?
> Can you sort something out with Xingyu Wu so that the dt-binding is
> added in a complete manner?
> In the meantime, gonna drop this series as "Changes Requested" from
> patchwork.
>
> Cheers,
> Conor.
Hi Conor,
After discussing with Xingyu, I will sort all of it and send a complete
dt-binding today.
Best regards,
William