This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
The patch has been tested on the VisionFive 2 board.
This patchset should be applied after the patchset [1], [2] and[3]:
[1] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
[3] https://patchwork.kernel.org/project/linux-phy/cover/[email protected]/
This patchset is base on v6.3-rc4
patch 1 is usb phy dt-binding document.
patch 2 is Pcie PHY dt-binding document.
patch 3 is USB 2.0 PHY driver.
patch 4 is PCIe PHY driver.
patch 5 is usb dt-binding document.
patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
patch 7 is USB device tree configuration.
previous version
---
v1: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
v2: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
v3: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
changes
v4:
1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
3. (patch 3)
- split PCIe PHY driver to patch 4.
- replace dr_mode to phy mode in jh7110_usb2_phy.
4. (patch 4)
- Makefile and Kconfig sorted by alphabet sequence.
- Add PCIe PHY stg and syscon PHY connection configuration
for USB 3.0.
5. (patch 5)
- commit message changed.
- merge wrapper dts node and cdns3 node in example.
- Add interrupts, reg, phy and dr_mode in property.
- Add reset-name in property example.
6. (patch 6)
- For dts node is merged, Using platform_device_alloc and
platform_device_add to generate cadence sub device.
- IOMEM and IRQ resource are passed to Cadence sub device.
- Add PHY ops process for PHY dts setting can not be passed to
Cadence USB driver.
- remove the stg and sys USB 3.0 PHY configuration.
- Change the suspend clock reset and clock enable sequence.
- Get all reset and clock resources before enable them in
cdns_clk_rst_init.
- commit message changed.
7. (patch 7)
- merge wrapper dts node and cdns3 node in usb dts.
- move the stg and sys USB 3.0 PHY confiuration to
PCIe PHY dts node.
- commit message changed.
- Add reset-names dts.
v3:
1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
USB PHY codes are moved to patch 3 and patch 4.
2. (patch 5)
- USB wrapper module dts document is moved to usb directory.
- Remove the 'dr_mode' and 'starfive,usb2-only' setting.
- Some dts format changes. dts binding check pass.
3. (patch 6)
- Remove the PHY codes.
- Search 'dr_mode' and phy setting from Cadence subnode.
4. (patch 7)
- Add USB PHY dts configurion.
- 'dr_mode' is moved to Cadence controller submode.
v2:
1. (patch 5) dt-binding changes. The document example is the same as dts config.
2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
3. (patch 7) dts nodes sorted by the address after @
Minda Chen (7):
dt-bindings: phy: Add StarFive JH7110 USB document
dt-bindings: phy: Add StarFive JH7110 PCIe document
phy: starfive: add JH7110 USB 2.0 PHY driver.
phy: starfive: add JH7110 PCIE 2.0 PHY driver.
dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
usb: cdns3: add StarFive JH7110 USB driver.
riscv: dts: starfive: add USB dts configuration for JH7110
.../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
.../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
.../bindings/usb/starfive,jh7110-usb.yaml | 136 +++++++
MAINTAINERS | 16 +
.../jh7110-starfive-visionfive-2.dtsi | 7 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
drivers/phy/starfive/Kconfig | 22 +
drivers/phy/starfive/Makefile | 2 +
drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++
drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++
drivers/usb/cdns3/Kconfig | 11 +
drivers/usb/cdns3/Makefile | 1 +
drivers/usb/cdns3/cdns3-starfive.c | 378 ++++++++++++++++++
drivers/usb/cdns3/core.h | 3 +
14 files changed, 1086 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
prerequisite-patch-id: bb939c0c7c26b08addfccd890f9d3974b6eaec53
prerequisite-patch-id: 8a6f135bcabdad4a4bfb21f0c6a0ffd2bb57efe7
prerequisite-patch-id: c2366f993a9d85e28c06d8d09f064dd5e8b29a61
prerequisite-patch-id: 50d53a21f91f4087fc80b6f1f72864adfb0002b9
prerequisite-patch-id: 0df3703af91c30f1ca2c47f5609012f2d7200028
prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
prerequisite-patch-id: 551fae54377090044c3612fca9740a9b359abdd2
prerequisite-patch-id: c7fdf904f398d478f0ed6d57eb878982bc73329d
prerequisite-patch-id: 1b2d0982b18da060c82134f05bf3ce16425bac8d
prerequisite-patch-id: 090ba4b78d47bc19204916e76fdbc70021785388
prerequisite-patch-id: a5d9e0f7d4f8163f566678894cf693015119f2d9
prerequisite-patch-id: 4637a8fa2334a45fa6b64351f4e9e28d3e2d60d3
prerequisite-patch-id: 32647ec60a3b614e1c59ec8e54cb511ae832c22f
prerequisite-patch-id: aa06658ecf89c92d0dfdd6a4ba6d9e6e67532971
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: e7773c977a7b37692e9792b21cc4f17fa58f9215
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 9f911969d0a550648493952c99096d26e05d4d83
prerequisite-patch-id: 41eddeabff082d08a76d8da523f90da4b5218d28
prerequisite-patch-id: 2ddada18ab6ea5cd1da14212aaf59632f5203d40
prerequisite-patch-id: 398744c61913c76a35754de867c4f820ca7a8d99
prerequisite-patch-id: 1a2c49c1cf81607f062f35898457037d86598cf9
prerequisite-patch-id: f59269382164b5d642a5e10443ca447f5caa595c
prerequisite-patch-id: 1babe83d6bf999bad17584dc595480f9070a5369
prerequisite-patch-id: d95ea69f88a048ef702dceed0f2edee31e6fdfd2
prerequisite-patch-id: 77be3d122d66df813f13088141ce27b21107a341
prerequisite-patch-id: 9fbb7ad1dd258bb8ff5946c4a0e59de4bfd82a04
prerequisite-patch-id: a02411a8fe009acc0888e4a7d60233c9ee5a1e71
prerequisite-patch-id: 6f6984916dffd0cc66aa733c9b6bd3a55495a50c
prerequisite-patch-id: 584c256c9acb52ee2773d0c81c3f4977fc18155a
prerequisite-patch-id: b37ac15032973e1fcd918f157c82a0606775c9e9
prerequisite-patch-id: 999c243dca89d56d452aa52ea3e181358b5c1d80
prerequisite-patch-id: ca653566085079839fb3dc1e722effafbc8109a4
prerequisite-patch-id: 2fe72c216673efe690db54cbf500ba7f15e6247a
prerequisite-patch-id: 776afb78743657e4a6bfebd2cd8a44c5c9017ee2
prerequisite-patch-id: c9b92e6d1531d0a9fb122d9d038cc3d9df380e0f
--
2.17.1
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.
Signed-off-by: Minda Chen <[email protected]>
---
.../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
new file mode 100644
index 000000000000..80604dfe01f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive USB 2.0 PHY
+
+maintainers:
+ - Minda Chen <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh7110-usb-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: usb 125m clock
+ - description: app 125m clock
+
+ clock-names:
+ items:
+ - const: 125m
+ - const: app_125
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@10200000 {
+ compatible = "starfive,jh7110-usb-phy";
+ reg = <0x10200000 0x10000>;
+ clocks = <&syscrg 95>,
+ <&stgcrg 6>;
+ clock-names = "125m", "app_125";
+ #phy-cells = <0>;
+ };
--
2.17.1
Add Starfive JH7110 SoC USB 2.0 PHY driver support.
USB 2.0 PHY default connect to Cadence USB controller.
Signed-off-by: Minda Chen <[email protected]>
---
MAINTAINERS | 7 ++
drivers/phy/starfive/Kconfig | 11 ++
drivers/phy/starfive/Makefile | 1 +
drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++++++++++++++++++++
4 files changed, 180 insertions(+)
create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 1aef5ba46d71..9da352084403 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19968,6 +19968,13 @@ M: William Qiu <[email protected]>
S: Supported
F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+STARFIVE JH71X0 USB PHY DRIVER
+M: Emil Renner Berthing <[email protected]>
+M: Minda Chen <[email protected]>
+S: Supported
+F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
+F: drivers/phy/starfive/phy-jh7110-usb.c
+
STATIC BRANCH/CALL
M: Peter Zijlstra <[email protected]>
M: Josh Poimboeuf <[email protected]>
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index f989b8ff8bcb..2c013c390dee 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -11,3 +11,14 @@ config PHY_STARFIVE_DPHY_RX
Choose this option if you have a StarFive D-PHY in your
system. If M is selected, the module will be called
phy-starfive-dphy-rx.
+
+config PHY_STARFIVE_JH7110_USB
+ tristate "Starfive JH7110 USB 2.0 PHY support"
+ depends on USB_SUPPORT
+ select GENERIC_PHY
+ select USB_PHY
+ help
+ Enable this to support the StarFive USB 2.0 PHY,
+ used with the Cadence USB controller.
+ If M is selected, the module will be called
+ phy-jh7110-usb.ko.
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index 7ec576cb30ae..176443852f4d 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) += phy-starfive-dphy-rx.o
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c
new file mode 100644
index 000000000000..fe2cec39e5d3
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2023 Minda Chen <[email protected]>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/usb/of.h>
+
+#define USB_125M_CLK_RATE 125000000
+#define USB_LS_KEEPALIVE_OFF 0x4
+#define USB_LS_KEEPALIVE_ENABLE BIT(4)
+
+struct jh7110_usb2_phy {
+ struct phy *phy;
+ void __iomem *regs;
+ struct clk *usb_125m_clk;
+ struct clk *app_125;
+ enum phy_mode mode;
+};
+
+static void jh7110_usb2_mode_set(struct jh7110_usb2_phy *phy)
+{
+ unsigned int val;
+
+ if (phy->mode != PHY_MODE_USB_HOST) {
+ /* Enable the LS speed keep-alive signal */
+ val = readl(phy->regs + USB_LS_KEEPALIVE_OFF);
+ val |= USB_LS_KEEPALIVE_ENABLE;
+ writel(val, phy->regs + USB_LS_KEEPALIVE_OFF);
+ }
+}
+
+static int jh7110_usb2_phy_set_mode(struct phy *_phy,
+ enum phy_mode mode, int submode)
+{
+ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mode != phy->mode) {
+ dev_info(&_phy->dev, "Changing phy to %d\n", mode);
+ phy->mode = mode;
+ jh7110_usb2_mode_set(phy);
+ }
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *_phy)
+{
+ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
+ int ret;
+
+ ret = clk_set_rate(phy->usb_125m_clk, USB_125M_CLK_RATE);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(phy->app_125);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_exit(struct phy *_phy)
+{
+ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
+
+ clk_disable_unprepare(phy->app_125);
+
+ return 0;
+}
+
+static const struct phy_ops jh7110_usb2_phy_ops = {
+ .init = jh7110_usb2_phy_init,
+ .exit = jh7110_usb2_phy_exit,
+ .set_mode = jh7110_usb2_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static int jh7110_usb_phy_probe(struct platform_device *pdev)
+{
+ struct jh7110_usb2_phy *phy;
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ phy->usb_125m_clk = devm_clk_get(dev, "125m");
+ if (IS_ERR(phy->usb_125m_clk))
+ return dev_err_probe(dev, PTR_ERR(phy->usb_125m_clk),
+ "Failed to get 125m clock\n");
+
+ phy->app_125 = devm_clk_get(dev, "app_125");
+ if (IS_ERR(phy->app_125))
+ return dev_err_probe(dev, PTR_ERR(phy->app_125),
+ "Failed to get app 125m clock\n");
+
+ phy->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(phy->regs))
+ return dev_err_probe(dev, PTR_ERR(phy->regs),
+ "Failed to map phy base\n");
+
+ phy->phy = devm_phy_create(dev, NULL, &jh7110_usb2_phy_ops);
+ if (IS_ERR(phy->phy))
+ return dev_err_probe(dev, PTR_ERR(phy->phy),
+ "Failed to create phy\n");
+
+ platform_set_drvdata(pdev, phy);
+ phy_set_drvdata(phy->phy, phy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static int jh7110_usb_phy_remove(struct platform_device *pdev)
+{
+ struct jh7110_usb2_phy *phy = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(phy->app_125);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static const struct of_device_id jh7110_usb_phy_of_match[] = {
+ { .compatible = "starfive,jh7110-usb-phy" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jh7110_usb_phy_of_match);
+
+static struct platform_driver jh7110_usb_phy_driver = {
+ .probe = jh7110_usb_phy_probe,
+ .remove = jh7110_usb_phy_remove,
+ .driver = {
+ .of_match_table = jh7110_usb_phy_of_match,
+ .name = "jh7110-usb-phy",
+ }
+};
+module_platform_driver(jh7110_usb_phy_driver);
+
+MODULE_DESCRIPTION("StarFive JH7110 USB 2.0 PHY driver");
+MODULE_AUTHOR("Minda Chen <[email protected]>");
+MODULE_LICENSE("GPL");
--
2.17.1
Adds Specific Glue layer to support USB peripherals on
StarFive JH7110 SoC.
There is a Cadence USB3 core for JH7110 SoCs, the cdns
core is the child of this USB wrapper module device.
Signed-off-by: Minda Chen <[email protected]>
---
MAINTAINERS | 7 +
drivers/usb/cdns3/Kconfig | 11 +
drivers/usb/cdns3/Makefile | 1 +
drivers/usb/cdns3/cdns3-starfive.c | 378 +++++++++++++++++++++++++++++
drivers/usb/cdns3/core.h | 3 +
5 files changed, 400 insertions(+)
create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
diff --git a/MAINTAINERS b/MAINTAINERS
index d98b70d62fd4..0610bbf921bb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19977,6 +19977,13 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
F: drivers/phy/starfive/phy-jh7110-pcie.c
F: drivers/phy/starfive/phy-jh7110-usb.c
+STARFIVE JH71X0 USB DRIVERS
+M: Emil Renner Berthing <[email protected]>
+M: Minda Chen <[email protected]>
+S: Maintained
+F: Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
+F: drivers/usb/cdns3/cdns3-starfive.c
+
STATIC BRANCH/CALL
M: Peter Zijlstra <[email protected]>
M: Josh Poimboeuf <[email protected]>
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index b98ca0a1352a..0a514b591527 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -78,6 +78,17 @@ config USB_CDNS3_IMX
For example, imx8qm and imx8qxp.
+config USB_CDNS3_STARFIVE
+ tristate "Cadence USB3 support on StarFive SoC platforms"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ help
+ Say 'Y' or 'M' here if you are building for StarFive SoCs
+ platforms that contain Cadence USB3 controller core.
+
+ e.g. JH7110.
+
+ If you choose to build this driver as module it will
+ be dynamically linked and module will be called cdns3-starfive.ko
endif
if USB_CDNS_SUPPORT
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 61edb2f89276..48dfae75b5aa 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -24,6 +24,7 @@ endif
obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o
+obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
cdnsp-udc-pci-y := cdnsp-pci.o
diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 000000000000..925209a97bf9
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2022 Starfive, Inc.
+ * Author: Yanhong Wang <[email protected]>
+ * Author: Mason Huo <[email protected]>
+ * Author: Minda Chen <[email protected]>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/usb/otg.h>
+#include "core.h"
+
+#define USB_STRAP_HOST BIT(17)
+#define USB_STRAP_DEVICE BIT(18)
+#define USB_STRAP_MASK GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST BIT(19)
+#define USB_SUSPENDM_MASK BIT(19)
+#define CDNS_IRQ_WAKEUP_INDEX 3
+
+struct cdns_starfive {
+ struct device *dev;
+ struct phy *usb2_phy;
+ struct phy *usb3_phy;
+ struct regmap *stg_syscon;
+ struct reset_control *resets;
+ struct clk_bulk_data *clks;
+ int num_clks;
+ enum phy_mode phy_mode;
+ u32 stg_usb_mode;
+};
+
+static int set_phy_power_on(struct cdns_starfive *data)
+{
+ int ret;
+
+ ret = phy_power_on(data->usb2_phy);
+ if (ret)
+ return ret;
+
+ ret = phy_power_on(data->usb3_phy);
+ if (ret)
+ phy_power_off(data->usb2_phy);
+
+ return ret;
+}
+
+static void set_phy_power_off(struct cdns_starfive *data)
+{
+ phy_power_off(data->usb3_phy);
+ phy_power_off(data->usb2_phy);
+}
+
+static void cdns_mode_init(struct platform_device *pdev,
+ struct cdns_starfive *data)
+{
+ enum usb_dr_mode mode;
+
+ mode = usb_get_dr_mode(&pdev->dev);
+
+ switch (mode) {
+ case USB_DR_MODE_HOST:
+ regmap_update_bits(data->stg_syscon,
+ data->stg_usb_mode,
+ USB_STRAP_MASK,
+ USB_STRAP_HOST);
+ regmap_update_bits(data->stg_syscon,
+ data->stg_usb_mode,
+ USB_SUSPENDM_MASK,
+ USB_SUSPENDM_HOST);
+ data->phy_mode = PHY_MODE_USB_HOST;
+ break;
+
+ case USB_DR_MODE_PERIPHERAL:
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_STRAP_MASK, USB_STRAP_DEVICE);
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_SUSPENDM_MASK, 0);
+ data->phy_mode = PHY_MODE_USB_DEVICE;
+ break;
+
+ case USB_DR_MODE_OTG:
+ data->phy_mode = PHY_MODE_USB_OTG;
+ default:
+ break;
+ }
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+ int ret;
+
+ data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
+ if (data->num_clks < 0)
+ return dev_err_probe(data->dev, -ENODEV,
+ "Failed to get clocks\n");
+
+ data->resets = devm_reset_control_array_get_exclusive(data->dev);
+ if (IS_ERR(data->resets)) {
+ return dev_err_probe(data->dev, PTR_ERR(data->resets),
+ "Failed to get resets");
+ }
+
+ ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
+ if (ret)
+ return dev_err_probe(data->dev, ret,
+ "failed to enable clocks\n");
+
+ ret = reset_control_deassert(data->resets);
+ if (ret) {
+ ret = dev_err_probe(data->dev, ret,
+ "failed to reset clocks\n");
+ goto err_clk_init;
+ }
+
+ return ret;
+
+err_clk_init:
+ clk_bulk_disable_unprepare(data->num_clks, data->clks);
+ return ret;
+}
+
+static int cdns3_starfive_phy_init(struct device *dev, struct cdns_starfive *data)
+{
+ int ret;
+
+ ret = phy_init(data->usb2_phy);
+ if (ret)
+ return ret;
+
+ ret = phy_init(data->usb3_phy);
+ if (ret)
+ goto err_phy3_init;
+
+ ret = set_phy_power_on(data);
+ if (ret)
+ goto err_phy_power_on;
+
+ phy_set_mode(data->usb2_phy, data->phy_mode);
+ phy_set_mode(data->usb3_phy, data->phy_mode);
+
+ return 0;
+
+err_phy_power_on:
+ phy_exit(data->usb3_phy);
+err_phy3_init:
+ phy_exit(data->usb2_phy);
+ return ret;
+}
+
+static int cdns3_starfive_platform_device_add(struct platform_device *pdev,
+ struct cdns_starfive *data)
+{
+ struct platform_device *cdns3;
+ struct resource cdns_res[CDNS_RESOURCES_NUM], *res;
+ struct device *dev = &pdev->dev;
+ const char *reg_name[CDNS_IOMEM_RESOURCES_NUM] = {"otg", "xhci", "dev"};
+ const char *irq_name[CDNS_IRQ_RESOURCES_NUM] = {"host", "peripheral", "otg", "wakeup"};
+ int i, ret, res_idx = 0;
+
+ cdns3 = platform_device_alloc("cdns-usb3", PLATFORM_DEVID_AUTO);
+ if (!cdns3)
+ return dev_err_probe(dev, -ENOMEM,
+ "couldn't alloc cdns3 usb device\n");
+
+ cdns3->dev.parent = dev;
+ memset(cdns_res, 0, sizeof(cdns_res));
+
+ for (i = 0; i < CDNS_IOMEM_RESOURCES_NUM; i++) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[i]);
+ if (!res) {
+ ret = dev_err_probe(dev,
+ -ENXIO, "couldn't get %s reg resource\n", reg_name[i]);
+ goto free_memory;
+ }
+ cdns_res[res_idx] = *res;
+ res_idx++;
+ }
+
+ for (i = 0; i < CDNS_IRQ_RESOURCES_NUM; i++) {
+ if (i == CDNS_IRQ_WAKEUP_INDEX) {
+ ret = platform_get_irq_byname_optional(pdev, irq_name[i]);
+ if (ret < 0)
+ continue;
+ } else {
+ ret = platform_get_irq_byname(pdev, irq_name[i]);
+ if (ret < 0) {
+ dev_err(dev, "couldn't get %s irq\n", irq_name[i]);
+ goto free_memory;
+ }
+ }
+ cdns_res[res_idx].start = ret;
+ cdns_res[res_idx].end = ret;
+ cdns_res[res_idx].flags = IORESOURCE_IRQ;
+ cdns_res[res_idx].name = irq_name[i];
+ res_idx++;
+ }
+
+ ret = platform_device_add_resources(cdns3, cdns_res, res_idx);
+ if (ret) {
+ dev_err(dev, "couldn't add res to cdns3 device\n");
+ goto free_memory;
+ }
+
+ ret = platform_device_add(cdns3);
+ if (ret) {
+ dev_err(dev, "failed to register cdns3 device\n");
+ goto free_memory;
+ }
+
+ return ret;
+free_memory:
+ platform_device_put(cdns3);
+ return ret;
+}
+
+static int cdns_starfive_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct cdns_starfive *data;
+ unsigned int args;
+ int ret;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, data);
+
+ data->dev = dev;
+
+ data->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+ "starfive,stg-syscon", 1, &args);
+
+ if (IS_ERR(data->stg_syscon))
+ return dev_err_probe(dev, PTR_ERR(data->stg_syscon),
+ "Failed to parse starfive,stg-syscon\n");
+
+ data->stg_usb_mode = args;
+
+ cdns_mode_init(pdev, data);
+
+ ret = cdns_clk_rst_init(data);
+ if (ret)
+ return ret;
+
+ data->usb2_phy = devm_phy_optional_get(dev, "usb2-phy");
+ if (IS_ERR(data->usb2_phy))
+ return dev_err_probe(dev, PTR_ERR(data->usb2_phy),
+ "Failed to parse usb2 phy\n");
+
+ data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
+ if (IS_ERR(data->usb3_phy))
+ return dev_err_probe(dev, PTR_ERR(data->usb3_phy),
+ "Failed to parse usb3 phy\n");
+
+ cdns3_starfive_phy_init(dev, data);
+
+ ret = cdns3_starfive_platform_device_add(pdev, data);
+ if (ret) {
+ set_phy_power_off(data);
+ phy_exit(data->usb3_phy);
+ phy_exit(data->usb2_phy);
+ reset_control_assert(data->resets);
+ clk_bulk_disable_unprepare(data->num_clks, data->clks);
+ return dev_err_probe(dev, ret, "Failed to create children\n");
+ }
+
+ device_set_wakeup_capable(dev, true);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ dev_info(dev, "usb mode %d probe success\n", data->phy_mode);
+
+ return 0;
+}
+
+static int cdns_starfive_remove_core(struct device *dev, void *c)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+
+ platform_device_unregister(pdev);
+
+ return 0;
+}
+
+static int cdns_starfive_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct cdns_starfive *data = dev_get_drvdata(dev);
+
+ pm_runtime_get_sync(dev);
+ device_for_each_child(dev, NULL, cdns_starfive_remove_core);
+
+ set_phy_power_off(data);
+ phy_exit(data->usb2_phy);
+ phy_exit(data->usb3_phy);
+
+ reset_control_assert(data->resets);
+ clk_bulk_disable_unprepare(data->num_clks, data->clks);
+ pm_runtime_disable(dev);
+ pm_runtime_put_noidle(dev);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int cdns_starfive_resume(struct device *dev)
+{
+ struct cdns_starfive *data = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
+ if (ret)
+ return ret;
+
+ ret = reset_control_deassert(data->resets);
+ if (ret)
+ return ret;
+
+ ret = cdns3_starfive_phy_init(dev, data);
+
+ return ret;
+}
+
+static int cdns_starfive_suspend(struct device *dev)
+{
+ struct cdns_starfive *data = dev_get_drvdata(dev);
+
+ set_phy_power_off(data);
+ phy_exit(data->usb2_phy);
+ phy_exit(data->usb3_phy);
+ reset_control_assert(data->resets);
+ clk_bulk_disable_unprepare(data->num_clks, data->clks);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops cdns_starfive_pm_ops = {
+ SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume)
+};
+
+static const struct of_device_id cdns_starfive_of_match[] = {
+ { .compatible = "starfive,jh7110-usb", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, cdns_starfive_of_match);
+
+static struct platform_driver cdns_starfive_driver = {
+ .probe = cdns_starfive_probe,
+ .remove = cdns_starfive_remove,
+ .driver = {
+ .name = "cdns3-starfive",
+ .of_match_table = cdns_starfive_of_match,
+ .pm = &cdns_starfive_pm_ops,
+ },
+};
+module_platform_driver(cdns_starfive_driver);
+
+MODULE_ALIAS("platform:cdns3-starfive");
+MODULE_AUTHOR("YanHong Wang <[email protected]>");
+MODULE_AUTHOR("Mason Huo <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer");
diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h
index 2d332a788871..8d44ab504898 100644
--- a/drivers/usb/cdns3/core.h
+++ b/drivers/usb/cdns3/core.h
@@ -38,6 +38,9 @@ struct cdns_role_driver {
};
#define CDNS_XHCI_RESOURCES_NUM 2
+#define CDNS_IOMEM_RESOURCES_NUM 3
+#define CDNS_IRQ_RESOURCES_NUM 4
+#define CDNS_RESOURCES_NUM (CDNS_IOMEM_RESOURCES_NUM + CDNS_IRQ_RESOURCES_NUM)
struct cdns3_platform_data {
int (*platform_suspend)(struct device *dev,
--
2.17.1
Add USB wrapper layer and Cadence USB3 controller dts
configuration for StarFive JH7110 SoC and VisionFive2
Board.
USB controller connect to PHY, The PHY dts configuration
are also added.
Signed-off-by: Minda Chen <[email protected]>
---
.../jh7110-starfive-visionfive-2.dtsi | 7 +++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 +++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 1155b97b593d..cf0a66faf5d3 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -221,3 +221,10 @@
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&usb0 {
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ dr_mode = "peripheral";
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 29cd798b6732..2f67196ffac0 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -366,6 +366,50 @@
status = "disabled";
};
+ usb0: usb@10100000 {
+ compatible = "starfive,jh7110-usb";
+ reg = <0x0 0x10100000 0x0 0x10000>,
+ <0x0 0x10110000 0x0 0x10000>,
+ <0x0 0x10120000 0x0 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <100>, <108>, <110>;
+ interrupt-names = "host", "peripheral", "otg";
+ clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
+ <&stgcrg JH7110_STGCLK_USB0_STB>,
+ <&stgcrg JH7110_STGCLK_USB0_APB>,
+ <&stgcrg JH7110_STGCLK_USB0_AXI>,
+ <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
+ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+ resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
+ <&stgcrg JH7110_STGRST_USB0_APB>,
+ <&stgcrg JH7110_STGRST_USB0_AXI>,
+ <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
+ reset-names = "pwrup","apb","axi","utmi";
+ starfive,stg-syscon = <&stg_syscon 0x4>;
+ status = "disabled";
+ };
+
+ usbphy0: phy@10200000 {
+ compatible = "starfive,jh7110-usb-phy";
+ reg = <0x0 0x10200000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+ <&stgcrg JH7110_STGCLK_USB0_APP_125>;
+ clock-names = "125m", "app_125";
+ #phy-cells = <0>;
+ };
+
+ pciephy0: phy@10210000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10210000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
+ pciephy1: phy@10220000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10220000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
stgcrg: clock-controller@10230000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;
--
2.17.1
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
Signed-off-by: Minda Chen <[email protected]>
---
.../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
new file mode 100644
index 000000000000..1b868f75ddae
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive PCIe 2.0 PHY
+
+maintainers:
+ - Minda Chen <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh7110-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ starfive,sys-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to System Register Controller sys_syscon node.
+ - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
+ description:
+ The phandle to System Register Controller syscon node and the PHY connect offset
+ of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
+
+ starfive,stg-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to System Register Controller stg_syscon node.
+ - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
+ - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
+ description:
+ The phandle to System Register Controller syscon node and the offset
+ of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@10210000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x10210000 0x10000>;
+ #phy-cells = <0>;
+ starfive,sys-syscon = <&sys_syscon 0x18>;
+ starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
+ };
--
2.17.1
Add Starfive JH7110 SoC PCIe 2.0 driver support.
PCIe 2.0 PHY default connect to PCIe controller.
But pcie0 PHY can connect to USB 3.0 controlller.
Signed-off-by: Minda Chen <[email protected]>
---
MAINTAINERS | 4 +-
drivers/phy/starfive/Kconfig | 11 ++
drivers/phy/starfive/Makefile | 1 +
drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++++++++++++++++++
4 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 9da352084403..d98b70d62fd4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19968,11 +19968,13 @@ M: William Qiu <[email protected]>
S: Supported
F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
-STARFIVE JH71X0 USB PHY DRIVER
+STARFIVE JH71X0 PCIE AND USB PHY DRIVER
M: Emil Renner Berthing <[email protected]>
M: Minda Chen <[email protected]>
S: Supported
+F: Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
+F: drivers/phy/starfive/phy-jh7110-pcie.c
F: drivers/phy/starfive/phy-jh7110-usb.c
STATIC BRANCH/CALL
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index 2c013c390dee..c21c21d284a6 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -12,6 +12,17 @@ config PHY_STARFIVE_DPHY_RX
system. If M is selected, the module will be called
phy-starfive-dphy-rx.
+config PHY_STARFIVE_JH7110_PCIE
+ tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
+ depends on USB_SUPPORT
+ select GENERIC_PHY
+ select USB_PHY
+ help
+ Enable this to support the StarFive PCIe 2.0 PHY,
+ or used as USB 3.0 PHY.
+ If M is selected, the module will be called
+ phy-jh7110-pcie.ko.
+
config PHY_STARFIVE_JH7110_USB
tristate "Starfive JH7110 USB 2.0 PHY support"
depends on USB_SUPPORT
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index 176443852f4d..03a55aad53a2 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) += phy-starfive-dphy-rx.o
+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c
new file mode 100644
index 000000000000..725815aabe74
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 PCIe 2.0 PHY driver
+ *
+ * Copyright (C) 2023 Minda Chen <[email protected]>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define PCIE_KVCO_LEVEL_OFF (0x28)
+#define PCIE_USB3_PHY_PLL_CTL_OFF (0x7c)
+#define PCIE_KVCO_TUNE_SIGNAL_OFF (0x80)
+#define PCIE_USB3_PHY_ENABLE BIT(4)
+#define PHY_KVCO_FINE_TUNE_LEVEL 0x91
+#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc
+
+#define USB_PDRSTN_SPLIT BIT(17)
+
+#define PCIE_CKREF_SRC_MASK GENMASK(19, 18)
+#define PCIE_CLK_SEL_MASK GENMASK(21, 20)
+#define PCIE_PHY_MODE BIT(20)
+#define PCIE_PHY_MODE_MASK GENMASK(21, 20)
+#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2)
+#define PCIE_USB3_RATE_MASK GENMASK(6, 5)
+#define PCIE_USB3_RX_STANDBY_MASK BIT(7)
+#define PCIE_USB3_PHY_ENABLE BIT(4)
+
+struct jh7110_pcie_phy {
+ struct phy *phy;
+ struct regmap *stg_syscon;
+ struct regmap *sys_syscon;
+ void __iomem *regs;
+ u32 sys_phy_connect;
+ u32 stg_pcie_mode;
+ u32 stg_pcie_usb;
+ enum phy_mode mode;
+};
+
+static int jh7110_usb3_mode_set(struct jh7110_pcie_phy *data)
+{
+ if (!data->stg_syscon || !data->sys_syscon) {
+ dev_info(&data->phy->dev, "don't support usb3 mode\n");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
+ PCIE_PHY_MODE_MASK, PCIE_PHY_MODE);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_BUS_WIDTH_MASK, 0);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_RATE_MASK, 0);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_RX_STANDBY_MASK, 0);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE);
+
+ /* Connect usb 3.0 phy mode */
+ regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
+ USB_PDRSTN_SPLIT, 0);
+
+ /* Configuare spread-spectrum mode: down-spread-spectrum */
+ writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
+
+ return 0;
+}
+
+static void jh7110_pcie_mode_set(struct jh7110_pcie_phy *phy)
+{
+ /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
+ writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
+ writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
+}
+
+static int jh7110_pcie_phy_set_mode(struct phy *_phy,
+ enum phy_mode mode, int submode)
+{
+ struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy);
+ int ret;
+
+ if (mode != phy->mode) {
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ ret = jh7110_usb3_mode_set(phy);
+ if (ret)
+ return ret;
+ break;
+ case PHY_MODE_PCIE:
+ jh7110_pcie_mode_set(phy);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dev_info(&_phy->dev, "Changing phy mode to %d\n", mode);
+ phy->mode = mode;
+ }
+
+ return 0;
+}
+
+static int jh7110_pcie_phy_init(struct phy *_phy)
+{
+ return 0;
+}
+
+static int jh7110_pcie_phy_exit(struct phy *_phy)
+{
+ return 0;
+}
+
+static const struct phy_ops jh7110_pcie_phy_ops = {
+ .init = jh7110_pcie_phy_init,
+ .exit = jh7110_pcie_phy_exit,
+ .set_mode = jh7110_pcie_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static int jh7110_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct jh7110_pcie_phy *phy;
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+ u32 args[3];
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ phy->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(phy->regs))
+ return PTR_ERR(phy->regs);
+
+ phy->phy = devm_phy_create(dev, NULL, &jh7110_pcie_phy_ops);
+ if (IS_ERR(phy->phy))
+ return dev_err_probe(dev, PTR_ERR(phy->regs),
+ "Failed to map phy base\n");
+
+ phy->sys_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+ "starfive,sys-syscon", 1, args);
+
+ if (!IS_ERR_OR_NULL(phy->sys_syscon))
+ phy->sys_phy_connect = args[0];
+ else
+ phy->sys_syscon = NULL;
+
+ phy->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+ "starfive,stg-syscon", 2, args);
+
+ if (!IS_ERR_OR_NULL(phy->stg_syscon)) {
+ phy->stg_pcie_mode = args[0];
+ phy->stg_pcie_usb = args[1];
+ } else
+ phy->stg_syscon = NULL;
+
+ platform_set_drvdata(pdev, phy);
+ phy_set_drvdata(phy->phy, phy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static int jh7110_pcie_phy_remove(struct platform_device *pdev)
+{
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static const struct of_device_id jh7110_pcie_phy_of_match[] = {
+ { .compatible = "starfive,jh7110-pcie-phy" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jh7110_pcie_phy_of_match);
+
+static struct platform_driver jh7110_pcie_phy_driver = {
+ .probe = jh7110_pcie_phy_probe,
+ .remove = jh7110_pcie_phy_remove,
+ .driver = {
+ .of_match_table = jh7110_pcie_phy_of_match,
+ .name = "jh7110-pcie-phy",
+ }
+};
+module_platform_driver(jh7110_pcie_phy_driver);
+
+MODULE_DESCRIPTION("StarFive JH7110 PCIe 2.0 PHY driver");
+MODULE_AUTHOR("Minda Chen <[email protected]>");
+MODULE_LICENSE("GPL");
--
2.17.1
On 23-04-06 09:52:15, Minda Chen wrote:
> Adds Specific Glue layer to support USB peripherals on
> StarFive JH7110 SoC.
> There is a Cadence USB3 core for JH7110 SoCs, the cdns
> core is the child of this USB wrapper module device.
>
> Signed-off-by: Minda Chen <[email protected]>
> ---
> MAINTAINERS | 7 +
> drivers/usb/cdns3/Kconfig | 11 +
> drivers/usb/cdns3/Makefile | 1 +
> drivers/usb/cdns3/cdns3-starfive.c | 378 +++++++++++++++++++++++++++++
> drivers/usb/cdns3/core.h | 3 +
> 5 files changed, 400 insertions(+)
> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d98b70d62fd4..0610bbf921bb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19977,6 +19977,13 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> F: drivers/phy/starfive/phy-jh7110-pcie.c
> F: drivers/phy/starfive/phy-jh7110-usb.c
>
> +STARFIVE JH71X0 USB DRIVERS
> +M: Emil Renner Berthing <[email protected]>
> +M: Minda Chen <[email protected]>
> +S: Maintained
> +F: Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> +F: drivers/usb/cdns3/cdns3-starfive.c
> +
> STATIC BRANCH/CALL
> M: Peter Zijlstra <[email protected]>
> M: Josh Poimboeuf <[email protected]>
> diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
> index b98ca0a1352a..0a514b591527 100644
> --- a/drivers/usb/cdns3/Kconfig
> +++ b/drivers/usb/cdns3/Kconfig
> @@ -78,6 +78,17 @@ config USB_CDNS3_IMX
>
> For example, imx8qm and imx8qxp.
>
> +config USB_CDNS3_STARFIVE
> + tristate "Cadence USB3 support on StarFive SoC platforms"
> + depends on ARCH_STARFIVE || COMPILE_TEST
> + help
> + Say 'Y' or 'M' here if you are building for StarFive SoCs
> + platforms that contain Cadence USB3 controller core.
> +
> + e.g. JH7110.
> +
> + If you choose to build this driver as module it will
> + be dynamically linked and module will be called cdns3-starfive.ko
> endif
>
> if USB_CDNS_SUPPORT
> diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
> index 61edb2f89276..48dfae75b5aa 100644
> --- a/drivers/usb/cdns3/Makefile
> +++ b/drivers/usb/cdns3/Makefile
> @@ -24,6 +24,7 @@ endif
> obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
> obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
> obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o
> +obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
>
> cdnsp-udc-pci-y := cdnsp-pci.o
>
> diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
> new file mode 100644
> index 000000000000..925209a97bf9
> --- /dev/null
> +++ b/drivers/usb/cdns3/cdns3-starfive.c
> @@ -0,0 +1,378 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
> + *
> + * Copyright (C) 2022 Starfive, Inc.
> + * Author: Yanhong Wang <[email protected]>
> + * Author: Mason Huo <[email protected]>
> + * Author: Minda Chen <[email protected]>
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/kernel.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/of_platform.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/usb/otg.h>
> +#include "core.h"
> +
> +#define USB_STRAP_HOST BIT(17)
> +#define USB_STRAP_DEVICE BIT(18)
> +#define USB_STRAP_MASK GENMASK(18, 16)
> +
> +#define USB_SUSPENDM_HOST BIT(19)
> +#define USB_SUSPENDM_MASK BIT(19)
> +#define CDNS_IRQ_WAKEUP_INDEX 3
> +
> +struct cdns_starfive {
> + struct device *dev;
> + struct phy *usb2_phy;
> + struct phy *usb3_phy;
> + struct regmap *stg_syscon;
> + struct reset_control *resets;
> + struct clk_bulk_data *clks;
> + int num_clks;
> + enum phy_mode phy_mode;
> + u32 stg_usb_mode;
> +};
> +
> +static int set_phy_power_on(struct cdns_starfive *data)
> +{
> + int ret;
> +
> + ret = phy_power_on(data->usb2_phy);
> + if (ret)
> + return ret;
> +
> + ret = phy_power_on(data->usb3_phy);
> + if (ret)
> + phy_power_off(data->usb2_phy);
> +
> + return ret;
> +}
> +
> +static void set_phy_power_off(struct cdns_starfive *data)
> +{
> + phy_power_off(data->usb3_phy);
> + phy_power_off(data->usb2_phy);
> +}
> +
> +static void cdns_mode_init(struct platform_device *pdev,
> + struct cdns_starfive *data)
> +{
> + enum usb_dr_mode mode;
> +
> + mode = usb_get_dr_mode(&pdev->dev);
> +
> + switch (mode) {
> + case USB_DR_MODE_HOST:
> + regmap_update_bits(data->stg_syscon,
> + data->stg_usb_mode,
> + USB_STRAP_MASK,
> + USB_STRAP_HOST);
> + regmap_update_bits(data->stg_syscon,
> + data->stg_usb_mode,
> + USB_SUSPENDM_MASK,
> + USB_SUSPENDM_HOST);
> + data->phy_mode = PHY_MODE_USB_HOST;
> + break;
> +
> + case USB_DR_MODE_PERIPHERAL:
> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
> + USB_STRAP_MASK, USB_STRAP_DEVICE);
> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
> + USB_SUSPENDM_MASK, 0);
> + data->phy_mode = PHY_MODE_USB_DEVICE;
> + break;
> +
> + case USB_DR_MODE_OTG:
> + data->phy_mode = PHY_MODE_USB_OTG;
> + default:
> + break;
> + }
> +}
> +
> +static int cdns_clk_rst_init(struct cdns_starfive *data)
> +{
> + int ret;
> +
> + data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
> + if (data->num_clks < 0)
> + return dev_err_probe(data->dev, -ENODEV,
> + "Failed to get clocks\n");
> +
> + data->resets = devm_reset_control_array_get_exclusive(data->dev);
> + if (IS_ERR(data->resets)) {
> + return dev_err_probe(data->dev, PTR_ERR(data->resets),
> + "Failed to get resets");
> + }
> +
> + ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
> + if (ret)
> + return dev_err_probe(data->dev, ret,
> + "failed to enable clocks\n");
> +
> + ret = reset_control_deassert(data->resets);
> + if (ret) {
> + ret = dev_err_probe(data->dev, ret,
> + "failed to reset clocks\n");
> + goto err_clk_init;
> + }
> +
> + return ret;
> +
> +err_clk_init:
> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
> + return ret;
> +}
> +
> +static int cdns3_starfive_phy_init(struct device *dev, struct cdns_starfive *data)
> +{
> + int ret;
> +
> + ret = phy_init(data->usb2_phy);
> + if (ret)
> + return ret;
> +
> + ret = phy_init(data->usb3_phy);
> + if (ret)
> + goto err_phy3_init;
> +
> + ret = set_phy_power_on(data);
> + if (ret)
> + goto err_phy_power_on;
> +
> + phy_set_mode(data->usb2_phy, data->phy_mode);
> + phy_set_mode(data->usb3_phy, data->phy_mode);
> +
> + return 0;
> +
> +err_phy_power_on:
> + phy_exit(data->usb3_phy);
> +err_phy3_init:
> + phy_exit(data->usb2_phy);
> + return ret;
> +}
> +
> +static int cdns3_starfive_platform_device_add(struct platform_device *pdev,
> + struct cdns_starfive *data)
> +{
> + struct platform_device *cdns3;
> + struct resource cdns_res[CDNS_RESOURCES_NUM], *res;
> + struct device *dev = &pdev->dev;
> + const char *reg_name[CDNS_IOMEM_RESOURCES_NUM] = {"otg", "xhci", "dev"};
> + const char *irq_name[CDNS_IRQ_RESOURCES_NUM] = {"host", "peripheral", "otg", "wakeup"};
> + int i, ret, res_idx = 0;
> +
> + cdns3 = platform_device_alloc("cdns-usb3", PLATFORM_DEVID_AUTO);
> + if (!cdns3)
> + return dev_err_probe(dev, -ENOMEM,
> + "couldn't alloc cdns3 usb device\n");
> +
> + cdns3->dev.parent = dev;
> + memset(cdns_res, 0, sizeof(cdns_res));
> +
> + for (i = 0; i < CDNS_IOMEM_RESOURCES_NUM; i++) {
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[i]);
> + if (!res) {
> + ret = dev_err_probe(dev,
> + -ENXIO, "couldn't get %s reg resource\n", reg_name[i]);
> + goto free_memory;
> + }
> + cdns_res[res_idx] = *res;
> + res_idx++;
> + }
> +
> + for (i = 0; i < CDNS_IRQ_RESOURCES_NUM; i++) {
> + if (i == CDNS_IRQ_WAKEUP_INDEX) {
> + ret = platform_get_irq_byname_optional(pdev, irq_name[i]);
> + if (ret < 0)
> + continue;
> + } else {
> + ret = platform_get_irq_byname(pdev, irq_name[i]);
> + if (ret < 0) {
> + dev_err(dev, "couldn't get %s irq\n", irq_name[i]);
> + goto free_memory;
> + }
> + }
> + cdns_res[res_idx].start = ret;
> + cdns_res[res_idx].end = ret;
> + cdns_res[res_idx].flags = IORESOURCE_IRQ;
> + cdns_res[res_idx].name = irq_name[i];
> + res_idx++;
> + }
> +
> + ret = platform_device_add_resources(cdns3, cdns_res, res_idx);
> + if (ret) {
> + dev_err(dev, "couldn't add res to cdns3 device\n");
> + goto free_memory;
> + }
> +
> + ret = platform_device_add(cdns3);
> + if (ret) {
> + dev_err(dev, "failed to register cdns3 device\n");
> + goto free_memory;
> + }
> +
> + return ret;
> +free_memory:
> + platform_device_put(cdns3);
> + return ret;
> +}
> +
> +static int cdns_starfive_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct cdns_starfive *data;
> + unsigned int args;
> + int ret;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, data);
> +
> + data->dev = dev;
> +
> + data->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
> + "starfive,stg-syscon", 1, &args);
> +
> + if (IS_ERR(data->stg_syscon))
> + return dev_err_probe(dev, PTR_ERR(data->stg_syscon),
> + "Failed to parse starfive,stg-syscon\n");
> +
> + data->stg_usb_mode = args;
> +
> + cdns_mode_init(pdev, data);
> +
> + ret = cdns_clk_rst_init(data);
> + if (ret)
> + return ret;
> +
> + data->usb2_phy = devm_phy_optional_get(dev, "usb2-phy");
> + if (IS_ERR(data->usb2_phy))
> + return dev_err_probe(dev, PTR_ERR(data->usb2_phy),
> + "Failed to parse usb2 phy\n");
> +
> + data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
> + if (IS_ERR(data->usb3_phy))
> + return dev_err_probe(dev, PTR_ERR(data->usb3_phy),
> + "Failed to parse usb3 phy\n");
> +
You may not change the comment for if above functions are failed, there
is not opposite functions for clk and reset.
Others are okay for me.
Peter
> + cdns3_starfive_phy_init(dev, data);
> +
> + ret = cdns3_starfive_platform_device_add(pdev, data);
> + if (ret) {
> + set_phy_power_off(data);
> + phy_exit(data->usb3_phy);
> + phy_exit(data->usb2_phy);
> + reset_control_assert(data->resets);
> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
> + return dev_err_probe(dev, ret, "Failed to create children\n");
> + }
> +
> + device_set_wakeup_capable(dev, true);
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> +
> + dev_info(dev, "usb mode %d probe success\n", data->phy_mode);
> +
> + return 0;
> +}
> +
> +static int cdns_starfive_remove_core(struct device *dev, void *c)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> +
> + platform_device_unregister(pdev);
> +
> + return 0;
> +}
> +
> +static int cdns_starfive_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct cdns_starfive *data = dev_get_drvdata(dev);
> +
> + pm_runtime_get_sync(dev);
> + device_for_each_child(dev, NULL, cdns_starfive_remove_core);
> +
> + set_phy_power_off(data);
> + phy_exit(data->usb2_phy);
> + phy_exit(data->usb3_phy);
> +
> + reset_control_assert(data->resets);
> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
> + pm_runtime_disable(dev);
> + pm_runtime_put_noidle(dev);
> + platform_set_drvdata(pdev, NULL);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int cdns_starfive_resume(struct device *dev)
> +{
> + struct cdns_starfive *data = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
> + if (ret)
> + return ret;
> +
> + ret = reset_control_deassert(data->resets);
> + if (ret)
> + return ret;
> +
> + ret = cdns3_starfive_phy_init(dev, data);
> +
> + return ret;
> +}
> +
> +static int cdns_starfive_suspend(struct device *dev)
> +{
> + struct cdns_starfive *data = dev_get_drvdata(dev);
> +
> + set_phy_power_off(data);
> + phy_exit(data->usb2_phy);
> + phy_exit(data->usb3_phy);
> + reset_control_assert(data->resets);
> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
> +
> + return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops cdns_starfive_pm_ops = {
> + SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL)
> + SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume)
> +};
> +
> +static const struct of_device_id cdns_starfive_of_match[] = {
> + { .compatible = "starfive,jh7110-usb", },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, cdns_starfive_of_match);
> +
> +static struct platform_driver cdns_starfive_driver = {
> + .probe = cdns_starfive_probe,
> + .remove = cdns_starfive_remove,
> + .driver = {
> + .name = "cdns3-starfive",
> + .of_match_table = cdns_starfive_of_match,
> + .pm = &cdns_starfive_pm_ops,
> + },
> +};
> +module_platform_driver(cdns_starfive_driver);
> +
> +MODULE_ALIAS("platform:cdns3-starfive");
> +MODULE_AUTHOR("YanHong Wang <[email protected]>");
> +MODULE_AUTHOR("Mason Huo <[email protected]>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer");
> diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h
> index 2d332a788871..8d44ab504898 100644
> --- a/drivers/usb/cdns3/core.h
> +++ b/drivers/usb/cdns3/core.h
> @@ -38,6 +38,9 @@ struct cdns_role_driver {
> };
>
> #define CDNS_XHCI_RESOURCES_NUM 2
> +#define CDNS_IOMEM_RESOURCES_NUM 3
> +#define CDNS_IRQ_RESOURCES_NUM 4
> +#define CDNS_RESOURCES_NUM (CDNS_IOMEM_RESOURCES_NUM + CDNS_IRQ_RESOURCES_NUM)
>
> struct cdns3_platform_data {
> int (*platform_suspend)(struct device *dev,
> --
> 2.17.1
>
--
Thanks,
Peter Chen
On 2023/4/11 9:01, Peter Chen wrote:
> On 23-04-06 09:52:15, Minda Chen wrote:
>> Adds Specific Glue layer to support USB peripherals on
>> StarFive JH7110 SoC.
>> There is a Cadence USB3 core for JH7110 SoCs, the cdns
>> core is the child of this USB wrapper module device.
>>
>> Signed-off-by: Minda Chen <[email protected]>
>> ---
>> MAINTAINERS | 7 +
>> drivers/usb/cdns3/Kconfig | 11 +
>> drivers/usb/cdns3/Makefile | 1 +
>> drivers/usb/cdns3/cdns3-starfive.c | 378 +++++++++++++++++++++++++++++
>> drivers/usb/cdns3/core.h | 3 +
>> 5 files changed, 400 insertions(+)
>> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index d98b70d62fd4..0610bbf921bb 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -19977,6 +19977,13 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> F: drivers/phy/starfive/phy-jh7110-pcie.c
>> F: drivers/phy/starfive/phy-jh7110-usb.c
>>
>> +STARFIVE JH71X0 USB DRIVERS
>> +M: Emil Renner Berthing <[email protected]>
>> +M: Minda Chen <[email protected]>
>> +S: Maintained
>> +F: Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> +F: drivers/usb/cdns3/cdns3-starfive.c
>> +
>> STATIC BRANCH/CALL
>> M: Peter Zijlstra <[email protected]>
>> M: Josh Poimboeuf <[email protected]>
>> diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
>> index b98ca0a1352a..0a514b591527 100644
>> --- a/drivers/usb/cdns3/Kconfig
>> +++ b/drivers/usb/cdns3/Kconfig
>> @@ -78,6 +78,17 @@ config USB_CDNS3_IMX
>>
>> For example, imx8qm and imx8qxp.
>>
>> +config USB_CDNS3_STARFIVE
>> + tristate "Cadence USB3 support on StarFive SoC platforms"
>> + depends on ARCH_STARFIVE || COMPILE_TEST
>> + help
>> + Say 'Y' or 'M' here if you are building for StarFive SoCs
>> + platforms that contain Cadence USB3 controller core.
>> +
>> + e.g. JH7110.
>> +
>> + If you choose to build this driver as module it will
>> + be dynamically linked and module will be called cdns3-starfive.ko
>> endif
>>
>> if USB_CDNS_SUPPORT
>> diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
>> index 61edb2f89276..48dfae75b5aa 100644
>> --- a/drivers/usb/cdns3/Makefile
>> +++ b/drivers/usb/cdns3/Makefile
>> @@ -24,6 +24,7 @@ endif
>> obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
>> obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
>> obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o
>> +obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
>>
>> cdnsp-udc-pci-y := cdnsp-pci.o
>>
>> diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
>> new file mode 100644
>> index 000000000000..925209a97bf9
>> --- /dev/null
>> +++ b/drivers/usb/cdns3/cdns3-starfive.c
>> @@ -0,0 +1,378 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/**
>> + * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
>> + *
>> + * Copyright (C) 2022 Starfive, Inc.
>> + * Author: Yanhong Wang <[email protected]>
>> + * Author: Mason Huo <[email protected]>
>> + * Author: Minda Chen <[email protected]>
>> + */
>> +
>> +#include <linux/bits.h>
>> +#include <linux/clk.h>
>> +#include <linux/module.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/kernel.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/io.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/regmap.h>
>> +#include <linux/reset.h>
>> +#include <linux/usb/otg.h>
>> +#include "core.h"
>> +
>> +#define USB_STRAP_HOST BIT(17)
>> +#define USB_STRAP_DEVICE BIT(18)
>> +#define USB_STRAP_MASK GENMASK(18, 16)
>> +
>> +#define USB_SUSPENDM_HOST BIT(19)
>> +#define USB_SUSPENDM_MASK BIT(19)
>> +#define CDNS_IRQ_WAKEUP_INDEX 3
>> +
>> +struct cdns_starfive {
>> + struct device *dev;
>> + struct phy *usb2_phy;
>> + struct phy *usb3_phy;
>> + struct regmap *stg_syscon;
>> + struct reset_control *resets;
>> + struct clk_bulk_data *clks;
>> + int num_clks;
>> + enum phy_mode phy_mode;
>> + u32 stg_usb_mode;
>> +};
>> +
>> +static int set_phy_power_on(struct cdns_starfive *data)
>> +{
>> + int ret;
>> +
>> + ret = phy_power_on(data->usb2_phy);
>> + if (ret)
>> + return ret;
>> +
>> + ret = phy_power_on(data->usb3_phy);
>> + if (ret)
>> + phy_power_off(data->usb2_phy);
>> +
>> + return ret;
>> +}
>> +
>> +static void set_phy_power_off(struct cdns_starfive *data)
>> +{
>> + phy_power_off(data->usb3_phy);
>> + phy_power_off(data->usb2_phy);
>> +}
>> +
>> +static void cdns_mode_init(struct platform_device *pdev,
>> + struct cdns_starfive *data)
>> +{
>> + enum usb_dr_mode mode;
>> +
>> + mode = usb_get_dr_mode(&pdev->dev);
>> +
>> + switch (mode) {
>> + case USB_DR_MODE_HOST:
>> + regmap_update_bits(data->stg_syscon,
>> + data->stg_usb_mode,
>> + USB_STRAP_MASK,
>> + USB_STRAP_HOST);
>> + regmap_update_bits(data->stg_syscon,
>> + data->stg_usb_mode,
>> + USB_SUSPENDM_MASK,
>> + USB_SUSPENDM_HOST);
>> + data->phy_mode = PHY_MODE_USB_HOST;
>> + break;
>> +
>> + case USB_DR_MODE_PERIPHERAL:
>> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
>> + USB_STRAP_MASK, USB_STRAP_DEVICE);
>> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
>> + USB_SUSPENDM_MASK, 0);
>> + data->phy_mode = PHY_MODE_USB_DEVICE;
>> + break;
>> +
>> + case USB_DR_MODE_OTG:
>> + data->phy_mode = PHY_MODE_USB_OTG;
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +static int cdns_clk_rst_init(struct cdns_starfive *data)
>> +{
>> + int ret;
>> +
>> + data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
>> + if (data->num_clks < 0)
>> + return dev_err_probe(data->dev, -ENODEV,
>> + "Failed to get clocks\n");
>> +
>> + data->resets = devm_reset_control_array_get_exclusive(data->dev);
>> + if (IS_ERR(data->resets)) {
>> + return dev_err_probe(data->dev, PTR_ERR(data->resets),
>> + "Failed to get resets");
>> + }
>> +
>> + ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
>> + if (ret)
>> + return dev_err_probe(data->dev, ret,
>> + "failed to enable clocks\n");
>> +
>> + ret = reset_control_deassert(data->resets);
>> + if (ret) {
>> + ret = dev_err_probe(data->dev, ret,
>> + "failed to reset clocks\n");
>> + goto err_clk_init;
>> + }
>> +
>> + return ret;
>> +
>> +err_clk_init:
>> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
>> + return ret;
>> +}
>> +
>> +static int cdns3_starfive_phy_init(struct device *dev, struct cdns_starfive *data)
>> +{
>> + int ret;
>> +
>> + ret = phy_init(data->usb2_phy);
>> + if (ret)
>> + return ret;
>> +
>> + ret = phy_init(data->usb3_phy);
>> + if (ret)
>> + goto err_phy3_init;
>> +
>> + ret = set_phy_power_on(data);
>> + if (ret)
>> + goto err_phy_power_on;
>> +
>> + phy_set_mode(data->usb2_phy, data->phy_mode);
>> + phy_set_mode(data->usb3_phy, data->phy_mode);
>> +
>> + return 0;
>> +
>> +err_phy_power_on:
>> + phy_exit(data->usb3_phy);
>> +err_phy3_init:
>> + phy_exit(data->usb2_phy);
>> + return ret;
>> +}
>> +
>> +static int cdns3_starfive_platform_device_add(struct platform_device *pdev,
>> + struct cdns_starfive *data)
>> +{
>> + struct platform_device *cdns3;
>> + struct resource cdns_res[CDNS_RESOURCES_NUM], *res;
>> + struct device *dev = &pdev->dev;
>> + const char *reg_name[CDNS_IOMEM_RESOURCES_NUM] = {"otg", "xhci", "dev"};
>> + const char *irq_name[CDNS_IRQ_RESOURCES_NUM] = {"host", "peripheral", "otg", "wakeup"};
>> + int i, ret, res_idx = 0;
>> +
>> + cdns3 = platform_device_alloc("cdns-usb3", PLATFORM_DEVID_AUTO);
>> + if (!cdns3)
>> + return dev_err_probe(dev, -ENOMEM,
>> + "couldn't alloc cdns3 usb device\n");
>> +
>> + cdns3->dev.parent = dev;
>> + memset(cdns_res, 0, sizeof(cdns_res));
>> +
>> + for (i = 0; i < CDNS_IOMEM_RESOURCES_NUM; i++) {
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[i]);
>> + if (!res) {
>> + ret = dev_err_probe(dev,
>> + -ENXIO, "couldn't get %s reg resource\n", reg_name[i]);
>> + goto free_memory;
>> + }
>> + cdns_res[res_idx] = *res;
>> + res_idx++;
>> + }
>> +
>> + for (i = 0; i < CDNS_IRQ_RESOURCES_NUM; i++) {
>> + if (i == CDNS_IRQ_WAKEUP_INDEX) {
>> + ret = platform_get_irq_byname_optional(pdev, irq_name[i]);
>> + if (ret < 0)
>> + continue;
>> + } else {
>> + ret = platform_get_irq_byname(pdev, irq_name[i]);
>> + if (ret < 0) {
>> + dev_err(dev, "couldn't get %s irq\n", irq_name[i]);
>> + goto free_memory;
>> + }
>> + }
>> + cdns_res[res_idx].start = ret;
>> + cdns_res[res_idx].end = ret;
>> + cdns_res[res_idx].flags = IORESOURCE_IRQ;
>> + cdns_res[res_idx].name = irq_name[i];
>> + res_idx++;
>> + }
>> +
>> + ret = platform_device_add_resources(cdns3, cdns_res, res_idx);
>> + if (ret) {
>> + dev_err(dev, "couldn't add res to cdns3 device\n");
>> + goto free_memory;
>> + }
>> +
>> + ret = platform_device_add(cdns3);
>> + if (ret) {
>> + dev_err(dev, "failed to register cdns3 device\n");
>> + goto free_memory;
>> + }
>> +
>> + return ret;
>> +free_memory:
>> + platform_device_put(cdns3);
>> + return ret;
>> +}
>> +
>> +static int cdns_starfive_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct cdns_starfive *data;
>> + unsigned int args;
>> + int ret;
>> +
>> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + platform_set_drvdata(pdev, data);
>> +
>> + data->dev = dev;
>> +
>> + data->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
>> + "starfive,stg-syscon", 1, &args);
>> +
>> + if (IS_ERR(data->stg_syscon))
>> + return dev_err_probe(dev, PTR_ERR(data->stg_syscon),
>> + "Failed to parse starfive,stg-syscon\n");
>> +
>> + data->stg_usb_mode = args;
>> +
>> + cdns_mode_init(pdev, data);
>> +
>> + ret = cdns_clk_rst_init(data);
>> + if (ret)
>> + return ret;
>> +
>> + data->usb2_phy = devm_phy_optional_get(dev, "usb2-phy");
>> + if (IS_ERR(data->usb2_phy))
>> + return dev_err_probe(dev, PTR_ERR(data->usb2_phy),
>> + "Failed to parse usb2 phy\n");
>> +
>> + data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
>> + if (IS_ERR(data->usb3_phy))
>> + return dev_err_probe(dev, PTR_ERR(data->usb3_phy),
>> + "Failed to parse usb3 phy\n");
>> +
>
> You may not change the comment for if above functions are failed, there
> is not opposite functions for clk and reset.
>
> Others are okay for me.
>
> Peter
>
OK, I will change this. Thank you very much.
>> + cdns3_starfive_phy_init(dev, data);
>> +
>> + ret = cdns3_starfive_platform_device_add(pdev, data);
>> + if (ret) {
>> + set_phy_power_off(data);
>> + phy_exit(data->usb3_phy);
>> + phy_exit(data->usb2_phy);
>> + reset_control_assert(data->resets);
>> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
>> + return dev_err_probe(dev, ret, "Failed to create children\n");
>> + }
>> +
>> + device_set_wakeup_capable(dev, true);
>> + pm_runtime_set_active(dev);
>> + pm_runtime_enable(dev);
>> +
>> + dev_info(dev, "usb mode %d probe success\n", data->phy_mode);
>> +
>> + return 0;
>> +}
>> +
>> +static int cdns_starfive_remove_core(struct device *dev, void *c)
>> +{
>> + struct platform_device *pdev = to_platform_device(dev);
>> +
>> + platform_device_unregister(pdev);
>> +
>> + return 0;
>> +}
>> +
>> +static int cdns_starfive_remove(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct cdns_starfive *data = dev_get_drvdata(dev);
>> +
>> + pm_runtime_get_sync(dev);
>> + device_for_each_child(dev, NULL, cdns_starfive_remove_core);
>> +
>> + set_phy_power_off(data);
>> + phy_exit(data->usb2_phy);
>> + phy_exit(data->usb3_phy);
>> +
>> + reset_control_assert(data->resets);
>> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
>> + pm_runtime_disable(dev);
>> + pm_runtime_put_noidle(dev);
>> + platform_set_drvdata(pdev, NULL);
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM
>> +static int cdns_starfive_resume(struct device *dev)
>> +{
>> + struct cdns_starfive *data = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
>> + if (ret)
>> + return ret;
>> +
>> + ret = reset_control_deassert(data->resets);
>> + if (ret)
>> + return ret;
>> +
>> + ret = cdns3_starfive_phy_init(dev, data);
>> +
>> + return ret;
>> +}
>> +
>> +static int cdns_starfive_suspend(struct device *dev)
>> +{
>> + struct cdns_starfive *data = dev_get_drvdata(dev);
>> +
>> + set_phy_power_off(data);
>> + phy_exit(data->usb2_phy);
>> + phy_exit(data->usb3_phy);
>> + reset_control_assert(data->resets);
>> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static const struct dev_pm_ops cdns_starfive_pm_ops = {
>> + SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL)
>> + SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume)
>> +};
>> +
>> +static const struct of_device_id cdns_starfive_of_match[] = {
>> + { .compatible = "starfive,jh7110-usb", },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, cdns_starfive_of_match);
>> +
>> +static struct platform_driver cdns_starfive_driver = {
>> + .probe = cdns_starfive_probe,
>> + .remove = cdns_starfive_remove,
>> + .driver = {
>> + .name = "cdns3-starfive",
>> + .of_match_table = cdns_starfive_of_match,
>> + .pm = &cdns_starfive_pm_ops,
>> + },
>> +};
>> +module_platform_driver(cdns_starfive_driver);
>> +
>> +MODULE_ALIAS("platform:cdns3-starfive");
>> +MODULE_AUTHOR("YanHong Wang <[email protected]>");
>> +MODULE_AUTHOR("Mason Huo <[email protected]>");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer");
>> diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h
>> index 2d332a788871..8d44ab504898 100644
>> --- a/drivers/usb/cdns3/core.h
>> +++ b/drivers/usb/cdns3/core.h
>> @@ -38,6 +38,9 @@ struct cdns_role_driver {
>> };
>>
>> #define CDNS_XHCI_RESOURCES_NUM 2
>> +#define CDNS_IOMEM_RESOURCES_NUM 3
>> +#define CDNS_IRQ_RESOURCES_NUM 4
>> +#define CDNS_RESOURCES_NUM (CDNS_IOMEM_RESOURCES_NUM + CDNS_IRQ_RESOURCES_NUM)
>>
>> struct cdns3_platform_data {
>> int (*platform_suspend)(struct device *dev,
>> --
>> 2.17.1
>>
>
On 06/04/2023 03:52, Minda Chen wrote:
> Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.
Not much improvements in the subject. I asked to drop, not replace
document with document.
"Add StarFive JH7110 USB PHY"
>
> Signed-off-by: Minda Chen <[email protected]>
> ---
> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++
> 1 file changed, 50 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> new file mode 100644
> index 000000000000..80604dfe01f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive USB 2.0 PHY
Missing model name.
> +
> +maintainers:
> + - Minda Chen <[email protected]>
> +
Best regards,
Krzysztof
On 06/04/2023 03:52, Minda Chen wrote:
> Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
> PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
Subject: drop second/last, redundant "document". The "dt-bindings"
prefix is already stating that this is documentation.
>
> Signed-off-by: Minda Chen <[email protected]>
> ---
> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
> new file mode 100644
> index 000000000000..1b868f75ddae
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive PCIe 2.0 PHY
JH7110
Unless you plan to add here more compatibles, but then use enum for
compatible, not const.
> +
> +maintainers:
> + - Minda Chen <[email protected]>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-pcie-phy
> +
> + reg:
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 0
> +
> + starfive,sys-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle to System Register Controller sys_syscon node.
> + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
No improvements here.
> + description:
> + The phandle to System Register Controller syscon node and the PHY connect offset
> + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
> +
> + starfive,stg-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle to System Register Controller stg_syscon node.
> + - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
> + - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
No improvements.
Best regards,
Krzysztof
On 06/04/2023 03:52, Minda Chen wrote:
> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
> The patch has been tested on the VisionFive 2 board.
>
> This patchset should be applied after the patchset [1], [2] and[3]:
> [1] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
> [2] https://lore.kernel.org/all/[email protected]/
> [3] https://patchwork.kernel.org/project/linux-phy/cover/[email protected]/
>
> This patchset is base on v6.3-rc4
>
> patch 1 is usb phy dt-binding document.
> patch 2 is Pcie PHY dt-binding document.
> patch 3 is USB 2.0 PHY driver.
> patch 4 is PCIe PHY driver.
> patch 5 is usb dt-binding document.
> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
> patch 7 is USB device tree configuration.
>
> previous version
> ---
> v1: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
> v2: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
This is v2.
> v3: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>
> changes
> v4:
> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
> 3. (patch 3)
> - split PCIe PHY driver to patch 4.
> - replace dr_mode to phy mode in jh7110_usb2_phy.
> 4. (patch 4)
> - Makefile and Kconfig sorted by alphabet sequence.
> - Add PCIe PHY stg and syscon PHY connection configuration
> for USB 3.0.
> 5. (patch 5)
> - commit message changed.
> - merge wrapper dts node and cdns3 node in example.
> - Add interrupts, reg, phy and dr_mode in property.
> - Add reset-name in property example.
> 6. (patch 6)
> - For dts node is merged, Using platform_device_alloc and
> platform_device_add to generate cadence sub device.
> - IOMEM and IRQ resource are passed to Cadence sub device.
> - Add PHY ops process for PHY dts setting can not be passed to
> Cadence USB driver.
> - remove the stg and sys USB 3.0 PHY configuration.
> - Change the suspend clock reset and clock enable sequence.
> - Get all reset and clock resources before enable them in
> cdns_clk_rst_init.
> - commit message changed.
> 7. (patch 7)
> - merge wrapper dts node and cdns3 node in usb dts.
> - move the stg and sys USB 3.0 PHY confiuration to
> PCIe PHY dts node.
> - commit message changed.
> - Add reset-names dts.
>
> v3:
> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
> USB PHY codes are moved to patch 3 and patch 4.
> 2. (patch 5)
> - USB wrapper module dts document is moved to usb directory.
> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
> - Some dts format changes. dts binding check pass.
> 3. (patch 6)
> - Remove the PHY codes.
> - Search 'dr_mode' and phy setting from Cadence subnode.
> 4. (patch 7)
> - Add USB PHY dts configurion.
> - 'dr_mode' is moved to Cadence controller submode.
>
> v2:
> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
> 3. (patch 7) dts nodes sorted by the address after @
>
>
> Minda Chen (7):
> dt-bindings: phy: Add StarFive JH7110 USB document
> dt-bindings: phy: Add StarFive JH7110 PCIe document
> phy: starfive: add JH7110 USB 2.0 PHY driver.
> phy: starfive: add JH7110 PCIE 2.0 PHY driver.
> dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
> usb: cdns3: add StarFive JH7110 USB driver.
> riscv: dts: starfive: add USB dts configuration for JH7110
>
> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
> .../bindings/usb/starfive,jh7110-usb.yaml | 136 +++++++
> MAINTAINERS | 16 +
> .../jh7110-starfive-visionfive-2.dtsi | 7 +
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
> drivers/phy/starfive/Kconfig | 22 +
> drivers/phy/starfive/Makefile | 2 +
> drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++
> drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++
> drivers/usb/cdns3/Kconfig | 11 +
> drivers/usb/cdns3/Makefile | 1 +
> drivers/usb/cdns3/cdns3-starfive.c | 378 ++++++++++++++++++
> drivers/usb/cdns3/core.h | 3 +
> 14 files changed, 1086 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>
>
> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
What commits do you reference? How are they helpful?
Best regards,
Krzysztof
On 2023/4/12 16:26, Krzysztof Kozlowski wrote:
> On 06/04/2023 03:52, Minda Chen wrote:
>> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
>> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
>> The patch has been tested on the VisionFive 2 board.
>>
>> This patchset should be applied after the patchset [1], [2] and[3]:
>> [1] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
>> [2] https://lore.kernel.org/all/[email protected]/
>> [3] https://patchwork.kernel.org/project/linux-phy/cover/[email protected]/
>>
>> This patchset is base on v6.3-rc4
>>
>> patch 1 is usb phy dt-binding document.
>> patch 2 is Pcie PHY dt-binding document.
>> patch 3 is USB 2.0 PHY driver.
>> patch 4 is PCIe PHY driver.
>> patch 5 is usb dt-binding document.
>> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
>> patch 7 is USB device tree configuration.
>>
>> previous version
>> ---
>> v1: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>> v2: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>
> This is v2.
>
>> v3: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>>
>> changes
>> v4:
>> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
>> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
>> 3. (patch 3)
>> - split PCIe PHY driver to patch 4.
>> - replace dr_mode to phy mode in jh7110_usb2_phy.
>> 4. (patch 4)
>> - Makefile and Kconfig sorted by alphabet sequence.
>> - Add PCIe PHY stg and syscon PHY connection configuration
>> for USB 3.0.
>> 5. (patch 5)
>> - commit message changed.
>> - merge wrapper dts node and cdns3 node in example.
>> - Add interrupts, reg, phy and dr_mode in property.
>> - Add reset-name in property example.
>> 6. (patch 6)
>> - For dts node is merged, Using platform_device_alloc and
>> platform_device_add to generate cadence sub device.
>> - IOMEM and IRQ resource are passed to Cadence sub device.
>> - Add PHY ops process for PHY dts setting can not be passed to
>> Cadence USB driver.
>> - remove the stg and sys USB 3.0 PHY configuration.
>> - Change the suspend clock reset and clock enable sequence.
>> - Get all reset and clock resources before enable them in
>> cdns_clk_rst_init.
>> - commit message changed.
>> 7. (patch 7)
>> - merge wrapper dts node and cdns3 node in usb dts.
>> - move the stg and sys USB 3.0 PHY confiuration to
>> PCIe PHY dts node.
>> - commit message changed.
>> - Add reset-names dts.
>>
>> v3:
>> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
>> USB PHY codes are moved to patch 3 and patch 4.
>> 2. (patch 5)
>> - USB wrapper module dts document is moved to usb directory.
>> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
>> - Some dts format changes. dts binding check pass.
>> 3. (patch 6)
>> - Remove the PHY codes.
>> - Search 'dr_mode' and phy setting from Cadence subnode.
>> 4. (patch 7)
>> - Add USB PHY dts configurion.
>> - 'dr_mode' is moved to Cadence controller submode.
>>
>> v2:
>> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
>> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
>> 3. (patch 7) dts nodes sorted by the address after @
>>
>>
>> Minda Chen (7):
>> dt-bindings: phy: Add StarFive JH7110 USB document
>> dt-bindings: phy: Add StarFive JH7110 PCIe document
>> phy: starfive: add JH7110 USB 2.0 PHY driver.
>> phy: starfive: add JH7110 PCIE 2.0 PHY driver.
>> dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
>> usb: cdns3: add StarFive JH7110 USB driver.
>> riscv: dts: starfive: add USB dts configuration for JH7110
>>
>> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
>> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
>> .../bindings/usb/starfive,jh7110-usb.yaml | 136 +++++++
>> MAINTAINERS | 16 +
>> .../jh7110-starfive-visionfive-2.dtsi | 7 +
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
>> drivers/phy/starfive/Kconfig | 22 +
>> drivers/phy/starfive/Makefile | 2 +
>> drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++
>> drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++
>> drivers/usb/cdns3/Kconfig | 11 +
>> drivers/usb/cdns3/Makefile | 1 +
>> drivers/usb/cdns3/cdns3-starfive.c | 378 ++++++++++++++++++
>> drivers/usb/cdns3/core.h | 3 +
>> 14 files changed, 1086 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
>> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
>> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>>
>>
>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>
> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>
> What commits do you reference? How are they helpful?
>
I use "git format-patch --base=(commit) to generate patchset.
Maybe I set the wrong base commit.
>
> Best regards,
> Krzysztof
>
On 13/04/2023 12:44, Minda Chen wrote:
>
>
> On 2023/4/12 16:26, Krzysztof Kozlowski wrote:
>> On 06/04/2023 03:52, Minda Chen wrote:
>>> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
>>> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
>>> The patch has been tested on the VisionFive 2 board.
>>>
>>> This patchset should be applied after the patchset [1], [2] and[3]:
>>> [1] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
>>> [2] https://lore.kernel.org/all/[email protected]/
>>> [3] https://patchwork.kernel.org/project/linux-phy/cover/[email protected]/
>>>
>>> This patchset is base on v6.3-rc4
>>>
>>> patch 1 is usb phy dt-binding document.
>>> patch 2 is Pcie PHY dt-binding document.
>>> patch 3 is USB 2.0 PHY driver.
>>> patch 4 is PCIe PHY driver.
>>> patch 5 is usb dt-binding document.
>>> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
>>> patch 7 is USB device tree configuration.
>>>
>>> previous version
>>> ---
>>> v1: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>>> v2: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>>
>> This is v2.
>>
>>> v3: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>>>
>>> changes
>>> v4:
>>> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
>>> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
>>> 3. (patch 3)
>>> - split PCIe PHY driver to patch 4.
>>> - replace dr_mode to phy mode in jh7110_usb2_phy.
>>> 4. (patch 4)
>>> - Makefile and Kconfig sorted by alphabet sequence.
>>> - Add PCIe PHY stg and syscon PHY connection configuration
>>> for USB 3.0.
>>> 5. (patch 5)
>>> - commit message changed.
>>> - merge wrapper dts node and cdns3 node in example.
>>> - Add interrupts, reg, phy and dr_mode in property.
>>> - Add reset-name in property example.
>>> 6. (patch 6)
>>> - For dts node is merged, Using platform_device_alloc and
>>> platform_device_add to generate cadence sub device.
>>> - IOMEM and IRQ resource are passed to Cadence sub device.
>>> - Add PHY ops process for PHY dts setting can not be passed to
>>> Cadence USB driver.
>>> - remove the stg and sys USB 3.0 PHY configuration.
>>> - Change the suspend clock reset and clock enable sequence.
>>> - Get all reset and clock resources before enable them in
>>> cdns_clk_rst_init.
>>> - commit message changed.
>>> 7. (patch 7)
>>> - merge wrapper dts node and cdns3 node in usb dts.
>>> - move the stg and sys USB 3.0 PHY confiuration to
>>> PCIe PHY dts node.
>>> - commit message changed.
>>> - Add reset-names dts.
>>>
>>> v3:
>>> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
>>> USB PHY codes are moved to patch 3 and patch 4.
>>> 2. (patch 5)
>>> - USB wrapper module dts document is moved to usb directory.
>>> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
>>> - Some dts format changes. dts binding check pass.
>>> 3. (patch 6)
>>> - Remove the PHY codes.
>>> - Search 'dr_mode' and phy setting from Cadence subnode.
>>> 4. (patch 7)
>>> - Add USB PHY dts configurion.
>>> - 'dr_mode' is moved to Cadence controller submode.
>>>
>>> v2:
>>> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
>>> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
>>> 3. (patch 7) dts nodes sorted by the address after @
>>>
>>>
>>> Minda Chen (7):
>>> dt-bindings: phy: Add StarFive JH7110 USB document
>>> dt-bindings: phy: Add StarFive JH7110 PCIe document
>>> phy: starfive: add JH7110 USB 2.0 PHY driver.
>>> phy: starfive: add JH7110 PCIE 2.0 PHY driver.
>>> dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
>>> usb: cdns3: add StarFive JH7110 USB driver.
>>> riscv: dts: starfive: add USB dts configuration for JH7110
>>>
>>> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
>>> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
>>> .../bindings/usb/starfive,jh7110-usb.yaml | 136 +++++++
>>> MAINTAINERS | 16 +
>>> .../jh7110-starfive-visionfive-2.dtsi | 7 +
>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
>>> drivers/phy/starfive/Kconfig | 22 +
>>> drivers/phy/starfive/Makefile | 2 +
>>> drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++
>>> drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++
>>> drivers/usb/cdns3/Kconfig | 11 +
>>> drivers/usb/cdns3/Makefile | 1 +
>>> drivers/usb/cdns3/cdns3-starfive.c | 378 ++++++++++++++++++
>>> drivers/usb/cdns3/core.h | 3 +
>>> 14 files changed, 1086 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>>> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>>> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
>>> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
>>> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>>>
>>>
>>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>>
>> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>>
>> What commits do you reference? How are they helpful?
>>
> I use "git format-patch --base=(commit) to generate patchset.
> Maybe I set the wrong base commit.
How are they helpful if these are private commits?
Best regards,
Krzysztof
On 2023/4/13 22:13, Krzysztof Kozlowski wrote:
> On 13/04/2023 12:44, Minda Chen wrote:
>>
>>
>> On 2023/4/12 16:26, Krzysztof Kozlowski wrote:
>>> On 06/04/2023 03:52, Minda Chen wrote:
>>>> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
>>>> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
>>>> The patch has been tested on the VisionFive 2 board.
>>>>
>>>> This patchset should be applied after the patchset [1], [2] and[3]:
>>>> [1] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
>>>> [2] https://lore.kernel.org/all/[email protected]/
>>>> [3] https://patchwork.kernel.org/project/linux-phy/cover/[email protected]/
>>>>
>>>> This patchset is base on v6.3-rc4
>>>>
>>>> patch 1 is usb phy dt-binding document.
>>>> patch 2 is Pcie PHY dt-binding document.
>>>> patch 3 is USB 2.0 PHY driver.
>>>> patch 4 is PCIe PHY driver.
>>>> patch 5 is usb dt-binding document.
>>>> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
>>>> patch 7 is USB device tree configuration.
>>>>
>>>> previous version
>>>> ---
>>>> v1: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>>>> v2: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>>>
>>> This is v2.
>>>
>>>> v3: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>>>>
>>>> changes
>>>> v4:
>>>> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
>>>> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
>>>> 3. (patch 3)
>>>> - split PCIe PHY driver to patch 4.
>>>> - replace dr_mode to phy mode in jh7110_usb2_phy.
>>>> 4. (patch 4)
>>>> - Makefile and Kconfig sorted by alphabet sequence.
>>>> - Add PCIe PHY stg and syscon PHY connection configuration
>>>> for USB 3.0.
>>>> 5. (patch 5)
>>>> - commit message changed.
>>>> - merge wrapper dts node and cdns3 node in example.
>>>> - Add interrupts, reg, phy and dr_mode in property.
>>>> - Add reset-name in property example.
>>>> 6. (patch 6)
>>>> - For dts node is merged, Using platform_device_alloc and
>>>> platform_device_add to generate cadence sub device.
>>>> - IOMEM and IRQ resource are passed to Cadence sub device.
>>>> - Add PHY ops process for PHY dts setting can not be passed to
>>>> Cadence USB driver.
>>>> - remove the stg and sys USB 3.0 PHY configuration.
>>>> - Change the suspend clock reset and clock enable sequence.
>>>> - Get all reset and clock resources before enable them in
>>>> cdns_clk_rst_init.
>>>> - commit message changed.
>>>> 7. (patch 7)
>>>> - merge wrapper dts node and cdns3 node in usb dts.
>>>> - move the stg and sys USB 3.0 PHY confiuration to
>>>> PCIe PHY dts node.
>>>> - commit message changed.
>>>> - Add reset-names dts.
>>>>
>>>> v3:
>>>> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
>>>> USB PHY codes are moved to patch 3 and patch 4.
>>>> 2. (patch 5)
>>>> - USB wrapper module dts document is moved to usb directory.
>>>> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
>>>> - Some dts format changes. dts binding check pass.
>>>> 3. (patch 6)
>>>> - Remove the PHY codes.
>>>> - Search 'dr_mode' and phy setting from Cadence subnode.
>>>> 4. (patch 7)
>>>> - Add USB PHY dts configurion.
>>>> - 'dr_mode' is moved to Cadence controller submode.
>>>>
>>>> v2:
>>>> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
>>>> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
>>>> 3. (patch 7) dts nodes sorted by the address after @
>>>>
>>>>
>>>> Minda Chen (7):
>>>> dt-bindings: phy: Add StarFive JH7110 USB document
>>>> dt-bindings: phy: Add StarFive JH7110 PCIe document
>>>> phy: starfive: add JH7110 USB 2.0 PHY driver.
>>>> phy: starfive: add JH7110 PCIE 2.0 PHY driver.
>>>> dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
>>>> usb: cdns3: add StarFive JH7110 USB driver.
>>>> riscv: dts: starfive: add USB dts configuration for JH7110
>>>>
>>>> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
>>>> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
>>>> .../bindings/usb/starfive,jh7110-usb.yaml | 136 +++++++
>>>> MAINTAINERS | 16 +
>>>> .../jh7110-starfive-visionfive-2.dtsi | 7 +
>>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
>>>> drivers/phy/starfive/Kconfig | 22 +
>>>> drivers/phy/starfive/Makefile | 2 +
>>>> drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++
>>>> drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++
>>>> drivers/usb/cdns3/Kconfig | 11 +
>>>> drivers/usb/cdns3/Makefile | 1 +
>>>> drivers/usb/cdns3/cdns3-starfive.c | 378 ++++++++++++++++++
>>>> drivers/usb/cdns3/core.h | 3 +
>>>> 14 files changed, 1086 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>>>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>>>> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>>>> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
>>>> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
>>>> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>>>>
>>>>
>>>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>>>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>>>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>
>>> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>
>>> What commits do you reference? How are they helpful?
>>>
>> I use "git format-patch --base=(commit) to generate patchset.
>> Maybe I set the wrong base commit.
>
> How are they helpful if these are private commits?
>> Best regards,
> Krzysztof
>
base-commit is not private commits.
I should set base commit 197b6b60ae7bc51dd0814953c562833143b292aa. This is 6.3-rc4 commit.
But I set 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35. This is 6.3-rc4's previous commit.
On 18/04/2023 13:12, Minda Chen wrote:
>>>>>
>>>>>
>>>>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>>>>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>>>>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>>
>>>> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>>
>>>> What commits do you reference? How are they helpful?
>>>>
>>> I use "git format-patch --base=(commit) to generate patchset.
>>> Maybe I set the wrong base commit.
>>
>> How are they helpful if these are private commits?
>>> Best regards,
>> Krzysztof
>>
> base-commit is not private commits.
> I should set base commit 197b6b60ae7bc51dd0814953c562833143b292aa. This is 6.3-rc4 commit.
> But I set 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35. This is 6.3-rc4's previous commit.
You missed the point. I am not talking about base commit. I am talking
about your prerequisites, which are useless. What can we do with such SHA?
Best regards,
Krzysztof
On 2023/4/18 20:22, Krzysztof Kozlowski wrote:
> On 18/04/2023 13:12, Minda Chen wrote:
>>>>>>
>>>>>>
>>>>>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>>>>>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>>>>>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>>>
>>>>> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>>>
>>>>> What commits do you reference? How are they helpful?
>>>>>
>>>> I use "git format-patch --base=(commit) to generate patchset.
>>>> Maybe I set the wrong base commit.
>>>
>>> How are they helpful if these are private commits?
>>>> Best regards,
>>> Krzysztof
>>>
>> base-commit is not private commits.
>> I should set base commit 197b6b60ae7bc51dd0814953c562833143b292aa. This is 6.3-rc4 commit.
>> But I set 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35. This is 6.3-rc4's previous commit.
>
> You missed the point. I am not talking about base commit. I am talking
> about your prerequisites, which are useless. What can we do with such SHA?
>
> Best regards,
> Krzysztof
>
OK， I will delete them