Add missing ESM and watchdog nodes for the sake of devicetree completion
of hardware description w.r.t Linux and ESM and WDT enablement on
U-Boot. This patch series adds the missing nodes for J721E and J7200.
Boot logs:
https://gist.github.com/nehamalcom/5dc94ab60f57df5d515d0a6d0da6e0d1
Neha Malcom Francis (4):
arm64: dts: ti: k3-j721e-mcu: Add the WKUP ESM instance
arm64: dts: ti: k3-j721e-mcu: Add the MCU domain watchdog instances
arm64: dts: ti: k3-j721e-main: Add the MAIN domain watchdog instances
arm64: dts: ti: k3-j7200-main: Add the MAIN domain watchdog instances
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 27 ++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 93 +++++++++++++++++++
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 31 +++++++
3 files changed, 151 insertions(+)
--
2.34.1
Add the WKUP ESM instance for J721E. It has three instances in total,
one in the MAIN domain (main_esm) and two in the MCU-WKUP domain
(mcu_esm and wkup_esm).
Signed-off-by: Neha Malcom Francis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 4618b697fbc4..b0f41e9829cc 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -689,4 +689,9 @@ mcu_esm: esm@40800000 {
ti,esm-pins = <95>;
bootph-pre-ram;
};
+
+ wkup_esm: esm@42080000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x42080000 0x00 0x1000>;
+ };
};
--
2.34.1
There are 4 watchdog instances in the MAIN domain:
* one each for the 2 A72 cores
* one each for the 2 R5F cores
Currently, the devicetree only describes watchdog instances for the A72
cores and enables them. Describe the remaining but reserve them as they
will be used by their respective firmware.
Signed-off-by: Neha Malcom Francis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 27 +++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 657f9cc9f4ea..c448c2218e23 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -1254,6 +1254,33 @@ watchdog1: watchdog@2210000 {
assigned-clock-parents = <&k3_clks 253 5>;
};
+ /*
+ * The following RTI instances are coupled with MCU R5Fs so
+ * keeping them reserved as these will be used by their respective
+ * firmware
+ */
+ watchdog2: watchdog@23c0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23c0000 0x00 0x100>;
+ clocks = <&k3_clks 258 1>;
+ power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 258 1>;
+ assigned-clock-parents = <&k3_clks 258 5>;
+ /* reserved for MAIN_R5F0_0 */
+ status = "reserved";
+ };
+
+ watchdog3: watchdog@23d0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23d0000 0x00 0x100>;
+ clocks = <&k3_clks 259 1>;
+ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 259 1>;
+ assigned-clock-parents = <&k3_clks 259 5>;
+ /* reserved for MAIN_R5F0_1 */
+ status = "reserved";
+ };
+
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
--
2.34.1
There are 2 watchdog instances in the MCU domain. These instances are
coupled with the MCU domain R55 instances. Reserve them as they are not
used by A72.
Signed-off-by: Neha Malcom Francis <[email protected]>
---
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index b0f41e9829cc..867f307909be 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -694,4 +694,30 @@ wkup_esm: esm@42080000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x42080000 0x00 0x1000>;
};
+
+ /*
+ * The 2 RTI instances are couple with MCU R5Fs so keeping them
+ * reserved as these will be used by their respective firmware
+ */
+ mcu_watchdog0: watchdog@40600000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40600000 0x00 0x100>;
+ clocks = <&k3_clks 262 1>;
+ power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 262 1>;
+ assigned-clock-parents = <&k3_clks 262 5>;
+ /* reserved for MCU_R5F0_0 */
+ status = "reserved";
+ };
+
+ mcu_watchdog1: watchdog@40610000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40610000 0x00 0x100>;
+ clocks = <&k3_clks 263 1>;
+ power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 263 1>;
+ assigned-clock-parents = <&k3_clks 263 5>;
+ /* reserved for MCU_R5F0_1 */
+ status = "reserved";
+ };
};
--
2.34.1
There are 10 watchdog instances in the MAIN domain:
* one each for the 2 A72 cores
* one for the GPU core
* one for the C7x core
* one each for the 2 C66x cores
* one each for the 4 R5F cores
Currently, the devicetree only describes watchdog instances for the A72
cores and enables them. Describe the remaining but reserve them as they
will be used by their respective firmware.
Signed-off-by: Neha Malcom Francis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 93 +++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index c7eafbc862f9..d8930b8ea8ec 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -2157,6 +2157,99 @@ watchdog1: watchdog@2210000 {
assigned-clock-parents = <&k3_clks 253 5>;
};
+ /*
+ * The following RTI instances are coupled with MCU R5Fs, c7x and
+ * GPU so keeping them reserved as these will be used by their
+ * respective firmware
+ */
+ watchdog2: watchdog@22f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x22f0000 0x00 0x100>;
+ clocks = <&k3_clks 257 1>;
+ power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 257 1>;
+ assigned-clock-parents = <&k3_clks 257 5>;
+ /* reserved for GPU */
+ status = "reserved";
+ };
+
+ watchdog3: watchdog@2300000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2300000 0x00 0x100>;
+ clocks = <&k3_clks 256 1>;
+ power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 256 1>;
+ assigned-clock-parents = <&k3_clks 256 5>;
+ /* reserved for C7X */
+ status = "reserved";
+ };
+
+ watchdog4: watchdog@2380000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2380000 0x00 0x100>;
+ clocks = <&k3_clks 254 1>;
+ power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 254 1>;
+ assigned-clock-parents = <&k3_clks 254 5>;
+ /* reserved for C66X_0 */
+ status = "reserved";
+ };
+
+ watchdog5: watchdog@2390000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2390000 0x00 0x100>;
+ clocks = <&k3_clks 255 1>;
+ power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 255 1>;
+ assigned-clock-parents = <&k3_clks 255 5>;
+ /* reserved for C66X_1 */
+ status = "reserved";
+ };
+
+ watchdog6: watchdog@23c0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23c0000 0x00 0x100>;
+ clocks = <&k3_clks 258 1>;
+ power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 258 1>;
+ assigned-clock-parents = <&k3_clks 258 5>;
+ /* reserved for MAIN_R5F0_0 */
+ status = "reserved";
+ };
+
+ watchdog7: watchdog@23d0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23d0000 0x00 0x100>;
+ clocks = <&k3_clks 259 1>;
+ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 259 1>;
+ assigned-clock-parents = <&k3_clks 259 5>;
+ /* reserved for MAIN_R5F0_1 */
+ status = "reserved";
+ };
+
+ watchdog8: watchdog@23e0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23e0000 0x00 0x100>;
+ clocks = <&k3_clks 260 1>;
+ power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 260 1>;
+ assigned-clock-parents = <&k3_clks 260 5>;
+ /* reserved for MAIN_R5F1_0 */
+ status = "reserved";
+ };
+
+ watchdog9: watchdog@23f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23f0000 0x00 0x100>;
+ clocks = <&k3_clks 261 1>;
+ power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 261 1>;
+ assigned-clock-parents = <&k3_clks 261 5>;
+ /* reserved for MAIN_R5F1_1 */
+ status = "reserved";
+ };
+
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721e-r5fss";
ti,cluster-mode = <1>;
--
2.34.1
Hi Neha
On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
> Add the WKUP ESM instance for J721E. It has three instances in total,
> one in the MAIN domain (main_esm) and two in the MCU-WKUP domain
> (mcu_esm and wkup_esm).
>
> Signed-off-by: Neha Malcom Francis <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> index 4618b697fbc4..b0f41e9829cc 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> @@ -689,4 +689,9 @@ mcu_esm: esm@40800000 {
> ti,esm-pins = <95>;
> bootph-pre-ram;
> };
> +
> + wkup_esm: esm@42080000 {
> + compatible = "ti,j721e-esm";
> + reg = <0x00 0x42080000 0x00 0x1000>;
I think , only esm@40800000 should be good for this SOC.
I am not sure, why you want to add this. If you still want to add this
for completeness ,
then two options, I suggest
1) If you plan to use this mention bootph-pre-ram and ti,esm-pins
2) In case , no plan to use this then please mark node as disabled
> + };
> };
Hi Neha
On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
> There are 10 watchdog instances in the MAIN domain:
> * one each for the 2 A72 cores
> * one for the GPU core
> * one for the C7x core
> * one each for the 2 C66x cores
> * one each for the 4 R5F cores
>
> Currently, the devicetree only describes watchdog instances for the A72
> cores and enables them. Describe the remaining but reserve them as they
> will be used by their respective firmware.
>
> Signed-off-by: Neha Malcom Francis <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 93 +++++++++++++++++++++++
> 1 file changed, 93 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index c7eafbc862f9..d8930b8ea8ec 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -2157,6 +2157,99 @@ watchdog1: watchdog@2210000 {
> assigned-clock-parents = <&k3_clks 253 5>;
> };
>
Looking at TRM, SPRUIJ7*3–December 2018–Revised March 2019,
Table 12-22646. RTI Instances, says There is gap in numbering
RTI0, RTI1, RTI15 and so on
IMO, labels for watchdog should be as per TRM.
eg watchdog2 to watchdog15, But I don't have strong opinion on either .
Let maintainer suggest on this
> + /*
> + * The following RTI instances are coupled with MCU R5Fs, c7x and
> + * GPU so keeping them reserved as these will be used by their
> + * respective firmware
> + */
> + watchdog2: watchdog@22f0000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x22f0000 0x00 0x100>;
> + clocks = <&k3_clks 257 1>;
> + power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 257 1>;
> + assigned-clock-parents = <&k3_clks 257 5>;
> + /* reserved for GPU */
> + status = "reserved";
> + };
Please help me to understand, where from you got it for GPU,
May be I am looking at wrong data, Again above TRM
Table 12-22645. RTI Hardware Requests. RTI-15 says esm0
> +
> + watchdog3: watchdog@2300000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x2300000 0x00 0x100>;
> + clocks = <&k3_clks 256 1>;
> + power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 256 1>;
> + assigned-clock-parents = <&k3_clks 256 5>;
> + /* reserved for C7X */
> + status = "reserved";
This I see in above table for Compute Cluster
> + };
> +
> + watchdog4: watchdog@2380000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x2380000 0x00 0x100>;
> + clocks = <&k3_clks 254 1>;
> + power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 254 1>;
> + assigned-clock-parents = <&k3_clks 254 5>;
> + /* reserved for C66X_0 */
> + status = "reserved";
> + };
> +
> + watchdog5: watchdog@2390000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x2390000 0x00 0x100>;
> + clocks = <&k3_clks 255 1>;
> + power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 255 1>;
> + assigned-clock-parents = <&k3_clks 255 5>;
> + /* reserved for C66X_1 */
> + status = "reserved";
> + };
> +
> + watchdog6: watchdog@23c0000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x23c0000 0x00 0x100>;
> + clocks = <&k3_clks 258 1>;
> + power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 258 1>;
> + assigned-clock-parents = <&k3_clks 258 5>;
> + /* reserved for MAIN_R5F0_0 */
TRM says, this covers both MAIN_R5F0_0 and MAIN_R5F0_1.
Suggest , if split is done at fw level
> + status = "reserved";
> + };
> +
> + watchdog7: watchdog@23d0000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x23d0000 0x00 0x100>;
> + clocks = <&k3_clks 259 1>;
> + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 259 1>;
> + assigned-clock-parents = <&k3_clks 259 5>;
> + /* reserved for MAIN_R5F0_1 */
> + status = "reserved";
TRM says, this covers both MAIN_R5F0_0 and MAIN_R5F0_1.
Suggest , if split is done at fw level
> + };
> +
> + watchdog8: watchdog@23e0000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x23e0000 0x00 0x100>;
> + clocks = <&k3_clks 260 1>;
> + power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 260 1>;
> + assigned-clock-parents = <&k3_clks 260 5>;
> + /* reserved for MAIN_R5F1_0 */
> + status = "reserved";
> + };
TRM says, this covers both MAIN_R5F1_0 and MAIN_R5F1_1.
Suggest , if split is done at fw level
> +
> + watchdog9: watchdog@23f0000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x23f0000 0x00 0x100>;
> + clocks = <&k3_clks 261 1>;
> + power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 261 1>;
> + assigned-clock-parents = <&k3_clks 261 5>;
> + /* reserved for MAIN_R5F1_1 */
TRM says, this covers both MAIN_R5F1_0 and MAIN_R5F1_1.
Suggest , if split is done at fw level
> + status = "reserved";
> + };
> +
> main_r5fss0: r5fss@5c00000 {
> compatible = "ti,j721e-r5fss";
> ti,cluster-mode = <1>;
Hi Udit,
On 10/04/24 10:42, Kumar, Udit wrote:
> Hi Neha
>
> On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
>> Add the WKUP ESM instance for J721E. It has three instances in total,
>> one in the MAIN domain (main_esm) and two in the MCU-WKUP domain
>> (mcu_esm and wkup_esm).
>>
>> Signed-off-by: Neha Malcom Francis <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
>> b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
>> index 4618b697fbc4..b0f41e9829cc 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
>> @@ -689,4 +689,9 @@ mcu_esm: esm@40800000 {
>> ti,esm-pins = <95>;
>> bootph-pre-ram;
>> };
>> +
>> + wkup_esm: esm@42080000 {
>> + compatible = "ti,j721e-esm";
>> + reg = <0x00 0x42080000 0x00 0x1000>;
>
> I think , only esm@40800000 should be good for this SOC.
>
> I am not sure, why you want to add this. If you still want to add this for
> completeness ,
Yes, I wanted to make sure all ESM modules are present for DTS completeness.
>
> then two options, I suggest
>
> 1) If you plan to use this mention bootph-pre-ram and ti,esm-pins
>
No plans for using it as of now.
J721E ESM interrupt routing is such that the MAIN_ESM interrupt triggers an
error event in the MCU_ESM (which is correctly set via their node ti,j721e-esm
glue logic pins). The MCU_ESM and WKUP_ESM both generate the same interrupt
after. So there is no ti,j721e-esm pin applicable for WKUP_ESM.
> 2) In case , no plan to use this then please mark node as disabled
>
Yes I will mark this as disabled, I overlooked the fact that leaving this
enabled would throw "ESM init failed" when DT syncs with U-Boot. Thanks for
catching!
>
>> + };
>> };
--
Thanking You
Neha Malcom Francis
Hi Neha
On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
> There are 2 watchdog instances in the MCU domain. These instances are
> coupled with the MCU domain R55 instances. Reserve them as they are not
> used by A72.
>
> Signed-off-by: Neha Malcom Francis <[email protected]>
> ---
> .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> index b0f41e9829cc..867f307909be 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> @@ -694,4 +694,30 @@ wkup_esm: esm@42080000 {
> compatible = "ti,j721e-esm";
> reg = <0x00 0x42080000 0x00 0x1000>;
> };
> +
> + /*
> + * The 2 RTI instances are couple with MCU R5Fs so keeping them
> + * reserved as these will be used by their respective firmware
> + */
> + mcu_watchdog0: watchdog@40600000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x40600000 0x00 0x100>;
> + clocks = <&k3_clks 262 1>;
> + power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 262 1>;
> + assigned-clock-parents = <&k3_clks 262 5>;
> + /* reserved for MCU_R5F0_0 */
> + status = "reserved";
> + };
> +
> + mcu_watchdog1: watchdog@40610000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x40610000 0x00 0x100>;
> + clocks = <&k3_clks 263 1>;
> + power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 263 1>;
> + assigned-clock-parents = <&k3_clks 263 5>;
> + /* reserved for MCU_R5F0_1 */
Table 12-22642. MCU_RTI Hardware Requests (In same TRM referred in 3/4
patch review ),
says each WDT has destination of MCU0_R5_CORE0 and MCU0_R5_CORE1
Please suggest, if fw level this is decided to reserved like above ?
With that clarification, Please use
Reviewed-by: Udit Kumar <[email protected]>
> + status = "reserved";
> + };
> };
Hi Udit,
On 10/04/24 11:06, Kumar, Udit wrote:
> Hi Neha
>
> On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
>> There are 10 watchdog instances in the MAIN domain:
>> * one each for the 2 A72 cores
>> * one for the GPU core
>> * one for the C7x core
>> * one each for the 2 C66x cores
>> * one each for the 4 R5F cores
>>
>> Currently, the devicetree only describes watchdog instances for the A72
>> cores and enables them. Describe the remaining but reserve them as they
>> will be used by their respective firmware.
>>
>> Signed-off-by: Neha Malcom Francis <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 93 +++++++++++++++++++++++
>> 1 file changed, 93 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index c7eafbc862f9..d8930b8ea8ec 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -2157,6 +2157,99 @@ watchdog1: watchdog@2210000 {
>> assigned-clock-parents = <&k3_clks 253 5>;
>> };
>
> Looking at TRM, SPRUIJ7*3–December 2018–Revised March 2019,
>
> Table 12-22646. RTI Instances, says There is gap in numbering
>
> RTI0, RTI1, RTI15 and so on
>
> IMO, labels for watchdog should be as per TRM.
>
> eg watchdog2 to watchdog15, But I don't have strong opinion on either .
>
> Let maintainer suggest on this
>
Yes, perhaps sticking to the TRM numbering with gaps will improve readability. I
can change that in next version if no objections.
>
>
>> + /*
>> + * The following RTI instances are coupled with MCU R5Fs, c7x and
>> + * GPU so keeping them reserved as these will be used by their
>> + * respective firmware
>> + */
>> + watchdog2: watchdog@22f0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x22f0000 0x00 0x100>;
>> + clocks = <&k3_clks 257 1>;
>> + power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 257 1>;
>> + assigned-clock-parents = <&k3_clks 257 5>;
>> + /* reserved for GPU */
>> + status = "reserved";
>> + };
>
> Please help me to understand, where from you got it for GPU,
>
> May be I am looking at wrong data, Again above TRM
>
> Table 12-22645. RTI Hardware Requests. RTI-15 says esm0
>
The table you are looking at mentions where the interrupt from the watchdog is
routed to.
In the TRM, in sub-section 12.10.2 Windowed Watchdog Timer (WWDT) > 12.19.2.1
RTI Overview; it is mentioned that RTI15 is dedicated to the GPU.
>> +
>> + watchdog3: watchdog@2300000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2300000 0x00 0x100>;
>> + clocks = <&k3_clks 256 1>;
>> + power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 256 1>;
>> + assigned-clock-parents = <&k3_clks 256 5>;
>> + /* reserved for C7X */
>> + status = "reserved";
>
> This I see in above table for Compute Cluster
>
>
>> + };
>> +
>> + watchdog4: watchdog@2380000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2380000 0x00 0x100>;
>> + clocks = <&k3_clks 254 1>;
>> + power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 254 1>;
>> + assigned-clock-parents = <&k3_clks 254 5>;
>> + /* reserved for C66X_0 */
>> + status = "reserved";
>> + };
>> +
>> + watchdog5: watchdog@2390000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2390000 0x00 0x100>;
>> + clocks = <&k3_clks 255 1>;
>> + power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 255 1>;
>> + assigned-clock-parents = <&k3_clks 255 5>;
>> + /* reserved for C66X_1 */
>> + status = "reserved";
>> + };
>> +
>> + watchdog6: watchdog@23c0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23c0000 0x00 0x100>;
>> + clocks = <&k3_clks 258 1>;
>> + power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 258 1>;
>> + assigned-clock-parents = <&k3_clks 258 5>;
>> + /* reserved for MAIN_R5F0_0 */
>
> TRM says, this covers both MAIN_R5F0_0 and MAIN_R5F0_1.
>
> Suggest , if split is done at fw level
>
>> + status = "reserved";
>> + };
>> +
>> + watchdog7: watchdog@23d0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23d0000 0x00 0x100>;
>> + clocks = <&k3_clks 259 1>;
>> + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 259 1>;
>> + assigned-clock-parents = <&k3_clks 259 5>;
>> + /* reserved for MAIN_R5F0_1 */
>> + status = "reserved";
>
> TRM says, this covers both MAIN_R5F0_0 and MAIN_R5F0_1.
>
> Suggest , if split is done at fw level
I didn't quite understand, these watchdogs are mentioned only for DTS
completeness sake.
>
>> + };
>> +
>> + watchdog8: watchdog@23e0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23e0000 0x00 0x100>;
>> + clocks = <&k3_clks 260 1>;
>> + power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 260 1>;
>> + assigned-clock-parents = <&k3_clks 260 5>;
>> + /* reserved for MAIN_R5F1_0 */
>> + status = "reserved";
>> + };
>
>
> TRM says, this covers both MAIN_R5F1_0 and MAIN_R5F1_1.
>
> Suggest , if split is done at fw level
>
>> +
>> + watchdog9: watchdog@23f0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23f0000 0x00 0x100>;
>> + clocks = <&k3_clks 261 1>;
>> + power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 261 1>;
>> + assigned-clock-parents = <&k3_clks 261 5>;
>> + /* reserved for MAIN_R5F1_1 */
>
> TRM says, this covers both MAIN_R5F1_0 and MAIN_R5F1_1.
>
> Suggest , if split is done at fw level
>
>> + status = "reserved";
>> + };
>> +
>> main_r5fss0: r5fss@5c00000 {
>> compatible = "ti,j721e-r5fss";
>> ti,cluster-mode = <1>;
--
Thanking You
Neha Malcom Francis
Hi Udit
On 10/04/24 11:35, Kumar, Udit wrote:
> Hi Neha
>
> On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
>> There are 4 watchdog instances in the MAIN domain:
>> * one each for the 2 A72 cores
>> * one each for the 2 R5F cores
>>
>> Currently, the devicetree only describes watchdog instances for the A72
>> cores and enables them. Describe the remaining but reserve them as they
>> will be used by their respective firmware.
>>
>> Signed-off-by: Neha Malcom Francis <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 27 +++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> index 657f9cc9f4ea..c448c2218e23 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> @@ -1254,6 +1254,33 @@ watchdog1: watchdog@2210000 {
>> assigned-clock-parents = <&k3_clks 253 5>;
>> };
>> + /*
>> + * The following RTI instances are coupled with MCU R5Fs so
>> + * keeping them reserved as these will be used by their respective
>> + * firmware
>> + */
>> + watchdog2: watchdog@23c0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23c0000 0x00 0x100>;
>> + clocks = <&k3_clks 258 1>;
>> + power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 258 1>;
>> + assigned-clock-parents = <&k3_clks 258 5>;
>> + /* reserved for MAIN_R5F0_0 */
>> + status = "reserved";
>> + };
>> +
>> + watchdog3: watchdog@23d0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23d0000 0x00 0x100>;
>> + clocks = <&k3_clks 259 1>;
>> + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 259 1>;
>> + assigned-clock-parents = <&k3_clks 259 5>;
>> + /* reserved for MAIN_R5F0_1 */
>> + status = "reserved";
>> + };
>> +
>
> Please see, if this make more sense to have label as watchdog28 and watchdog29,
> to align with TRM.
Yes I will change all the patches in the series to align with TRM numbering.
>
> Also request to add mcu domain 2 watchdog as well.
Oh I had missed that out, will add it in v2.
>
>
>> main_timer0: timer@2400000 {
>> compatible = "ti,am654-timer";
>> reg = <0x00 0x2400000 0x00 0x400>;
--
Thanking You
Neha Malcom Francis
Hi Neha
On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
> There are 4 watchdog instances in the MAIN domain:
> * one each for the 2 A72 cores
> * one each for the 2 R5F cores
>
> Currently, the devicetree only describes watchdog instances for the A72
> cores and enables them. Describe the remaining but reserve them as they
> will be used by their respective firmware.
>
> Signed-off-by: Neha Malcom Francis <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 27 +++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 657f9cc9f4ea..c448c2218e23 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -1254,6 +1254,33 @@ watchdog1: watchdog@2210000 {
> assigned-clock-parents = <&k3_clks 253 5>;
> };
>
> + /*
> + * The following RTI instances are coupled with MCU R5Fs so
> + * keeping them reserved as these will be used by their respective
> + * firmware
> + */
> + watchdog2: watchdog@23c0000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x23c0000 0x00 0x100>;
> + clocks = <&k3_clks 258 1>;
> + power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 258 1>;
> + assigned-clock-parents = <&k3_clks 258 5>;
> + /* reserved for MAIN_R5F0_0 */
> + status = "reserved";
> + };
> +
> + watchdog3: watchdog@23d0000 {
> + compatible = "ti,j7-rti-wdt";
> + reg = <0x00 0x23d0000 0x00 0x100>;
> + clocks = <&k3_clks 259 1>;
> + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 259 1>;
> + assigned-clock-parents = <&k3_clks 259 5>;
> + /* reserved for MAIN_R5F0_1 */
> + status = "reserved";
> + };
> +
Please see, if this make more sense to have label as watchdog28 and
watchdog29, to align with TRM.
Also request to add mcu domain 2 watchdog as well.
> main_timer0: timer@2400000 {
> compatible = "ti,am654-timer";
> reg = <0x00 0x2400000 0x00 0x400>;
Hi Udit,
On 10/04/24 11:15, Kumar, Udit wrote:
> Hi Neha
>
> On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
>> There are 2 watchdog instances in the MCU domain. These instances are
>> coupled with the MCU domain R55 instances. Reserve them as they are not
>> used by A72.
>>
>> Signed-off-by: Neha Malcom Francis <[email protected]>
>> ---
>> .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 26 +++++++++++++++++++
>> 1 file changed, 26 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
>> b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
>> index b0f41e9829cc..867f307909be 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
>> @@ -694,4 +694,30 @@ wkup_esm: esm@42080000 {
>> compatible = "ti,j721e-esm";
>> reg = <0x00 0x42080000 0x00 0x1000>;
>> };
>> +
>> + /*
>> + * The 2 RTI instances are couple with MCU R5Fs so keeping them
>> + * reserved as these will be used by their respective firmware
>> + */
>> + mcu_watchdog0: watchdog@40600000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x40600000 0x00 0x100>;
>> + clocks = <&k3_clks 262 1>;
>> + power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 262 1>;
>> + assigned-clock-parents = <&k3_clks 262 5>;
>> + /* reserved for MCU_R5F0_0 */
>> + status = "reserved";
>> + };
>> +
>> + mcu_watchdog1: watchdog@40610000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x40610000 0x00 0x100>;
>> + clocks = <&k3_clks 263 1>;
>> + power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 263 1>;
>> + assigned-clock-parents = <&k3_clks 263 5>;
>> + /* reserved for MCU_R5F0_1 */
>
> Table 12-22642. MCU_RTI Hardware Requests (In same TRM referred in 3/4 patch
> review ),
>
> says each WDT has destination of MCU0_R5_CORE0 and MCU0_R5_CORE1
>
> Please suggest, if fw level this is decided to reserved like above ?
>
> With that clarification, Please use
>
> Reviewed-by: Udit Kumar <[email protected]>
>
>
At firmware level, the MCU R5 is in lockstep mode. The dual destination of the
WDT interrupt makes sense then.
>> + status = "reserved";
>> + };
>> };
--
Thanking You
Neha Malcom Francis
Hi Udit
On 10/04/24 11:06, Kumar, Udit wrote:
> Hi Neha
>
> On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
>> There are 10 watchdog instances in the MAIN domain:
>> * one each for the 2 A72 cores
>> * one for the GPU core
>> * one for the C7x core
>> * one each for the 2 C66x cores
>> * one each for the 4 R5F cores
>>
>> Currently, the devicetree only describes watchdog instances for the A72
>> cores and enables them. Describe the remaining but reserve them as they
>> will be used by their respective firmware.
>>
>> Signed-off-by: Neha Malcom Francis <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 93 +++++++++++++++++++++++
>> 1 file changed, 93 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index c7eafbc862f9..d8930b8ea8ec 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -2157,6 +2157,99 @@ watchdog1: watchdog@2210000 {
>> assigned-clock-parents = <&k3_clks 253 5>;
>> };
>
> Looking at TRM, SPRUIJ7*3–December 2018–Revised March 2019,
>
> Table 12-22646. RTI Instances, says There is gap in numbering
>
> RTI0, RTI1, RTI15 and so on
>
> IMO, labels for watchdog should be as per TRM.
>
> eg watchdog2 to watchdog15, But I don't have strong opinion on either .
>
> Let maintainer suggest on this
>
>
>
>> + /*
>> + * The following RTI instances are coupled with MCU R5Fs, c7x and
>> + * GPU so keeping them reserved as these will be used by their
>> + * respective firmware
>> + */
>> + watchdog2: watchdog@22f0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x22f0000 0x00 0x100>;
>> + clocks = <&k3_clks 257 1>;
>> + power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 257 1>;
>> + assigned-clock-parents = <&k3_clks 257 5>;
>> + /* reserved for GPU */
>> + status = "reserved";
>> + };
>
> Please help me to understand, where from you got it for GPU,
>
> May be I am looking at wrong data, Again above TRM
>
> Table 12-22645. RTI Hardware Requests. RTI-15 says esm0
>
>> +
>> + watchdog3: watchdog@2300000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2300000 0x00 0x100>;
>> + clocks = <&k3_clks 256 1>;
>> + power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 256 1>;
>> + assigned-clock-parents = <&k3_clks 256 5>;
>> + /* reserved for C7X */
>> + status = "reserved";
>
> This I see in above table for Compute Cluster
>
>
>> + };
>> +
>> + watchdog4: watchdog@2380000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2380000 0x00 0x100>;
>> + clocks = <&k3_clks 254 1>;
>> + power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 254 1>;
>> + assigned-clock-parents = <&k3_clks 254 5>;
>> + /* reserved for C66X_0 */
>> + status = "reserved";
>> + };
>> +
>> + watchdog5: watchdog@2390000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2390000 0x00 0x100>;
>> + clocks = <&k3_clks 255 1>;
>> + power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 255 1>;
>> + assigned-clock-parents = <&k3_clks 255 5>;
>> + /* reserved for C66X_1 */
>> + status = "reserved";
>> + };
>> +
>> + watchdog6: watchdog@23c0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23c0000 0x00 0x100>;
>> + clocks = <&k3_clks 258 1>;
>> + power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 258 1>;
>> + assigned-clock-parents = <&k3_clks 258 5>;
>> + /* reserved for MAIN_R5F0_0 */
>
> TRM says, this covers both MAIN_R5F0_0 and MAIN_R5F0_1.
>
> Suggest , if split is done at fw level
>
>> + status = "reserved";
>> + };
>> +
>> + watchdog7: watchdog@23d0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23d0000 0x00 0x100>;
>> + clocks = <&k3_clks 259 1>;
>> + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 259 1>;
>> + assigned-clock-parents = <&k3_clks 259 5>;
>> + /* reserved for MAIN_R5F0_1 */
>> + status = "reserved";
>
> TRM says, this covers both MAIN_R5F0_0 and MAIN_R5F0_1.
>
> Suggest , if split is done at fw level
>
>> + };
>> +
>> + watchdog8: watchdog@23e0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23e0000 0x00 0x100>;
>> + clocks = <&k3_clks 260 1>;
>> + power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 260 1>;
>> + assigned-clock-parents = <&k3_clks 260 5>;
>> + /* reserved for MAIN_R5F1_0 */
>> + status = "reserved";
>> + };
>
>
> TRM says, this covers both MAIN_R5F1_0 and MAIN_R5F1_1.
>
> Suggest , if split is done at fw level
>
>> +
>> + watchdog9: watchdog@23f0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23f0000 0x00 0x100>;
>> + clocks = <&k3_clks 261 1>;
>> + power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 261 1>;
>> + assigned-clock-parents = <&k3_clks 261 5>;
>> + /* reserved for MAIN_R5F1_1 */
>
> TRM says, this covers both MAIN_R5F1_0 and MAIN_R5F1_1.
>
> Suggest , if split is done at fw level
>
>> + status = "reserved";
>> + };
>> +
>> main_r5fss0: r5fss@5c00000 {
>> compatible = "ti,j721e-r5fss";
>> ti,cluster-mode = <1>;
At firmware level, the MAIN R5s are set to split mode.
--
Thanking You
Neha Malcom Francis