From: Xinlei Lee <[email protected]>
The panel spec stipulates that after lcm_reset is pulled high, cmd
should be sent to initialize the panel. Within the allowable range of
the DSI spec, this time needs to be reduced to avoid panel exceptions.
Xinlei Lee (2):
drm/mediatek: dsi: Reduce the time of dsi from LP11 to sending cmd
drm/panel: boe-tv101wum-nl6: Reduce lcm_reset to send initial code
time
drivers/gpu/drm/mediatek/mtk_dsi.c | 2 +-
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
--
2.18.0
From: Xinlei Lee <[email protected]>
According to Figure 16 Turnaround Procedure on page 36 in [1], you
can see the status of LP-00 -> LP10 -> LP11. This state can correspond
to the state of DSI from LP00 -> LP11 in mtk_dsi_lane_ready function
in mtk_dsi.c.
LP-00 -> LP10 -> LP11 takes about 2*TLPX time (refer to [1] page 51
to see that TLPX is 50ns).
The delay at the end of the mtk_dsi_lane_ready function should be
greater than the 2*TLPX specified by the DSI spec, and less than
the time specified by the DSI_RX (generally 6ms to 40ms), to avoid
problems caused by the RX specification.
[1]:mipi_D-PHY_specification_v1-1
Fixes: 39e8d062b03c ("drm/mediatek: Keep dsi as LP00 before dcs cmds transfer")
Signed-off-by: Xinlei Lee <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 3b7d13028fb6..9e1363c9fcdb 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -721,7 +721,7 @@ static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
mtk_dsi_clk_ulp_mode_leave(dsi);
mtk_dsi_lane0_ulp_mode_leave(dsi);
mtk_dsi_clk_hs_mode(dsi, 0);
- msleep(20);
+ usleep_range(1000, 3000);
/* The reaction time after pulling up the mipi signal for dsi_rx */
}
}
--
2.18.0
From: Xinlei Lee <[email protected]>
Since the panel spec stipulates that the time from lcm_reset to DSI to
send the initial code should be greater than 6ms and less than 40ms,
so reduce the delay before sending the initial code and avoid panel
exceptions.
Fixes: a869b9db7adf ("drm/panel: support for boe tv101wum-nl6 wuxga dsi video mode panel")
Signed-off-by: Xinlei Lee <[email protected]>
---
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index 857a2f0420d7..f0093035f1ff 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -780,7 +780,6 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = {
};
static const struct panel_init_cmd boe_init_cmd[] = {
- _INIT_DELAY_CMD(24),
_INIT_DCS_CMD(0xB0, 0x05),
_INIT_DCS_CMD(0xB1, 0xE5),
_INIT_DCS_CMD(0xB3, 0x52),
--
2.18.0
On Fri, Jan 06, 2023 at 11:05:20AM +0800, [email protected] wrote:
> From: Xinlei Lee <[email protected]>
>
> According to Figure 16 Turnaround Procedure on page 36 in [1], you
> can see the status of LP-00 -> LP10 -> LP11. This state can correspond
> to the state of DSI from LP00 -> LP11 in mtk_dsi_lane_ready function
> in mtk_dsi.c.
>
> LP-00 -> LP10 -> LP11 takes about 2*TLPX time (refer to [1] page 51
> to see that TLPX is 50ns).
>
> The delay at the end of the mtk_dsi_lane_ready function should be
> greater than the 2*TLPX specified by the DSI spec, and less than
> the time specified by the DSI_RX (generally 6ms to 40ms), to avoid
> problems caused by the RX specification.
>
> [1]:mipi_D-PHY_specification_v1-1
>
> Fixes: 39e8d062b03c ("drm/mediatek: Keep dsi as LP00 before dcs cmds transfer")
> Signed-off-by: Xinlei Lee <[email protected]>
Seems OK.
Acked-by: Sam Ravnborg <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 3b7d13028fb6..9e1363c9fcdb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -721,7 +721,7 @@ static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
> mtk_dsi_clk_ulp_mode_leave(dsi);
> mtk_dsi_lane0_ulp_mode_leave(dsi);
> mtk_dsi_clk_hs_mode(dsi, 0);
> - msleep(20);
> + usleep_range(1000, 3000);
> /* The reaction time after pulling up the mipi signal for dsi_rx */
> }
> }
> --
> 2.18.0
On Fri, Jan 06, 2023 at 11:05:21AM +0800, [email protected] wrote:
> From: Xinlei Lee <[email protected]>
>
> Since the panel spec stipulates that the time from lcm_reset to DSI to
> send the initial code should be greater than 6ms and less than 40ms,
> so reduce the delay before sending the initial code and avoid panel
> exceptions.
The changelog says "reduce the delay", but the patch removes the delay.
Are there other delays that make sure the "greater than 6 ms" is OK?
Sam
>
> Fixes: a869b9db7adf ("drm/panel: support for boe tv101wum-nl6 wuxga dsi video mode panel")
> Signed-off-by: Xinlei Lee <[email protected]>
> ---
> drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> index 857a2f0420d7..f0093035f1ff 100644
> --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> @@ -780,7 +780,6 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = {
> };
>
> static const struct panel_init_cmd boe_init_cmd[] = {
> - _INIT_DELAY_CMD(24),
> _INIT_DCS_CMD(0xB0, 0x05),
> _INIT_DCS_CMD(0xB1, 0xE5),
> _INIT_DCS_CMD(0xB3, 0x52),
> --
> 2.18.0
Il 06/01/23 04:05, [email protected] ha scritto:
> From: Xinlei Lee <[email protected]>
>
> Since the panel spec stipulates that the time from lcm_reset to DSI to
> send the initial code should be greater than 6ms and less than 40ms,
> so reduce the delay before sending the initial code and avoid panel
> exceptions.
>
> Fixes: a869b9db7adf ("drm/panel: support for boe tv101wum-nl6 wuxga dsi video mode panel")
> Signed-off-by: Xinlei Lee <[email protected]>
> ---
> drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> index 857a2f0420d7..f0093035f1ff 100644
> --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> @@ -780,7 +780,6 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = {
> };
>
> static const struct panel_init_cmd boe_init_cmd[] = {
> - _INIT_DELAY_CMD(24),
You said that should be greater than 6 and less than 40: perhaps on MediaTek
platforms removing this delay is fine but we don't know about others - and this
driver is for all platforms.
To stay on the safe side you should, at this point, replace this delay with
_INIT_DELAY_CMD(7);
Regards,
Angelo
Il 06/01/23 04:05, [email protected] ha scritto:
> From: Xinlei Lee <[email protected]>
>
> According to Figure 16 Turnaround Procedure on page 36 in [1], you
> can see the status of LP-00 -> LP10 -> LP11. This state can correspond
> to the state of DSI from LP00 -> LP11 in mtk_dsi_lane_ready function
> in mtk_dsi.c.
>
> LP-00 -> LP10 -> LP11 takes about 2*TLPX time (refer to [1] page 51
> to see that TLPX is 50ns).
>
> The delay at the end of the mtk_dsi_lane_ready function should be
> greater than the 2*TLPX specified by the DSI spec, and less than
> the time specified by the DSI_RX (generally 6ms to 40ms), to avoid
> problems caused by the RX specification.
>
> [1]:mipi_D-PHY_specification_v1-1
>
> Fixes: 39e8d062b03c ("drm/mediatek: Keep dsi as LP00 before dcs cmds transfer")
> Signed-off-by: Xinlei Lee <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
On Mon, 2023-01-09 at 12:25 +0100, AngeloGioacchino Del Regno wrote:
> Il 06/01/23 04:05, [email protected] ha scritto:
> > From: Xinlei Lee <[email protected]>
> >
> > Since the panel spec stipulates that the time from lcm_reset to DSI
> > to
> > send the initial code should be greater than 6ms and less than
> > 40ms,
> > so reduce the delay before sending the initial code and avoid panel
> > exceptions.
> >
> > Fixes: a869b9db7adf ("drm/panel: support for boe tv101wum-nl6 wuxga
> > dsi video mode panel")
> > Signed-off-by: Xinlei Lee <[email protected]>
> > ---
> > drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > index 857a2f0420d7..f0093035f1ff 100644
> > --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > @@ -780,7 +780,6 @@ static const struct panel_init_cmd
> > inx_hj110iz_init_cmd[] = {
> > };
> >
> > static const struct panel_init_cmd boe_init_cmd[] = {
> > - _INIT_DELAY_CMD(24),
>
> You said that should be greater than 6 and less than 40: perhaps on
> MediaTek
> platforms removing this delay is fine but we don't know about others
> - and this
> driver is for all platforms.
>
> To stay on the safe side you should, at this point, replace this
> delay with
>
> _INIT_DELAY_CMD(7);
>
> Regards,
> Angelo
>
Hi Angelo:
Thanks for your reply!
Please allow me to explain, in another dsi modification of this
series, I reduced the delay of dsi's LP00->LP11 stage from 20ms to 1ms
(to comply with dsi spec), in fact, in this file, the
boe_panel_prepare function The 6ms delay after pulling up lcm_reset
is before the 1ms mentioned just now, which ensures that the delay is
within the specified range (7ms).
Do you still have doubts about my explanation?
Best Regards!
xinlei
On Sat, 2023-01-07 at 21:31 +0100, Sam Ravnborg wrote:
> On Fri, Jan 06, 2023 at 11:05:21AM +0800, [email protected]
> wrote:
> > From: Xinlei Lee <[email protected]>
> >
> > Since the panel spec stipulates that the time from lcm_reset to DSI
> > to
> > send the initial code should be greater than 6ms and less than
> > 40ms,
> > so reduce the delay before sending the initial code and avoid panel
> > exceptions.
>
> The changelog says "reduce the delay", but the patch removes the
> delay.
> Are there other delays that make sure the "greater than 6 ms" is OK?
>
> Sam
>
> >
> > Fixes: a869b9db7adf ("drm/panel: support for boe tv101wum-nl6 wuxga
> > dsi video mode panel")
> > Signed-off-by: Xinlei Lee <[email protected]>
> > ---
> > drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > index 857a2f0420d7..f0093035f1ff 100644
> > --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > @@ -780,7 +780,6 @@ static const struct panel_init_cmd
> > inx_hj110iz_init_cmd[] = {
> > };
> >
> > static const struct panel_init_cmd boe_init_cmd[] = {
> > - _INIT_DELAY_CMD(24),
> > _INIT_DCS_CMD(0xB0, 0x05),
> > _INIT_DCS_CMD(0xB1, 0xE5),
> > _INIT_DCS_CMD(0xB3, 0x52),
> > --
> > 2.18.0
Hi Sam:
Thanks for your reply!
Please allow me to explain, in the boe_panel_prepare function in this
file, there will be a 6ms delay after the reset pin is pulled high
(gpiod_set_value(boe->enable_gpio, 1)), and the initial code will be
sent in the boe_panel_init_dcs_cmd function later, This period of time
ensures that the delay is within the specified range.
In addition, I will add a special panel control in the V2 version, if
you have any questions, we will discuss it later.
Best Regards!
xinlei
On Sat, 2023-01-07 at 21:31 +0100, Sam Ravnborg wrote:
> On Fri, Jan 06, 2023 at 11:05:21AM +0800, [email protected]
> wrote:
> > From: Xinlei Lee <[email protected]>
> >
> > Since the panel spec stipulates that the time from lcm_reset to DSI
> > to
> > send the initial code should be greater than 6ms and less than
> > 40ms,
> > so reduce the delay before sending the initial code and avoid panel
> > exceptions.
>
> The changelog says "reduce the delay", but the patch removes the
> delay.
> Are there other delays that make sure the "greater than 6 ms" is OK?
>
> Sam
>
> >
> > Fixes: a869b9db7adf ("drm/panel: support for boe tv101wum-nl6 wuxga
> > dsi video mode panel")
> > Signed-off-by: Xinlei Lee <[email protected]>
> > ---
> > drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > index 857a2f0420d7..f0093035f1ff 100644
> > --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > @@ -780,7 +780,6 @@ static const struct panel_init_cmd
> > inx_hj110iz_init_cmd[] = {
> > };
> >
> > static const struct panel_init_cmd boe_init_cmd[] = {
> > - _INIT_DELAY_CMD(24),
> > _INIT_DCS_CMD(0xB0, 0x05),
> > _INIT_DCS_CMD(0xB1, 0xE5),
> > _INIT_DCS_CMD(0xB3, 0x52),
> > --
> > 2.18.0
Hi Sam:
Thanks for your reply!
Please allow me to explain, in the boe_panel_prepare function in this
file, there will be a 6ms delay after the reset pin is pulled high
(gpiod_set_value(boe->enable_gpio, 1)), and the initial code will be
sent in the boe_panel_init_dcs_cmd function later, This period of time
ensures that the delay is within the specified range.
In addition, I will add a special panel control in the V2 version, if
you have any questions, we will discuss it later.
Best Regards!
xinlei