We observed soft-lockup on the host in a specific scenario where
the host on Ampere's Altra Max CPU has 64KB base page size and the
guest has 4KB base page size, 64 vCPUs and 13GB memory. The guest's
memory is backed by 512MB huge pages via hugetlbfs. All the 64 vCPUs
are simultaneously trapped into the host due to permission page faults,
to request adding the execution permission to the corresponding PMD
entry, before the soft-lockup is raised on the host. On handling the
parallel requests, the instruction cache for the 512MB huge page is
invalidated by mm_ops->icache_inval_pou() in stage2_attr_walker() on
64 hardware CPUs. Unfortunately, the instruction cache invalidation
on one CPU interfere with that on another CPU in the hardware level.
It takes 37 seconds for mm_ops->icache_inval_pou() to finish in the
worst case.
So we can't scale out to handle the permission faults at will. They
need to be serialized to some extent with the help of a interval tree,
to track IPA ranges, currently under service. For the incoming permission
faults, the vCPU is asked to bail for a retry if its IPA range is being
served since the vCPU can't proceed its execution.
Fixes: 1577cb5823ce ("KVM: arm64: Handle stage-2 faults in parallel")
Cc: [email protected] # v6.2+
Reported-by: Yihuang Yu <[email protected]>
Reported-by: Zhenyu Zhang <[email protected]>
Signed-off-by: Gavin Shan <[email protected]>
---
arch/arm64/include/asm/kvm_host.h | 4 ++
arch/arm64/include/asm/kvm_pgtable.h | 3 +-
arch/arm64/kvm/hyp/nvhe/mem_protect.c | 4 +-
arch/arm64/kvm/hyp/pgtable.c | 25 +++++++++---
arch/arm64/kvm/mmu.c | 55 ++++++++++++++++++++++++++-
5 files changed, 83 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index d3dd05bbfe23..a457720b5caf 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -175,6 +175,10 @@ struct kvm_s2_mmu {
struct kvm_mmu_memory_cache split_page_cache;
uint64_t split_page_chunk_size;
+ /* Page fault ranges */
+ struct mutex fault_ranges_mutex;
+ struct rb_root_cached fault_ranges;
+
struct kvm_arch *arch;
};
diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h
index 929d355eae0a..dca0bf81616f 100644
--- a/arch/arm64/include/asm/kvm_pgtable.h
+++ b/arch/arm64/include/asm/kvm_pgtable.h
@@ -149,7 +149,8 @@ struct kvm_pgtable_mm_ops {
void* (*phys_to_virt)(phys_addr_t phys);
phys_addr_t (*virt_to_phys)(void *addr);
void (*dcache_clean_inval_poc)(void *addr, size_t size);
- void (*icache_inval_pou)(void *addr, size_t size);
+ int (*icache_inval_pou)(struct kvm_s2_mmu *mmu,
+ void *addr, u64 ipa, size_t size);
};
/**
diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
index 9d703441278b..9bbe7c641770 100644
--- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
+++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
@@ -223,10 +223,12 @@ static void clean_dcache_guest_page(void *va, size_t size)
hyp_fixmap_unmap();
}
-static void invalidate_icache_guest_page(void *va, size_t size)
+static int invalidate_icache_guest_page(struct kvm_s2_mmu *mmu,
+ void *va, u64 ipa, size_t size)
{
__invalidate_icache_guest_page(hyp_fixmap_map(__hyp_pa(va)), size);
hyp_fixmap_unmap();
+ return 0;
}
int kvm_guest_prepare_stage2(struct pkvm_hyp_vm *vm, void *pgd)
diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
index f7a93ef29250..fabfdb4d1e00 100644
--- a/arch/arm64/kvm/hyp/pgtable.c
+++ b/arch/arm64/kvm/hyp/pgtable.c
@@ -875,6 +875,7 @@ static int stage2_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx,
u64 granule = kvm_granule_size(ctx->level);
struct kvm_pgtable *pgt = data->mmu->pgt;
struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops;
+ int ret;
if (!stage2_leaf_mapping_allowed(ctx, data))
return -E2BIG;
@@ -903,8 +904,14 @@ static int stage2_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx,
granule);
if (!kvm_pgtable_walk_skip_cmo(ctx) && mm_ops->icache_inval_pou &&
- stage2_pte_executable(new))
- mm_ops->icache_inval_pou(kvm_pte_follow(new, mm_ops), granule);
+ stage2_pte_executable(new)) {
+ ret = mm_ops->icache_inval_pou(data->mmu,
+ kvm_pte_follow(new, mm_ops),
+ ALIGN_DOWN(ctx->addr, granule),
+ granule);
+ if (ret)
+ return ret;
+ }
stage2_make_pte(ctx, new);
@@ -1101,6 +1108,7 @@ int kvm_pgtable_stage2_unmap(struct kvm_pgtable *pgt, u64 addr, u64 size)
}
struct stage2_attr_data {
+ struct kvm_s2_mmu *mmu;
kvm_pte_t attr_set;
kvm_pte_t attr_clr;
kvm_pte_t pte;
@@ -1113,6 +1121,8 @@ static int stage2_attr_walker(const struct kvm_pgtable_visit_ctx *ctx,
kvm_pte_t pte = ctx->old;
struct stage2_attr_data *data = ctx->arg;
struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops;
+ u64 granule = kvm_granule_size(ctx->level);
+ int ret;
if (!kvm_pte_valid(ctx->old))
return -EAGAIN;
@@ -1133,9 +1143,13 @@ static int stage2_attr_walker(const struct kvm_pgtable_visit_ctx *ctx,
* stage-2 PTE if we are going to add executable permission.
*/
if (mm_ops->icache_inval_pou &&
- stage2_pte_executable(pte) && !stage2_pte_executable(ctx->old))
- mm_ops->icache_inval_pou(kvm_pte_follow(pte, mm_ops),
- kvm_granule_size(ctx->level));
+ stage2_pte_executable(pte) && !stage2_pte_executable(ctx->old)) {
+ ret = mm_ops->icache_inval_pou(data->mmu,
+ kvm_pte_follow(pte, mm_ops),
+ ALIGN_DOWN(ctx->addr, granule), granule);
+ if (ret)
+ return ret;
+ }
if (!stage2_try_set_pte(ctx, pte))
return -EAGAIN;
@@ -1152,6 +1166,7 @@ static int stage2_update_leaf_attrs(struct kvm_pgtable *pgt, u64 addr,
int ret;
kvm_pte_t attr_mask = KVM_PTE_LEAF_ATTR_LO | KVM_PTE_LEAF_ATTR_HI;
struct stage2_attr_data data = {
+ .mmu = pgt->mmu,
.attr_set = attr_set & attr_mask,
.attr_clr = attr_clr & attr_mask,
};
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index d3b4feed460c..a778f48beb56 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -267,9 +267,58 @@ static void clean_dcache_guest_page(void *va, size_t size)
__clean_dcache_guest_page(va, size);
}
-static void invalidate_icache_guest_page(void *va, size_t size)
+static struct interval_tree_node *add_fault_range(struct kvm_s2_mmu *mmu,
+ u64 ipa, size_t size)
{
+ struct interval_tree_node *node;
+ unsigned long start = ipa, end = start + size - 1; /* inclusive */
+
+ mutex_lock(&mmu->fault_ranges_mutex);
+
+ node = interval_tree_iter_first(&mmu->fault_ranges, start, end);
+ if (node) {
+ node = NULL;
+ goto unlock;
+ }
+
+ node = kzalloc(sizeof(*node), GFP_KERNEL_ACCOUNT);
+ if (!node)
+ goto unlock;
+
+ node->start = start;
+ node->last = end;
+ interval_tree_insert(node, &mmu->fault_ranges);
+
+unlock:
+ mutex_unlock(&mmu->fault_ranges_mutex);
+ return node;
+}
+
+static void remove_fault_range(struct kvm_s2_mmu *mmu,
+ struct interval_tree_node *node)
+{
+ mutex_lock(&mmu->fault_ranges_mutex);
+
+ interval_tree_remove(node, &mmu->fault_ranges);
+ kfree(node);
+
+ mutex_unlock(&mmu->fault_ranges_mutex);
+}
+
+
+static int invalidate_icache_guest_page(struct kvm_s2_mmu *mmu,
+ void *va, u64 ipa, size_t size)
+{
+ struct interval_tree_node *node;
+
+ node = add_fault_range(mmu, ipa, size);
+ if (!node)
+ return -EAGAIN;
+
__invalidate_icache_guest_page(va, size);
+ remove_fault_range(mmu, node);
+
+ return 0;
}
/*
@@ -859,6 +908,10 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu, unsigned long t
mmu->split_page_chunk_size = KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT;
mmu->split_page_cache.gfp_zero = __GFP_ZERO;
+ /* Initialize the page fault ranges */
+ mutex_init(&mmu->fault_ranges_mutex);
+ mmu->fault_ranges = RB_ROOT_CACHED;
+
mmu->pgt = pgt;
mmu->pgd_phys = __pa(pgt->pgd);
return 0;
--
2.41.0
Hi Oliver,
On 9/7/23 02:29, Oliver Upton wrote:
> On Wed, Sep 06, 2023 at 08:26:24AM +1000, Gavin Shan wrote:
>
> [...]
>
>> It seems I didn't make it clear enough. The reason why I had the concern
>> to avoid reading ctr_el0 is we read ctr_el0 for twice in the following path,
>> but I doubt if anybody cares. Since it's a hot path, each bit of performance
>> gain will count.
>>
>> invalidate_icache_guest_page
>> __invalidate_icache_guest_page // first read on ctr_el0, with your code changes
>> icache_inval_pou(va, va + size)
>> invalidate_icache_by_line
>> icache_line_size // second read on ctr_el0
>
> That can be addressed by shoving the check deep into
> invalidate_icache_by_line, which would benefit _all_ use cases of
> I-cache invalidation by VA. I haven't completely made up my mind about
> that, though, because of the consequences of a global invalidation.
>
Yes, of course.
>>>> @size is guranteed to be PAGE_SIZE or PMD_SIZE aligned. Maybe
>>>> we can just aggressively do something like below, disregarding the icache thrashing.
>>>> In this way, the code is further simplified.
>>>>
>>>> if (size > PAGE_SIZE) {
>>>> icache_inval_all_pou();
>>>> } else {
>>>> icache_inval_pou((unsigned long)va,
>>>> (unsigned long)va + size);
>>>> } // parantheses is still needed
>>>
>>> This could work too but we already have a kernel heuristic for limiting
>>> the amount of broadcast invalidations, which is MAX_TLBI_OPS. I don't
>>> want to introduce a second, KVM-specific hack to address the exact same
>>> thing.
>>>
>>
>> Ok. I was confused at the first glance since TLB isn't relevant to icache.
>> I think it's fine to reuse MAX_TLBI_OPS here, but a comment may be needed.
>> Oliver, could you please send a formal patch for your changes?
>
> Yeah, I think I may have said it before, but this thing needs to be
> called 'MAX_DVM_OPS'. I-cache invalidations and TLB invalidations become
> DVMOps (Distributed Virtual Memory) in terms of CHI, which pile up at the
> miscellaneous node in the mesh.
>
> Give me a day or two to convince myself of the right way to go about
> this and I'll send out what I have.
>
Ok. 'MAX_DVM_OPS' sounds good and it's a new name to me anyway. Oliver,
please let me know if you don't have time for this and need me to file
the formal patches, based on your codes :)
Thanks,
Gavin