This patch series includes Tegra210 deepsleep support with RTC alarm
wake event.
This series also includes save and restore of PLLs, clocks, OSC contexts
for deepsleep exit to normal operation.
This patch series doesn't support 100% suspend/resume to allow fully
functional state upon resume and we are working on some more drivers suspend
and resume implementations.
[V5]: Changes between V4 & V5 are
- V4 feedback fixes
[V4]: Changes between V3 & V4 are
- V3 feedback fixes
- Removed park bits clear for EMMC pads in pinctrl-tegra driver
function tegra_pinctrl_clear_parked_bits as based on V3 feedback
parked_bit is updated to parked_bitmask to use with DRV_PINGROUP
as well and thierry posted patch series for this.
- Implemented all peripheral clocks save and restore through their
corresponding clk_ops save_context and restore_context and removed
all direct registers store and restore in clk-tegra210 driver.
- Created separate patch for fence_delay update during PLLU init based
on V3 feedback.
- Added more comments in tegra210_clk_resume regarding dfll restore
sequence and its dependency on peripheral clocks restore.
[V3]: Changes between V2 & V3 are
- V2 feedback fixes
- GPIO restore should happen prior to Pinctrl restore to prevent
glitch on GPIO lines. So using resume_noirq for gpio tegra to allow
gpio resume prior to pinctrl resume.
- Implemented save_context and restore_context callbacks for clock
plls, pll outs and dividers in corresponding drivers.
Note: Peripheral clocks and clock enable and reset need to be in
Tegra210 clock suspend/resume as they need to be in proper sequence
w.r.t DFLL resume for restoring CPU clock.
- Removed gpio-tegra changes for hierarchical support to have PMC as
parent to GPIOs for GPIO wake event support. Thierry is working on
gpiolib for some cleanup before adding hierarchical support. So
holding on to GPIO wake support for now.
[V2] : V1 feedback fixes
Patch 0002: This version still using syscore. Thierry suggest not to
use syscore and waiting on suggestion from Linux Walleij for any better
way of storing current state of pins before suspend entry and restoring
them on resume at very early stage. So left this the same way as V1 and
will address once I get more feedback on this.
Also need to findout and implement proper way of forcing resume order
between pinctrl and gpio driver.
[V1]: Tegra210 SC7 entry and exit thru RTC wake and Power button GPIO wake
using hierarchical IRQ with PMC as parent to GPIO.
Sowjanya Komatineni (18):
irqchip: tegra: do not disable COP IRQ during suspend
pinctrl: tegra: add suspend and resume support
clk: tegra: save and restore divider rate
clk: tegra: pllout: save and restore pllout context
clk: tegra: pll: save and restore pll context
clk: tegra: save and restore CPU and System clocks context
clk: tegra: support for saving and restoring OSC context
clk: tegra: add suspend resume support for DFLL
clk: tegra: add save and restore context support for peripheral clocks
clk: tegra210: use fence_udelay during PLLU init
clk: tegra210: support for Tegra210 clocks suspend and resume
soc/tegra: pmc: allow support for more tegra wake
soc/tegra: pmc: add pmc wake support for tegra210
arm64: tegra: enable wake from deep sleep on RTC alarm.
soc/tegra: pmc: configure core power request polarity
soc/tegra: pmc: configure deep sleep control settings
arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings
arm64: dts: tegra210-p2180: Jetson nano SC7 timings
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 7 +
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +-
drivers/clk/tegra/clk-dfll.c | 78 ++++++++++++
drivers/clk/tegra/clk-dfll.h | 2 +
drivers/clk/tegra/clk-divider.c | 23 ++++
drivers/clk/tegra/clk-periph-fixed.c | 31 +++++
drivers/clk/tegra/clk-periph-gate.c | 34 +++++
drivers/clk/tegra/clk-periph.c | 43 +++++++
drivers/clk/tegra/clk-pll-out.c | 28 ++++
drivers/clk/tegra/clk-pll.c | 121 +++++++++++++-----
drivers/clk/tegra/clk-sdmmc-mux.c | 30 +++++
drivers/clk/tegra/clk-tegra-fixed.c | 14 ++
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 -
drivers/clk/tegra/clk-tegra210.c | 128 +++++++++++++++++--
drivers/clk/tegra/clk.c | 94 ++++++++++++++
drivers/clk/tegra/clk.h | 45 ++++++-
drivers/irqchip/irq-tegra.c | 20 ++-
drivers/pinctrl/tegra/pinctrl-tegra.c | 52 ++++++++
drivers/pinctrl/tegra/pinctrl-tegra.h | 3 +
drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 +
drivers/soc/tegra/pmc.c | 141 ++++++++++++++++++++-
22 files changed, 858 insertions(+), 53 deletions(-)
--
2.7.4
This patch updates device tree for RTC and PMC to allow system wake
from deep sleep on RTC alarm.
Signed-off-by: Sowjanya Komatineni <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 659753118e96..30a7c48385a2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -768,7 +768,8 @@
rtc@7000e000 {
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pmc>;
clocks = <&tegra_car TEGRA210_CLK_RTC>;
clock-names = "rtc";
};
@@ -778,6 +779,8 @@
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #interrupt-cells = <2>;
+ interrupt-controller;
powergates {
pd_audio: aud {
--
2.7.4
This patch implements save and restore context for peripheral fixed
clock ops, peripheral gate clock ops, sdmmc mux clock ops, and
peripheral clock ops.
During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.
So during suspend entry clock and reset state of peripherals is saved
and on resume they are restored to have clocks back to same rate and
state as before suspend.
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
---
drivers/clk/tegra/clk-periph-fixed.c | 31 ++++++++++++++++++++++++++
drivers/clk/tegra/clk-periph-gate.c | 34 ++++++++++++++++++++++++++++
drivers/clk/tegra/clk-periph.c | 43 ++++++++++++++++++++++++++++++++++++
drivers/clk/tegra/clk-sdmmc-mux.c | 30 +++++++++++++++++++++++++
drivers/clk/tegra/clk.h | 8 +++++++
5 files changed, 146 insertions(+)
diff --git a/drivers/clk/tegra/clk-periph-fixed.c b/drivers/clk/tegra/clk-periph-fixed.c
index c088e7a280df..981f68b0a937 100644
--- a/drivers/clk/tegra/clk-periph-fixed.c
+++ b/drivers/clk/tegra/clk-periph-fixed.c
@@ -60,11 +60,42 @@ tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw,
return (unsigned long)rate;
}
+static int tegra_clk_periph_fixed_save_context(struct clk_hw *hw)
+{
+ struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
+ u32 mask = 1 << (fixed->num % 32);
+
+ fixed->enb_ctx = readl(fixed->base + fixed->regs->enb_reg) & mask;
+ fixed->rst_ctx = readl(fixed->base + fixed->regs->rst_reg) & mask;
+
+ return 0;
+}
+
+static void tegra_clk_periph_fixed_restore_context(struct clk_hw *hw)
+{
+ struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
+ u32 mask = 1 << (fixed->num % 32);
+
+ if (fixed->enb_ctx)
+ tegra_clk_periph_fixed_enable(hw);
+ else
+ tegra_clk_periph_fixed_disable(hw);
+
+ udelay(2);
+
+ if (!fixed->rst_ctx) {
+ udelay(5); /* reset propogation delay */
+ writel(mask, fixed->base + fixed->regs->rst_reg);
+ }
+}
+
static const struct clk_ops tegra_clk_periph_fixed_ops = {
.is_enabled = tegra_clk_periph_fixed_is_enabled,
.enable = tegra_clk_periph_fixed_enable,
.disable = tegra_clk_periph_fixed_disable,
.recalc_rate = tegra_clk_periph_fixed_recalc_rate,
+ .save_context = tegra_clk_periph_fixed_save_context,
+ .restore_context = tegra_clk_periph_fixed_restore_context,
};
struct clk *tegra_clk_register_periph_fixed(const char *name,
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 4b31beefc9fc..6ba5b08e0787 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -25,6 +25,8 @@ static DEFINE_SPINLOCK(periph_ref_lock);
#define read_rst(gate) \
readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
+#define write_rst_set(val, gate) \
+ writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
#define write_rst_clr(val, gate) \
writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
@@ -110,10 +112,42 @@ static void clk_periph_disable(struct clk_hw *hw)
spin_unlock_irqrestore(&periph_ref_lock, flags);
}
+static int clk_periph_gate_save_context(struct clk_hw *hw)
+{
+ struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
+
+ gate->clk_state_ctx = read_enb(gate) & periph_clk_to_bit(gate);
+ gate->rst_state_ctx = read_rst(gate) & periph_clk_to_bit(gate);
+
+ return 0;
+}
+
+static void clk_periph_gate_restore_context(struct clk_hw *hw)
+{
+ struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
+
+ if (gate->clk_state_ctx)
+ write_enb_set(periph_clk_to_bit(gate), gate);
+ else
+ write_enb_clr(periph_clk_to_bit(gate), gate);
+
+ udelay(5);
+
+ if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
+ !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
+ if (gate->rst_state_ctx)
+ write_rst_set(periph_clk_to_bit(gate), gate);
+ else
+ write_rst_clr(periph_clk_to_bit(gate), gate);
+ }
+}
+
const struct clk_ops tegra_clk_periph_gate_ops = {
.is_enabled = clk_periph_is_enabled,
.enable = clk_periph_enable,
.disable = clk_periph_disable,
+ .save_context = clk_periph_gate_save_context,
+ .restore_context = clk_periph_gate_restore_context,
};
struct clk *tegra_clk_register_periph_gate(const char *name,
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 58437da25156..d07882656e66 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -5,6 +5,7 @@
#include <linux/clk-provider.h>
#include <linux/export.h>
+#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
@@ -99,6 +100,42 @@ static void clk_periph_disable(struct clk_hw *hw)
gate_ops->disable(gate_hw);
}
+static int clk_periph_save_context(struct clk_hw *hw)
+{
+ struct tegra_clk_periph *periph = to_clk_periph(hw);
+ const struct clk_ops *gate_ops = periph->gate_ops;
+ struct clk_hw *gate_hw = &periph->gate.hw;
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE))
+ gate_ops->save_context(gate_hw);
+
+ if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV))
+ periph->rate_ctx = clk_periph_recalc_rate(hw, parent_rate);
+
+ periph->parent_ctx = clk_periph_get_parent(hw);
+
+ return 0;
+}
+
+static void clk_periph_restore_context(struct clk_hw *hw)
+{
+ struct tegra_clk_periph *periph = to_clk_periph(hw);
+ const struct clk_ops *gate_ops = periph->gate_ops;
+ struct clk_hw *gate_hw = &periph->gate.hw;
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE))
+ gate_ops->restore_context(gate_hw);
+
+ clk_periph_set_parent(hw, periph->parent_ctx);
+
+ if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV))
+ clk_periph_set_rate(hw, periph->rate_ctx, parent_rate);
+}
+
const struct clk_ops tegra_clk_periph_ops = {
.get_parent = clk_periph_get_parent,
.set_parent = clk_periph_set_parent,
@@ -108,6 +145,8 @@ const struct clk_ops tegra_clk_periph_ops = {
.is_enabled = clk_periph_is_enabled,
.enable = clk_periph_enable,
.disable = clk_periph_disable,
+ .save_context = clk_periph_save_context,
+ .restore_context = clk_periph_restore_context,
};
static const struct clk_ops tegra_clk_periph_nodiv_ops = {
@@ -116,6 +155,8 @@ static const struct clk_ops tegra_clk_periph_nodiv_ops = {
.is_enabled = clk_periph_is_enabled,
.enable = clk_periph_enable,
.disable = clk_periph_disable,
+ .save_context = clk_periph_save_context,
+ .restore_context = clk_periph_restore_context,
};
static const struct clk_ops tegra_clk_periph_no_gate_ops = {
@@ -124,6 +165,8 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = {
.recalc_rate = clk_periph_recalc_rate,
.round_rate = clk_periph_round_rate,
.set_rate = clk_periph_set_rate,
+ .save_context = clk_periph_save_context,
+ .restore_context = clk_periph_restore_context,
};
static struct clk *_tegra_clk_register_periph(const char *name,
diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c
index a5cd3e31dbae..fffe08e02c10 100644
--- a/drivers/clk/tegra/clk-sdmmc-mux.c
+++ b/drivers/clk/tegra/clk-sdmmc-mux.c
@@ -194,6 +194,34 @@ static void clk_sdmmc_mux_disable(struct clk_hw *hw)
gate_ops->disable(gate_hw);
}
+static int clk_sdmmc_mux_save_context(struct clk_hw *hw)
+{
+ struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+ const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
+ struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ sdmmc_mux->rate_ctx = clk_sdmmc_mux_recalc_rate(hw, parent_rate);
+ sdmmc_mux->parent_ctx = clk_sdmmc_mux_get_parent(hw);
+ gate_ops->save_context(gate_hw);
+
+ return 0;
+}
+
+static void clk_sdmmc_mux_restore_context(struct clk_hw *hw)
+{
+ struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
+ const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
+ struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ clk_sdmmc_mux_set_parent(hw, sdmmc_mux->parent_ctx);
+ clk_sdmmc_mux_set_rate(hw, sdmmc_mux->rate_ctx, parent_rate);
+ gate_ops->restore_context(gate_hw);
+}
+
static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
.get_parent = clk_sdmmc_mux_get_parent,
.set_parent = clk_sdmmc_mux_set_parent,
@@ -203,6 +231,8 @@ static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
.is_enabled = clk_sdmmc_mux_is_enabled,
.enable = clk_sdmmc_mux_enable,
.disable = clk_sdmmc_mux_disable,
+ .save_context = clk_sdmmc_mux_save_context,
+ .restore_context = clk_sdmmc_mux_restore_context,
};
struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index a687ed6127b6..13e16359ebbe 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -533,6 +533,8 @@ struct tegra_clk_periph_gate {
int clk_num;
int *enable_refcnt;
const struct tegra_clk_periph_regs *regs;
+ bool clk_state_ctx;
+ bool rst_state_ctx;
};
#define to_clk_periph_gate(_hw) \
@@ -559,6 +561,8 @@ struct tegra_clk_periph_fixed {
unsigned int mul;
unsigned int div;
unsigned int num;
+ bool enb_ctx;
+ bool rst_ctx;
};
struct clk *tegra_clk_register_periph_fixed(const char *name,
@@ -591,6 +595,8 @@ struct tegra_clk_periph {
const struct clk_ops *mux_ops;
const struct clk_ops *div_ops;
const struct clk_ops *gate_ops;
+ unsigned long rate_ctx;
+ u8 parent_ctx;
};
#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
@@ -742,6 +748,8 @@ struct tegra_sdmmc_mux {
const struct clk_ops *gate_ops;
struct tegra_clk_periph_gate gate;
u8 div_flags;
+ unsigned long rate_ctx;
+ u8 parent_ctx;
};
#define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
--
2.7.4
This patch implements save and restore of PLL context.
During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.
So during suspend entry pll rate is stored and on resume it is
restored back along with its state.
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
---
drivers/clk/tegra/clk-pll.c | 121 ++++++++++++++++++++++++++++-----------
drivers/clk/tegra/clk-tegra210.c | 2 +-
drivers/clk/tegra/clk.h | 10 +++-
3 files changed, 99 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 1583f5fc992f..3686ada022aa 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1008,6 +1008,59 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
return rate;
}
+void tegra_clk_sync_state_pll(struct clk_hw *hw)
+{
+ if (!__clk_get_enable_count(hw->clk))
+ clk_pll_disable(hw);
+ else
+ clk_pll_enable(hw);
+}
+
+static int tegra_clk_pll_save_context(struct clk_hw *hw)
+{
+ struct tegra_clk_pll *pll = to_clk_pll(hw);
+ u32 val = 0;
+
+ pll->rate = clk_hw_get_rate(hw);
+
+ if (pll->params->flags & TEGRA_PLLMB)
+ val = pll_readl_base(pll);
+ else if (pll->params->flags & TEGRA_PLLRE)
+ val = pll_readl_base(pll) & divp_mask_shifted(pll);
+
+ pll->pllbase_ctx = val;
+
+ return 0;
+}
+
+static void tegra_clk_pll_restore_context(struct clk_hw *hw)
+{
+ struct tegra_clk_pll *pll = to_clk_pll(hw);
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+ u32 val;
+
+ if (clk_pll_is_enabled(hw))
+ return;
+
+ if (pll->params->flags & TEGRA_PLLMB) {
+ pll_writel_base(pll->pllbase_ctx, pll);
+ } else if (pll->params->flags & TEGRA_PLLRE) {
+ val = pll_readl_base(pll);
+ val &= ~(divp_mask_shifted(pll));
+ pll_writel_base(pll->pllbase_ctx | val, pll);
+ }
+
+ if (pll->params->set_defaults)
+ pll->params->set_defaults(pll);
+
+ clk_pll_set_rate(hw, pll->rate, parent_rate);
+
+ /* do not sync pllx state here. pllx is sync'd after dfll resume */
+ if (!(pll->params->flags & TEGRA_PLLX))
+ tegra_clk_sync_state_pll(hw);
+}
+
const struct clk_ops tegra_clk_pll_ops = {
.is_enabled = clk_pll_is_enabled,
.enable = clk_pll_enable,
@@ -1015,6 +1068,8 @@ const struct clk_ops tegra_clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.round_rate = clk_pll_round_rate,
.set_rate = clk_pll_set_rate,
+ .save_context = tegra_clk_pll_save_context,
+ .restore_context = tegra_clk_pll_restore_context,
};
const struct clk_ops tegra_clk_plle_ops = {
@@ -1802,6 +1857,27 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw)
return ret;
}
+
+static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
+{
+ u32 val, val_aux;
+
+ /* ensure parent is set to pll_ref */
+ val = pll_readl_base(pll);
+ val_aux = pll_readl(pll->params->aux_reg, pll);
+
+ if (val & PLL_BASE_ENABLE) {
+ if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
+ (val_aux & PLLE_AUX_PLLP_SEL))
+ WARN(1, "pll_e enabled with unsupported parent %s\n",
+ (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
+ "pll_re_vco");
+ } else {
+ val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
+ pll_writel(val_aux, pll->params->aux_reg, pll);
+ fence_udelay(1, pll->clk_base);
+ }
+}
#endif
static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
@@ -2214,27 +2290,12 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
{
struct tegra_clk_pll *pll;
struct clk *clk;
- u32 val, val_aux;
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
if (IS_ERR(pll))
return ERR_CAST(pll);
- /* ensure parent is set to pll_re_vco */
-
- val = pll_readl_base(pll);
- val_aux = pll_readl(pll_params->aux_reg, pll);
-
- if (val & PLL_BASE_ENABLE) {
- if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
- (val_aux & PLLE_AUX_PLLP_SEL))
- WARN(1, "pll_e enabled with unsupported parent %s\n",
- (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
- "pll_re_vco");
- } else {
- val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
- pll_writel(val_aux, pll_params->aux_reg, pll);
- }
+ _clk_plle_tegra_init_parent(pll);
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
&tegra_clk_plle_tegra114_ops);
@@ -2276,6 +2337,8 @@ static const struct clk_ops tegra_clk_pllss_ops = {
.recalc_rate = clk_pll_recalc_rate,
.round_rate = clk_pll_ramp_round_rate,
.set_rate = clk_pllxc_set_rate,
+ .save_context = tegra_clk_pll_save_context,
+ .restore_context = tegra_clk_pll_restore_context,
};
struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
@@ -2375,6 +2438,7 @@ struct clk *tegra_clk_register_pllre_tegra210(const char *name,
pll_params->vco_min = pll_params->adjust_vco(pll_params,
parent_rate);
+ pll_params->flags |= TEGRA_PLLRE;
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
if (IS_ERR(pll))
return ERR_CAST(pll);
@@ -2520,11 +2584,19 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw)
spin_unlock_irqrestore(pll->lock, flags);
}
+static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)
+{
+ struct tegra_clk_pll *pll = to_clk_pll(hw);
+
+ _clk_plle_tegra_init_parent(pll);
+}
+
static const struct clk_ops tegra_clk_plle_tegra210_ops = {
.is_enabled = clk_plle_tegra210_is_enabled,
.enable = clk_plle_tegra210_enable,
.disable = clk_plle_tegra210_disable,
.recalc_rate = clk_pll_recalc_rate,
+ .restore_context = tegra_clk_plle_t210_restore_context,
};
struct clk *tegra_clk_register_plle_tegra210(const char *name,
@@ -2535,27 +2607,12 @@ struct clk *tegra_clk_register_plle_tegra210(const char *name,
{
struct tegra_clk_pll *pll;
struct clk *clk;
- u32 val, val_aux;
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
if (IS_ERR(pll))
return ERR_CAST(pll);
- /* ensure parent is set to pll_re_vco */
-
- val = pll_readl_base(pll);
- val_aux = pll_readl(pll_params->aux_reg, pll);
-
- if (val & PLLE_BASE_ENABLE) {
- if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
- (val_aux & PLLE_AUX_PLLP_SEL))
- WARN(1, "pll_e enabled with unsupported parent %s\n",
- (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
- "pll_re_vco");
- } else {
- val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
- pll_writel(val_aux, pll_params->aux_reg, pll);
- }
+ _clk_plle_tegra_init_parent(pll);
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
&tegra_clk_plle_tegra210_ops);
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index cbd77658dcf7..7f90442462af 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -1597,7 +1597,7 @@ static struct tegra_clk_pll_params pll_x_params = {
.pdiv_tohw = pll_qlin_pdiv_to_hw,
.div_nmp = &pllx_nmp,
.freq_table = pll_x_freq_table,
- .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
+ .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLLX,
.dyn_ramp = tegra210_pllx_dyn_ramp,
.set_defaults = tegra210_pllx_set_defaults,
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index fb29a8c27873..8532f5150091 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -235,6 +235,8 @@ struct tegra_clk_pll;
* TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
* flag indicated that it is PLLMB.
* TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
+ * TEGRA_PLLRE - Used to indicate that it is PLLRE.
+ * TEGRA_PLLX - Used to indicate that it is PLLX.
*/
struct tegra_clk_pll_params {
unsigned long input_min;
@@ -301,6 +303,8 @@ struct tegra_clk_pll_params {
#define TEGRA_MDIV_NEW BIT(11)
#define TEGRA_PLLMB BIT(12)
#define TEGRA_PLL_VCO_OUT BIT(13)
+#define TEGRA_PLLRE BIT(14)
+#define TEGRA_PLLX BIT(15)
/**
* struct tegra_clk_pll - Tegra PLL clock
@@ -310,6 +314,8 @@ struct tegra_clk_pll_params {
* @pmc: address of PMC, required to read override bits
* @lock: register lock
* @params: PLL parameters
+ * @rate: rate during system suspend and resume
+ * @pllbase_ctx: pll base register value during suspend and resume
*/
struct tegra_clk_pll {
struct clk_hw hw;
@@ -317,6 +323,8 @@ struct tegra_clk_pll {
void __iomem *pmc;
spinlock_t *lock;
struct tegra_clk_pll_params *params;
+ unsigned long rate;
+ u32 pllbase_ctx;
};
#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
@@ -840,7 +848,7 @@ u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
u8 frac_width, u8 flags);
-
+void tegra_clk_sync_state_pll(struct clk_hw *hw);
/* Combined read fence with delay */
#define fence_udelay(delay, reg) \
--
2.7.4
This patch uses fence_udelay rather than udelay during PLLU
initialization to ensure writes to clock registers happens before
waiting for specified delay.
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
---
drivers/clk/tegra/clk-tegra210.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 7f90442462af..1c08c53482a5 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2836,7 +2836,7 @@ static int tegra210_enable_pllu(void)
reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
reg &= ~BIT(pllu.params->iddq_bit_idx);
writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
- udelay(5);
+ fence_udelay(5, clk_base);
reg = readl_relaxed(clk_base + PLLU_BASE);
reg &= ~GENMASK(20, 0);
@@ -2844,7 +2844,7 @@ static int tegra210_enable_pllu(void)
reg |= fentry->n << 8;
reg |= fentry->p << 16;
writel(reg, clk_base + PLLU_BASE);
- udelay(1);
+ fence_udelay(1, clk_base);
reg |= PLL_ENABLE;
writel(reg, clk_base + PLLU_BASE);
@@ -2890,12 +2890,12 @@ static int tegra210_init_pllu(void)
reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
- udelay(1);
+ fence_udelay(1, clk_base);
reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
- udelay(1);
+ fence_udelay(1, clk_base);
reg = readl_relaxed(clk_base + PLLU_BASE);
reg &= ~PLLU_BASE_CLKENABLE_USB;
--
2.7.4
During system suspend state, core power goes off and looses all the
CAR controller register settings.
This patch creates APIs for saving and restoring the context of Tegra
CPUG, CPULP and SCLK.
CPU and System clock context includes
- CPUG, CPULP, and SCLK burst policy settings for clock sourcea of all
their normal states.
- SCLK divisor and System clock rate for restoring SCLK, AHB and APB
rates on resume.
- OSC_DIV settings which are used as reference clock input to some PLLs.
- SPARE_REG and CLK_MASK settings.
These APIs are used in Tegra210 clock driver during suspend and resume
operation.
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
---
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 --
drivers/clk/tegra/clk.c | 80 ++++++++++++++++++++++++++++++++
drivers/clk/tegra/clk.h | 14 ++++++
3 files changed, 94 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
index cdfe7c9697e1..ed69ec4d883e 100644
--- a/drivers/clk/tegra/clk-tegra-super-gen4.c
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -19,10 +19,6 @@
#define PLLX_MISC2 0x514
#define PLLX_MISC3 0x518
-#define CCLKG_BURST_POLICY 0x368
-#define CCLKLP_BURST_POLICY 0x370
-#define SCLK_BURST_POLICY 0x028
-#define SYSTEM_CLK_RATE 0x030
#define SCLK_DIVIDER 0x2c
static DEFINE_SPINLOCK(sysrate_lock);
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 573e3c967ae1..9e863362d2bf 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -70,6 +70,12 @@ static struct clk **clks;
static int clk_num;
static struct clk_onecell_data clk_data;
+static u32 cclkg_burst_policy_ctx[2];
+static u32 cclklp_burst_policy_ctx[2];
+static u32 sclk_burst_policy_ctx[2];
+static u32 sys_clk_divisor_ctx, system_rate_ctx;
+static u32 spare_ctx, misc_clk_enb_ctx, clk_arm_ctx;
+
/* Handlers for SoC-specific reset lines */
static int (*special_reset_assert)(unsigned long);
static int (*special_reset_deassert)(unsigned long);
@@ -199,6 +205,80 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
}
}
+void tegra_cclkg_burst_policy_save_context(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < BURST_POLICY_REG_SIZE; i++)
+ cclkg_burst_policy_ctx[i] = readl_relaxed(clk_base +
+ CCLKG_BURST_POLICY +
+ (i * 4));
+}
+
+void tegra_cclkg_burst_policy_restore_context(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < BURST_POLICY_REG_SIZE; i++)
+ writel_relaxed(cclkg_burst_policy_ctx[i],
+ clk_base + CCLKG_BURST_POLICY + (i * 4));
+
+ fence_udelay(2, clk_base);
+}
+
+void tegra_sclk_cclklp_burst_policy_save_context(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < BURST_POLICY_REG_SIZE; i++) {
+ cclklp_burst_policy_ctx[i] = readl_relaxed(clk_base +
+ CCLKLP_BURST_POLICY +
+ (i * 4));
+
+ sclk_burst_policy_ctx[i] = readl_relaxed(clk_base +
+ SCLK_BURST_POLICY +
+ (i * 4));
+ }
+
+ sys_clk_divisor_ctx = readl_relaxed(clk_base + SYS_CLK_DIV);
+ system_rate_ctx = readl_relaxed(clk_base + SYSTEM_CLK_RATE);
+ spare_ctx = readl_relaxed(clk_base + SPARE_REG0);
+ misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
+ clk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
+}
+
+void tegra_sclk_cpulp_burst_policy_restore_context(void)
+{
+ unsigned int i;
+ u32 val;
+
+ /*
+ * resume SCLK and CPULP clocks
+ * for SCLk, set safe dividers values first and then restore source
+ * and dividers
+ */
+
+ writel_relaxed(0x1, clk_base + SYSTEM_CLK_RATE);
+ val = readl_relaxed(clk_base + SYS_CLK_DIV);
+ if (val < sys_clk_divisor_ctx)
+ writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV);
+
+ fence_udelay(2, clk_base);
+
+ for (i = 0; i < BURST_POLICY_REG_SIZE; i++) {
+ writel_relaxed(cclklp_burst_policy_ctx[i],
+ clk_base + CCLKLP_BURST_POLICY + (i * 4));
+ writel_relaxed(sclk_burst_policy_ctx[i],
+ clk_base + SCLK_BURST_POLICY + (i * 4));
+ }
+
+ writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV);
+ writel_relaxed(system_rate_ctx, clk_base + SYSTEM_CLK_RATE);
+ writel_relaxed(spare_ctx, clk_base + SPARE_REG0);
+ writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
+ writel_relaxed(clk_arm_ctx, clk_base + CLK_MASK_ARM);
+}
+
struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
{
clk_base = regs;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 8532f5150091..c66b0a73bb01 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -10,6 +10,16 @@
#include <linux/clkdev.h>
#include <linux/delay.h>
+#define SCLK_BURST_POLICY 0x28
+#define SYSTEM_CLK_RATE 0x30
+#define CLK_MASK_ARM 0x44
+#define MISC_CLK_ENB 0x48
+#define CCLKG_BURST_POLICY 0x368
+#define CCLKLP_BURST_POLICY 0x370
+#define SYS_CLK_DIV 0x400
+#define SPARE_REG0 0x55c
+#define BURST_POLICY_REG_SIZE 2
+
/**
* struct tegra_clk_sync_source - external clock source from codec
*
@@ -849,6 +859,10 @@ int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
u8 frac_width, u8 flags);
void tegra_clk_sync_state_pll(struct clk_hw *hw);
+void tegra_cclkg_burst_policy_save_context(void);
+void tegra_cclkg_burst_policy_restore_context(void);
+void tegra_sclk_cclklp_burst_policy_save_context(void);
+void tegra_sclk_cpulp_burst_policy_restore_context(void);
/* Combined read fence with delay */
#define fence_udelay(delay, reg) \
--
2.7.4
This patch implements context save and restore for clock divider.
During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.
So during suspend entry the context of clock divider is saved and
on resume context is restored back for normal operation.
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
---
drivers/clk/tegra/clk-divider.c | 23 +++++++++++++++++++++++
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index e76731fb7d69..ecb7ff9ce97e 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -109,10 +109,33 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
+static int clk_divider_save_context(struct clk_hw *hw)
+{
+ struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ divider->rate = clk_frac_div_recalc_rate(hw, parent_rate);
+
+ return 0;
+}
+
+static void clk_divider_restore_context(struct clk_hw *hw)
+{
+ struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+ unsigned long parent_rate = clk_hw_get_rate(parent);
+
+ if (clk_frac_div_set_rate(hw, divider->rate, parent_rate) < 0)
+ WARN_ON(1);
+}
+
const struct clk_ops tegra_clk_frac_div_ops = {
.recalc_rate = clk_frac_div_recalc_rate,
.set_rate = clk_frac_div_set_rate,
.round_rate = clk_frac_div_round_rate,
+ .save_context = clk_divider_save_context,
+ .restore_context = clk_divider_restore_context,
};
struct clk *tegra_clk_register_divider(const char *name,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 905bf1096558..83623f5f55f3 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -42,6 +42,7 @@ struct clk *tegra_clk_register_sync_source(const char *name,
* @width: width of the divider bit field
* @frac_width: width of the fractional bit field
* @lock: register lock
+ * @rate: rate during suspend and resume
*
* Flags:
* TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
@@ -62,6 +63,7 @@ struct tegra_clk_frac_div {
u8 width;
u8 frac_width;
spinlock_t *lock;
+ unsigned long rate;
};
#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
--
2.7.4
This patch adds support for Tegra pinctrl driver suspend and resume.
During suspend, context of all pinctrl registers are stored and
on resume they are all restored to have all the pinmux and pad
configuration for normal operation.
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
---
drivers/pinctrl/tegra/pinctrl-tegra.c | 52 ++++++++++++++++++++++++++++++++
drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 +
3 files changed, 56 insertions(+)
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 34596b246578..e7c0a1011cba 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -621,6 +621,43 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
}
}
+static int tegra_pinctrl_suspend(struct device *dev)
+{
+ struct tegra_pmx *pmx = dev_get_drvdata(dev);
+ u32 *backup_regs = pmx->backup_regs;
+ u32 *regs;
+ unsigned int i, j;
+
+ for (i = 0; i < pmx->nbanks; i++) {
+ regs = pmx->regs[i];
+ for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
+ *backup_regs++ = readl(regs++);
+ }
+
+ return pinctrl_force_sleep(pmx->pctl);
+}
+
+static int tegra_pinctrl_resume(struct device *dev)
+{
+ struct tegra_pmx *pmx = dev_get_drvdata(dev);
+ u32 *backup_regs = pmx->backup_regs;
+ u32 *regs;
+ unsigned int i, j;
+
+ for (i = 0; i < pmx->nbanks; i++) {
+ regs = pmx->regs[i];
+ for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
+ writel(*backup_regs++, regs++);
+ }
+
+ return 0;
+}
+
+const struct dev_pm_ops tegra_pinctrl_pm = {
+ .suspend = &tegra_pinctrl_suspend,
+ .resume = &tegra_pinctrl_resume
+};
+
static bool gpio_node_has_range(const char *compatible)
{
struct device_node *np;
@@ -645,6 +682,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
int i;
const char **group_pins;
int fn, gn, gfn;
+ unsigned long backup_regs_size = 0;
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx)
@@ -697,6 +735,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res)
break;
+ backup_regs_size += resource_size(res);
}
pmx->nbanks = i;
@@ -705,11 +744,24 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
if (!pmx->regs)
return -ENOMEM;
+ pmx->reg_bank_size = devm_kcalloc(&pdev->dev, pmx->nbanks,
+ sizeof(*pmx->reg_bank_size),
+ GFP_KERNEL);
+ if (!pmx->reg_bank_size)
+ return -ENOMEM;
+
+ pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
+ GFP_KERNEL);
+ if (!pmx->backup_regs)
+ return -ENOMEM;
+
for (i = 0; i < pmx->nbanks; i++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pmx->regs[i]))
return PTR_ERR(pmx->regs[i]);
+
+ pmx->reg_bank_size[i] = resource_size(res);
}
pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index 287702660783..55456f8d44cf 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -17,6 +17,8 @@ struct tegra_pmx {
int nbanks;
void __iomem **regs;
+ size_t *reg_bank_size;
+ u32 *backup_regs;
};
enum tegra_pinconf_param {
@@ -193,6 +195,7 @@ struct tegra_pinctrl_soc_data {
bool drvtype_in_mux;
};
+extern const struct dev_pm_ops tegra_pinctrl_pm;
int tegra_pinctrl_probe(struct platform_device *pdev,
const struct tegra_pinctrl_soc_data *soc_data);
#endif
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c
index 0b56ad5c9c1c..edd3f4606cdb 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra210.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c
@@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = {
.driver = {
.name = "tegra210-pinctrl",
.of_match_table = tegra210_pinctrl_of_match,
+ .pm = &tegra_pinctrl_pm,
},
.probe = tegra210_pinctrl_probe,
};
--
2.7.4
This patch adds support for storing OSC clock frequency and the
drive-strength during OSC clock init and creates an API to restore
OSC control register value from the saved context.
This API is invoked by Tegra210 clock driver during system resume
to restore the OSC clock settings.
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
---
drivers/clk/tegra/clk-tegra-fixed.c | 14 ++++++++++++++
drivers/clk/tegra/clk.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
index 8d91b2b191cf..e8df0ccbffd0 100644
--- a/drivers/clk/tegra/clk-tegra-fixed.c
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -17,7 +17,10 @@
#define OSC_CTRL 0x50
#define OSC_CTRL_OSC_FREQ_SHIFT 28
#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
+#define OSC_CTRL_MASK (0x3f2 | \
+ (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
+static u32 osc_ctrl_ctx;
int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
unsigned long *input_freqs, unsigned int num,
unsigned int clk_m_div, unsigned long *osc_freq,
@@ -29,6 +32,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
unsigned osc_idx;
val = readl_relaxed(clk_base + OSC_CTRL);
+ osc_ctrl_ctx = val & OSC_CTRL_MASK;
osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
if (osc_idx < num)
@@ -96,3 +100,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
*dt_clk = clk;
}
}
+
+void tegra_clk_osc_resume(void __iomem *clk_base)
+{
+ u32 val;
+
+ val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
+ val |= osc_ctrl_ctx;
+ writel_relaxed(val, clk_base + OSC_CTRL);
+ fence_udelay(2, clk_base);
+}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index c66b0a73bb01..a687ed6127b6 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -863,6 +863,7 @@ void tegra_cclkg_burst_policy_save_context(void);
void tegra_cclkg_burst_policy_restore_context(void);
void tegra_sclk_cclklp_burst_policy_save_context(void);
void tegra_sclk_cpulp_burst_policy_restore_context(void);
+void tegra_clk_osc_resume(void __iomem *clk_base);
/* Combined read fence with delay */
#define fence_udelay(delay, reg) \
--
2.7.4
28.06.2019 5:12, Sowjanya Komatineni пишет:
> This patch adds support for Tegra pinctrl driver suspend and resume.
>
> During suspend, context of all pinctrl registers are stored and
> on resume they are all restored to have all the pinmux and pad
> configuration for normal operation.
>
> Acked-by: Thierry Reding <[email protected]>
> Signed-off-by: Sowjanya Komatineni <[email protected]>
> ---
> drivers/pinctrl/tegra/pinctrl-tegra.c | 52 ++++++++++++++++++++++++++++++++
> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
> drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 +
> 3 files changed, 56 insertions(+)
>
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
> index 34596b246578..e7c0a1011cba 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -621,6 +621,43 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
> }
> }
>
> +static int tegra_pinctrl_suspend(struct device *dev)
> +{
> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
> + u32 *backup_regs = pmx->backup_regs;
> + u32 *regs;
> + unsigned int i, j;
In general it's better not to use "j" in conjunction with "i" because they look
similar and I seen quite a lot of bugs caused by unnoticed typos like that. So I'm
suggesting to use "i, k" for clarity.
> +
> + for (i = 0; i < pmx->nbanks; i++) {
> + regs = pmx->regs[i];
> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
> + *backup_regs++ = readl(regs++);
Please use readl_relaxed(), we don't need memory barriers here.
> + }
> +
> + return pinctrl_force_sleep(pmx->pctl);
> +}
> +
> +static int tegra_pinctrl_resume(struct device *dev)
> +{
> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
> + u32 *backup_regs = pmx->backup_regs;
> + u32 *regs;
> + unsigned int i, j;
> +
> + for (i = 0; i < pmx->nbanks; i++) {
> + regs = pmx->regs[i];> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
> + writel(*backup_regs++, regs++);
Same for writel_relaxed(), memory barrier is inserted *before* the write to ensure
that all previous memory stores are completed. IOREMAP'ed memory is strongly-ordered,
memory barriers are not needed here.
> + }
> +
> + return 0;
> +}
> +
> +const struct dev_pm_ops tegra_pinctrl_pm = {
> + .suspend = &tegra_pinctrl_suspend,
> + .resume = &tegra_pinctrl_resume
> +};
> +
> static bool gpio_node_has_range(const char *compatible)
> {
> struct device_node *np;
> @@ -645,6 +682,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
> int i;
> const char **group_pins;
> int fn, gn, gfn;
> + unsigned long backup_regs_size = 0;
>
> pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
> if (!pmx)
> @@ -697,6 +735,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
> res = platform_get_resource(pdev, IORESOURCE_MEM, i);
> if (!res)
> break;
> + backup_regs_size += resource_size(res);
> }
> pmx->nbanks = i;
>
> @@ -705,11 +744,24 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
> if (!pmx->regs)
> return -ENOMEM;
>
> + pmx->reg_bank_size = devm_kcalloc(&pdev->dev, pmx->nbanks,
> + sizeof(*pmx->reg_bank_size),
> + GFP_KERNEL);
> + if (!pmx->reg_bank_size)
> + return -ENOMEM;
It looks to me that we don't really need to churn with this allocation because the
bank sizes are already a part of the platform driver's description.
We could add a simple helper function that retrieves the bank sizes, like this:
static unsigned int tegra_pinctrl_bank_size(struct device *dev,
unsigned int bank_id)
{
struct platform_device *pdev;
struct resource *res;
pdev = to_platform_device(dev);
res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
return resource_size(res) / 4;
}
> + pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
> + GFP_KERNEL);
> + if (!pmx->backup_regs)
> + return -ENOMEM;
> +
> for (i = 0; i < pmx->nbanks; i++) {
> res = platform_get_resource(pdev, IORESOURCE_MEM, i);
> pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(pmx->regs[i]))
> return PTR_ERR(pmx->regs[i]);
> +
> + pmx->reg_bank_size[i] = resource_size(res);
> }
>
> pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
> index 287702660783..55456f8d44cf 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.h
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
> @@ -17,6 +17,8 @@ struct tegra_pmx {
>
> int nbanks;
> void __iomem **regs;
> + size_t *reg_bank_size;
> + u32 *backup_regs;
> };
>
> enum tegra_pinconf_param {
> @@ -193,6 +195,7 @@ struct tegra_pinctrl_soc_data {
> bool drvtype_in_mux;
> };
>
> +extern const struct dev_pm_ops tegra_pinctrl_pm;
Please add a newline here.
> int tegra_pinctrl_probe(struct platform_device *pdev,
> const struct tegra_pinctrl_soc_data *soc_data);
> #endif
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c
> index 0b56ad5c9c1c..edd3f4606cdb 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c
> @@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = {
> .driver = {
> .name = "tegra210-pinctrl",
> .of_match_table = tegra210_pinctrl_of_match,
> + .pm = &tegra_pinctrl_pm,
> },
> .probe = tegra210_pinctrl_probe,
> };
>
Could you please address my comments in the next revision if there will be one?
28.06.2019 14:56, Dmitry Osipenko пишет:
> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>
>> During suspend, context of all pinctrl registers are stored and
>> on resume they are all restored to have all the pinmux and pad
>> configuration for normal operation.
>>
>> Acked-by: Thierry Reding <[email protected]>
>> Signed-off-by: Sowjanya Komatineni <[email protected]>
>> ---
>> int tegra_pinctrl_probe(struct platform_device *pdev,
>> const struct tegra_pinctrl_soc_data *soc_data);
>> #endif
>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c
>> index 0b56ad5c9c1c..edd3f4606cdb 100644
>> --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c
>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c
>> @@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = {
>> .driver = {
>> .name = "tegra210-pinctrl",
>> .of_match_table = tegra210_pinctrl_of_match,
>> + .pm = &tegra_pinctrl_pm,
>> },
>> .probe = tegra210_pinctrl_probe,
>> };
>>
>
> Could you please address my comments in the next revision if there will be one?
>
Also, what about adding ".pm' for other Tegras? I'm sure Jon could test them for you.
On 6/28/19 5:05 AM, Dmitry Osipenko wrote:
> 28.06.2019 14:56, Dmitry Osipenko пишет:
>> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>>
>>> During suspend, context of all pinctrl registers are stored and
>>> on resume they are all restored to have all the pinmux and pad
>>> configuration for normal operation.
>>>
>>> Acked-by: Thierry Reding <[email protected]>
>>> Signed-off-by: Sowjanya Komatineni <[email protected]>
>>> ---
>>> int tegra_pinctrl_probe(struct platform_device *pdev,
>>> const struct tegra_pinctrl_soc_data *soc_data);
>>> #endif
>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>> index 0b56ad5c9c1c..edd3f4606cdb 100644
>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>> @@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = {
>>> .driver = {
>>> .name = "tegra210-pinctrl",
>>> .of_match_table = tegra210_pinctrl_of_match,
>>> + .pm = &tegra_pinctrl_pm,
>>> },
>>> .probe = tegra210_pinctrl_probe,
>>> };
>>>
>> Could you please address my comments in the next revision if there will be one?
>>
> Also, what about adding ".pm' for other Tegras? I'm sure Jon could test them for you.
This series is for Tegra210 SC7 entry/exit along with clocks and pinctrl
suspend resume needed for Tegra210 basic sc7 entry and exit.
This includes pinctrl, pmc changes, clock-tegra210 driver changes all
w.r.t Tegra210 platforms specific.
Suspend/resume support for other Tegras will be in separate patch series.
thanks
Sowjanya
29.06.2019 2:00, Sowjanya Komatineni пишет:
>
> On 6/28/19 5:05 AM, Dmitry Osipenko wrote:
>> 28.06.2019 14:56, Dmitry Osipenko пишет:
>>> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>>>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>>>
>>>> During suspend, context of all pinctrl registers are stored and
>>>> on resume they are all restored to have all the pinmux and pad
>>>> configuration for normal operation.
>>>>
>>>> Acked-by: Thierry Reding <[email protected]>
>>>> Signed-off-by: Sowjanya Komatineni <[email protected]>
>>>> ---
>>>> int tegra_pinctrl_probe(struct platform_device *pdev,
>>>> const struct tegra_pinctrl_soc_data *soc_data);
>>>> #endif
>>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>>> b/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>>> index 0b56ad5c9c1c..edd3f4606cdb 100644
>>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>>> @@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = {
>>>> .driver = {
>>>> .name = "tegra210-pinctrl",
>>>> .of_match_table = tegra210_pinctrl_of_match,
>>>> + .pm = &tegra_pinctrl_pm,
>>>> },
>>>> .probe = tegra210_pinctrl_probe,
>>>> };
>>>>
>>> Could you please address my comments in the next revision if there will be one?
>>>
>> Also, what about adding ".pm' for other Tegras? I'm sure Jon could test them for you.
>
> This series is for Tegra210 SC7 entry/exit along with clocks and pinctrl suspend
> resume needed for Tegra210 basic sc7 entry and exit.
>
> This includes pinctrl, pmc changes, clock-tegra210 driver changes all w.r.t Tegra210
> platforms specific.
>
> Suspend/resume support for other Tegras will be in separate patch series.
Okay, fair enough.
28.06.2019 5:12, Sowjanya Komatineni пишет:
> This patch implements save and restore context for peripheral fixed
> clock ops, peripheral gate clock ops, sdmmc mux clock ops, and
> peripheral clock ops.
>
> During system suspend, core power goes off and looses the settings
> of the Tegra CAR controller registers.
>
> So during suspend entry clock and reset state of peripherals is saved
> and on resume they are restored to have clocks back to same rate and
> state as before suspend.
>
> Acked-by: Thierry Reding <[email protected]>
> Signed-off-by: Sowjanya Komatineni <[email protected]>
> ---
> drivers/clk/tegra/clk-periph-fixed.c | 31 ++++++++++++++++++++++++++
> drivers/clk/tegra/clk-periph-gate.c | 34 ++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-periph.c | 43 ++++++++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-sdmmc-mux.c | 30 +++++++++++++++++++++++++
> drivers/clk/tegra/clk.h | 8 +++++++
> 5 files changed, 146 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-periph-fixed.c b/drivers/clk/tegra/clk-periph-fixed.c
> index c088e7a280df..981f68b0a937 100644
> --- a/drivers/clk/tegra/clk-periph-fixed.c
> +++ b/drivers/clk/tegra/clk-periph-fixed.c
> @@ -60,11 +60,42 @@ tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw,
> return (unsigned long)rate;
> }
>
> +static int tegra_clk_periph_fixed_save_context(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
> + u32 mask = 1 << (fixed->num % 32);
> +
> + fixed->enb_ctx = readl(fixed->base + fixed->regs->enb_reg) & mask;
> + fixed->rst_ctx = readl(fixed->base + fixed->regs->rst_reg) & mask;
> +
readl_relaxed() ?
28.06.2019 5:12, Sowjanya Komatineni пишет:
> During system suspend state, core power goes off and looses all the
> CAR controller register settings.
>
> This patch creates APIs for saving and restoring the context of Tegra
> CPUG, CPULP and SCLK.
>
> CPU and System clock context includes
> - CPUG, CPULP, and SCLK burst policy settings for clock sourcea of all
> their normal states.
> - SCLK divisor and System clock rate for restoring SCLK, AHB and APB
> rates on resume.
> - OSC_DIV settings which are used as reference clock input to some PLLs.
> - SPARE_REG and CLK_MASK settings.
>
> These APIs are used in Tegra210 clock driver during suspend and resume
> operation.
>
> Acked-by: Thierry Reding <[email protected]>
> Signed-off-by: Sowjanya Komatineni <[email protected]>
> ---
> drivers/clk/tegra/clk-tegra-super-gen4.c | 4 --
> drivers/clk/tegra/clk.c | 80 ++++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk.h | 14 ++++++
> 3 files changed, 94 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
> index cdfe7c9697e1..ed69ec4d883e 100644
> --- a/drivers/clk/tegra/clk-tegra-super-gen4.c
> +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
> @@ -19,10 +19,6 @@
> #define PLLX_MISC2 0x514
> #define PLLX_MISC3 0x518
>
> -#define CCLKG_BURST_POLICY 0x368
> -#define CCLKLP_BURST_POLICY 0x370
> -#define SCLK_BURST_POLICY 0x028
> -#define SYSTEM_CLK_RATE 0x030
> #define SCLK_DIVIDER 0x2c
>
> static DEFINE_SPINLOCK(sysrate_lock);
> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> index 573e3c967ae1..9e863362d2bf 100644
> --- a/drivers/clk/tegra/clk.c
> +++ b/drivers/clk/tegra/clk.c
> @@ -70,6 +70,12 @@ static struct clk **clks;
> static int clk_num;
> static struct clk_onecell_data clk_data;
>
> +static u32 cclkg_burst_policy_ctx[2];
> +static u32 cclklp_burst_policy_ctx[2];
> +static u32 sclk_burst_policy_ctx[2];
> +static u32 sys_clk_divisor_ctx, system_rate_ctx;
> +static u32 spare_ctx, misc_clk_enb_ctx, clk_arm_ctx;
> +
> /* Handlers for SoC-specific reset lines */
> static int (*special_reset_assert)(unsigned long);
> static int (*special_reset_deassert)(unsigned long);
> @@ -199,6 +205,80 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
> }
> }
>
> +void tegra_cclkg_burst_policy_save_context(void)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < BURST_POLICY_REG_SIZE; i++)
> + cclkg_burst_policy_ctx[i] = readl_relaxed(clk_base +
> + CCLKG_BURST_POLICY +
> + (i * 4));
> +}
> +
> +void tegra_cclkg_burst_policy_restore_context(void)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < BURST_POLICY_REG_SIZE; i++)
> + writel_relaxed(cclkg_burst_policy_ctx[i],
> + clk_base + CCLKG_BURST_POLICY + (i * 4));
> +
> + fence_udelay(2, clk_base);
> +}
> +
> +void tegra_sclk_cclklp_burst_policy_save_context(void)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) {
> + cclklp_burst_policy_ctx[i] = readl_relaxed(clk_base +
> + CCLKLP_BURST_POLICY +
> + (i * 4));
> +
> + sclk_burst_policy_ctx[i] = readl_relaxed(clk_base +
> + SCLK_BURST_POLICY +
> + (i * 4));
> + }
> +
> + sys_clk_divisor_ctx = readl_relaxed(clk_base + SYS_CLK_DIV);
> + system_rate_ctx = readl_relaxed(clk_base + SYSTEM_CLK_RATE);
> + spare_ctx = readl_relaxed(clk_base + SPARE_REG0);
> + misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
> + clk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
> +}
> +
> +void tegra_sclk_cpulp_burst_policy_restore_context(void)
> +{
> + unsigned int i;
> + u32 val;
> +
> + /*
> + * resume SCLK and CPULP clocks
> + * for SCLk, set safe dividers values first and then restore source
> + * and dividers
> + */
> +
> + writel_relaxed(0x1, clk_base + SYSTEM_CLK_RATE);
> + val = readl_relaxed(clk_base + SYS_CLK_DIV);
> + if (val < sys_clk_divisor_ctx)
> + writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV);
> +
> + fence_udelay(2, clk_base);
> +
> + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) {
> + writel_relaxed(cclklp_burst_policy_ctx[i],
> + clk_base + CCLKLP_BURST_POLICY + (i * 4));
> + writel_relaxed(sclk_burst_policy_ctx[i],
> + clk_base + SCLK_BURST_POLICY + (i * 4));
> + }
> +
> + writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV);
> + writel_relaxed(system_rate_ctx, clk_base + SYSTEM_CLK_RATE);
> + writel_relaxed(spare_ctx, clk_base + SPARE_REG0);
> + writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
> + writel_relaxed(clk_arm_ctx, clk_base + CLK_MASK_ARM);
Why fence_udelay was needed above and not needed here?
> +}
28.06.2019 5:12, Sowjanya Komatineni пишет:
> During system suspend state, core power goes off and looses all the
> CAR controller register settings.
>
> This patch creates APIs for saving and restoring the context of Tegra
> CPUG, CPULP and SCLK.
>
> CPU and System clock context includes
> - CPUG, CPULP, and SCLK burst policy settings for clock sourcea of all
> their normal states.
> - SCLK divisor and System clock rate for restoring SCLK, AHB and APB
> rates on resume.
> - OSC_DIV settings which are used as reference clock input to some PLLs.
> - SPARE_REG and CLK_MASK settings.
>
> These APIs are used in Tegra210 clock driver during suspend and resume
> operation.
>
> Acked-by: Thierry Reding <[email protected]>
> Signed-off-by: Sowjanya Komatineni <[email protected]>
> ---
> drivers/clk/tegra/clk-tegra-super-gen4.c | 4 --
> drivers/clk/tegra/clk.c | 80 ++++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk.h | 14 ++++++
> 3 files changed, 94 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
> index cdfe7c9697e1..ed69ec4d883e 100644
> --- a/drivers/clk/tegra/clk-tegra-super-gen4.c
> +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
> @@ -19,10 +19,6 @@
> #define PLLX_MISC2 0x514
> #define PLLX_MISC3 0x518
>
> -#define CCLKG_BURST_POLICY 0x368
> -#define CCLKLP_BURST_POLICY 0x370
> -#define SCLK_BURST_POLICY 0x028
> -#define SYSTEM_CLK_RATE 0x030
> #define SCLK_DIVIDER 0x2c
>
> static DEFINE_SPINLOCK(sysrate_lock);
> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> index 573e3c967ae1..9e863362d2bf 100644
> --- a/drivers/clk/tegra/clk.c
> +++ b/drivers/clk/tegra/clk.c
> @@ -70,6 +70,12 @@ static struct clk **clks;
> static int clk_num;
> static struct clk_onecell_data clk_data;
>
> +static u32 cclkg_burst_policy_ctx[2];
> +static u32 cclklp_burst_policy_ctx[2];
> +static u32 sclk_burst_policy_ctx[2];
> +static u32 sys_clk_divisor_ctx, system_rate_ctx;
> +static u32 spare_ctx, misc_clk_enb_ctx, clk_arm_ctx;
> +
> /* Handlers for SoC-specific reset lines */
> static int (*special_reset_assert)(unsigned long);
> static int (*special_reset_deassert)(unsigned long);
> @@ -199,6 +205,80 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
> }
> }
>
> +void tegra_cclkg_burst_policy_save_context(void)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < BURST_POLICY_REG_SIZE; i++)
> + cclkg_burst_policy_ctx[i] = readl_relaxed(clk_base +
> + CCLKG_BURST_POLICY +
> + (i * 4));
> +}
> +
> +void tegra_cclkg_burst_policy_restore_context(void)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < BURST_POLICY_REG_SIZE; i++)
> + writel_relaxed(cclkg_burst_policy_ctx[i],
> + clk_base + CCLKG_BURST_POLICY + (i * 4));
> +
> + fence_udelay(2, clk_base);
> +}
> +
> +void tegra_sclk_cclklp_burst_policy_save_context(void)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) {
> + cclklp_burst_policy_ctx[i] = readl_relaxed(clk_base +
> + CCLKLP_BURST_POLICY +
> + (i * 4));
> +
> + sclk_burst_policy_ctx[i] = readl_relaxed(clk_base +
> + SCLK_BURST_POLICY +
> + (i * 4));
> + }
> +
> + sys_clk_divisor_ctx = readl_relaxed(clk_base + SYS_CLK_DIV);
> + system_rate_ctx = readl_relaxed(clk_base + SYSTEM_CLK_RATE);
> + spare_ctx = readl_relaxed(clk_base + SPARE_REG0);
> + misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
> + clk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
> +}
> +
> +void tegra_sclk_cpulp_burst_policy_restore_context(void)
> +{
> + unsigned int i;
> + u32 val;
> +
> + /*
> + * resume SCLK and CPULP clocks
> + * for SCLk, set safe dividers values first and then restore source
> + * and dividers
> + */
> +
> + writel_relaxed(0x1, clk_base + SYSTEM_CLK_RATE);
> + val = readl_relaxed(clk_base + SYS_CLK_DIV);
> + if (val < sys_clk_divisor_ctx)
> + writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV);
> +
> + fence_udelay(2, clk_base);
> +
> + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) {
> + writel_relaxed(cclklp_burst_policy_ctx[i],
> + clk_base + CCLKLP_BURST_POLICY + (i * 4));
> + writel_relaxed(sclk_burst_policy_ctx[i],
> + clk_base + SCLK_BURST_POLICY + (i * 4));
> + }
> +
> + writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV);
> + writel_relaxed(system_rate_ctx, clk_base + SYSTEM_CLK_RATE);
> + writel_relaxed(spare_ctx, clk_base + SPARE_REG0);
> + writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
> + writel_relaxed(clk_arm_ctx, clk_base + CLK_MASK_ARM);
> +}
> +
> struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
> {
> clk_base = regs;
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 8532f5150091..c66b0a73bb01 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -10,6 +10,16 @@
> #include <linux/clkdev.h>
> #include <linux/delay.h>
>
> +#define SCLK_BURST_POLICY 0x28
> +#define SYSTEM_CLK_RATE 0x30
> +#define CLK_MASK_ARM 0x44
> +#define MISC_CLK_ENB 0x48
> +#define CCLKG_BURST_POLICY 0x368
> +#define CCLKLP_BURST_POLICY 0x370
> +#define SYS_CLK_DIV 0x400
> +#define SPARE_REG0 0x55c
> +#define BURST_POLICY_REG_SIZE 2
"clk-tegra30.c", "clk-tegra114.c" and "clk-tegra124.c" also define the
CCLKG_BURST_POLICY .. apparently you haven't tried to compile ARM32 kernel because I
assume that compile should bark at the re-definitions.
29.06.2019 15:38, Dmitry Osipenko пишет:
> 29.06.2019 2:00, Sowjanya Komatineni пишет:
>>
>> On 6/28/19 5:05 AM, Dmitry Osipenko wrote:
>>> 28.06.2019 14:56, Dmitry Osipenko пишет:
>>>> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>>>>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>>>>
>>>>> During suspend, context of all pinctrl registers are stored and
>>>>> on resume they are all restored to have all the pinmux and pad
>>>>> configuration for normal operation.
>>>>>
>>>>> Acked-by: Thierry Reding <[email protected]>
>>>>> Signed-off-by: Sowjanya Komatineni <[email protected]>
>>>>> ---
>>>>> int tegra_pinctrl_probe(struct platform_device *pdev,
>>>>> const struct tegra_pinctrl_soc_data *soc_data);
>>>>> #endif
>>>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>>>> b/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>>>> index 0b56ad5c9c1c..edd3f4606cdb 100644
>>>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c
>>>>> @@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = {
>>>>> .driver = {
>>>>> .name = "tegra210-pinctrl",
>>>>> .of_match_table = tegra210_pinctrl_of_match,
>>>>> + .pm = &tegra_pinctrl_pm,
>>>>> },
>>>>> .probe = tegra210_pinctrl_probe,
>>>>> };
>>>>>
>>>> Could you please address my comments in the next revision if there will be one?
>>>>
>>> Also, what about adding ".pm' for other Tegras? I'm sure Jon could test them for you.
>>
>> This series is for Tegra210 SC7 entry/exit along with clocks and pinctrl suspend
>> resume needed for Tegra210 basic sc7 entry and exit.
>>
>> This includes pinctrl, pmc changes, clock-tegra210 driver changes all w.r.t Tegra210
>> platforms specific.
>>
>> Suspend/resume support for other Tegras will be in separate patch series.
>
> Okay, fair enough.
>
It may also make some sense to split this patch into two:
1) add generic tegra-pinctrl suspend-resume support
2) add suspend-resume OPS to the pinctrl-tegra210
For consistency.
28.06.2019 5:12, Sowjanya Komatineni пишет:
> This patch adds support for Tegra pinctrl driver suspend and resume.
>
> During suspend, context of all pinctrl registers are stored and
> on resume they are all restored to have all the pinmux and pad
> configuration for normal operation.
>
> Acked-by: Thierry Reding <[email protected]>
> Signed-off-by: Sowjanya Komatineni <[email protected]>
> ---
> drivers/pinctrl/tegra/pinctrl-tegra.c | 52 ++++++++++++++++++++++++++++++++
> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
> drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 +
> 3 files changed, 56 insertions(+)
>
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
> index 34596b246578..e7c0a1011cba 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -621,6 +621,43 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
> }
> }
>
> +static int tegra_pinctrl_suspend(struct device *dev)
> +{
> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
> + u32 *backup_regs = pmx->backup_regs;
> + u32 *regs;
> + unsigned int i, j;
> +
> + for (i = 0; i < pmx->nbanks; i++) {
> + regs = pmx->regs[i];
> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
> + *backup_regs++ = readl(regs++);
> + }
> +
> + return pinctrl_force_sleep(pmx->pctl);
> +}
> +
> +static int tegra_pinctrl_resume(struct device *dev)
> +{
> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
> + u32 *backup_regs = pmx->backup_regs;
> + u32 *regs;
> + unsigned int i, j;
> +
> + for (i = 0; i < pmx->nbanks; i++) {
> + regs = pmx->regs[i];
> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
> + writel(*backup_regs++, regs++);
> + }
> +
> + return 0;
> +}
> +
> +const struct dev_pm_ops tegra_pinctrl_pm = {
> + .suspend = &tegra_pinctrl_suspend,
> + .resume = &tegra_pinctrl_resume
> +};
Hm, so this are the generic platform-driver suspend-resume OPS here, which is very
nice! But.. shouldn't pinctrl be resumed before the CLK driver (which is syscore_ops
in this version of the series)? .. Given that "clock" function may need to be
selected for some of the pins.
29.06.2019 18:46, Dmitry Osipenko пишет:
> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>
>> During suspend, context of all pinctrl registers are stored and
>> on resume they are all restored to have all the pinmux and pad
>> configuration for normal operation.
>>
>> Acked-by: Thierry Reding <[email protected]>
>> Signed-off-by: Sowjanya Komatineni <[email protected]>
>> ---
>> drivers/pinctrl/tegra/pinctrl-tegra.c | 52 ++++++++++++++++++++++++++++++++
>> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
>> drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 +
>> 3 files changed, 56 insertions(+)
>>
>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
>> index 34596b246578..e7c0a1011cba 100644
>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
>> @@ -621,6 +621,43 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
>> }
>> }
>>
>> +static int tegra_pinctrl_suspend(struct device *dev)
>> +{
>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>> + u32 *backup_regs = pmx->backup_regs;
>> + u32 *regs;
>> + unsigned int i, j;
>> +
>> + for (i = 0; i < pmx->nbanks; i++) {
>> + regs = pmx->regs[i];
>> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
>> + *backup_regs++ = readl(regs++);
>> + }
>> +
>> + return pinctrl_force_sleep(pmx->pctl);
>> +}
>> +
>> +static int tegra_pinctrl_resume(struct device *dev)
>> +{
>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>> + u32 *backup_regs = pmx->backup_regs;
>> + u32 *regs;
>> + unsigned int i, j;
>> +
>> + for (i = 0; i < pmx->nbanks; i++) {
>> + regs = pmx->regs[i];
>> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
>> + writel(*backup_regs++, regs++);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +const struct dev_pm_ops tegra_pinctrl_pm = {
>> + .suspend = &tegra_pinctrl_suspend,
>> + .resume = &tegra_pinctrl_resume
>> +};
>
> Hm, so this are the generic platform-driver suspend-resume OPS here, which is very
> nice! But.. shouldn't pinctrl be resumed before the CLK driver (which is syscore_ops
> in this version of the series)? .. Given that "clock" function may need to be
> selected for some of the pins.
>
Oh, also what about GPIO-pinctrl suspend resume ordering .. is it okay that pinctrl
will be resumed after GPIO? Shouldn't a proper pin-muxing be selected at first?
This also looks to me very unsafe in a context of older Tegras which are initializing
the static muxing very early during of the boot, otherwise things won't work well for
the drivers.
29.06.2019 18:58, Dmitry Osipenko пишет:
> 29.06.2019 18:46, Dmitry Osipenko пишет:
>> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>>
>>> During suspend, context of all pinctrl registers are stored and
>>> on resume they are all restored to have all the pinmux and pad
>>> configuration for normal operation.
>>>
>>> Acked-by: Thierry Reding <[email protected]>
>>> Signed-off-by: Sowjanya Komatineni <[email protected]>
>>> ---
>>> drivers/pinctrl/tegra/pinctrl-tegra.c | 52 ++++++++++++++++++++++++++++++++
>>> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
>>> drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 +
>>> 3 files changed, 56 insertions(+)
>>>
>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
>>> index 34596b246578..e7c0a1011cba 100644
>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
>>> @@ -621,6 +621,43 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
>>> }
>>> }
>>>
>>> +static int tegra_pinctrl_suspend(struct device *dev)
>>> +{
>>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>>> + u32 *backup_regs = pmx->backup_regs;
>>> + u32 *regs;
>>> + unsigned int i, j;
>>> +
>>> + for (i = 0; i < pmx->nbanks; i++) {
>>> + regs = pmx->regs[i];
>>> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
>>> + *backup_regs++ = readl(regs++);
>>> + }
>>> +
>>> + return pinctrl_force_sleep(pmx->pctl);
>>> +}
>>> +
>>> +static int tegra_pinctrl_resume(struct device *dev)
>>> +{
>>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>>> + u32 *backup_regs = pmx->backup_regs;
>>> + u32 *regs;
>>> + unsigned int i, j;
>>> +
>>> + for (i = 0; i < pmx->nbanks; i++) {
>>> + regs = pmx->regs[i];
>>> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
>>> + writel(*backup_regs++, regs++);
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +const struct dev_pm_ops tegra_pinctrl_pm = {
>>> + .suspend = &tegra_pinctrl_suspend,
>>> + .resume = &tegra_pinctrl_resume
>>> +};
>>
>> Hm, so this are the generic platform-driver suspend-resume OPS here, which is very
>> nice! But.. shouldn't pinctrl be resumed before the CLK driver (which is syscore_ops
>> in this version of the series)? .. Given that "clock" function may need to be
>> selected for some of the pins.
>>
>
> Oh, also what about GPIO-pinctrl suspend resume ordering .. is it okay that pinctrl
> will be resumed after GPIO? Shouldn't a proper pin-muxing be selected at first?
>
> This also looks to me very unsafe in a context of older Tegras which are initializing
> the static muxing very early during of the boot, otherwise things won't work well for
> the drivers.
>
Although, scratch what I wrote about older Tegras. We are probing pinctl driver very
early, hence it should suspend last and resume first. Should be okay.
On Fri, Jun 28, 2019 at 4:13 AM Sowjanya Komatineni
<[email protected]> wrote:
> This patch adds support for Tegra pinctrl driver suspend and resume.
>
> During suspend, context of all pinctrl registers are stored and
> on resume they are all restored to have all the pinmux and pad
> configuration for normal operation.
>
> Acked-by: Thierry Reding <[email protected]>
> Signed-off-by: Sowjanya Komatineni <[email protected]>
Looks good.
Can I just apply this patch or does it need to go in with
the other (clk) changes?
Yours,
Linus Walleij
On Sat, Jun 29, 2019 at 5:58 PM Dmitry Osipenko <[email protected]> wrote:
> Oh, also what about GPIO-pinctrl suspend resume ordering .. is it okay that pinctrl
> will be resumed after GPIO? Shouldn't a proper pin-muxing be selected at first?
Thierry sent some initial patches about this I think. We need to use
device links for this to work properly so he adds support for
linking the pinctrl and GPIO devices through the ranges.
For links between pin control handles and their consumers, see also:
036f394dd77f pinctrl: Enable device link creation for pin control
c6045b4e3cad pinctrl: stmfx: enable links creations
489b64d66325 pinctrl: stm32: Add links to consumers
I am using STM32 as guinea pig for this, consider adding links also
from the Tegra pinctrl. I might simply make these pinctrl consumer
to producer links default because I think it makes a lot sense.
Yours,
Linus Walleij
04.07.2019 10:31, Linus Walleij пишет:
> On Sat, Jun 29, 2019 at 5:58 PM Dmitry Osipenko <[email protected]> wrote:
>
>> Oh, also what about GPIO-pinctrl suspend resume ordering .. is it okay that pinctrl
>> will be resumed after GPIO? Shouldn't a proper pin-muxing be selected at first?
>
> Thierry sent some initial patches about this I think. We need to use
> device links for this to work properly so he adds support for
> linking the pinctrl and GPIO devices through the ranges.
>
> For links between pin control handles and their consumers, see also:
> 036f394dd77f pinctrl: Enable device link creation for pin control
> c6045b4e3cad pinctrl: stmfx: enable links creations
> 489b64d66325 pinctrl: stm32: Add links to consumers
>
> I am using STM32 as guinea pig for this, consider adding links also
> from the Tegra pinctrl. I might simply make these pinctrl consumer
> to producer links default because I think it makes a lot sense.
IIUC, currently the plan is to resume pinctrl *after* GPIO for Tegra210 [1]. But this
contradicts to what was traditionally done for older Tegras where pinctrl was always
resumed first and apparently it won't work well for the GPIO ranges as well. I think this
and the other patchsets related to suspend-resume still need some more thought.
[1] https://patchwork.kernel.org/patch/11012077/
On 7/4/19 3:40 AM, Dmitry Osipenko wrote:
> 04.07.2019 10:31, Linus Walleij пишет:
>> On Sat, Jun 29, 2019 at 5:58 PM Dmitry Osipenko <[email protected]> wrote:
>>
>>> Oh, also what about GPIO-pinctrl suspend resume ordering .. is it okay that pinctrl
>>> will be resumed after GPIO? Shouldn't a proper pin-muxing be selected at first?
>> Thierry sent some initial patches about this I think. We need to use
>> device links for this to work properly so he adds support for
>> linking the pinctrl and GPIO devices through the ranges.
>>
>> For links between pin control handles and their consumers, see also:
>> 036f394dd77f pinctrl: Enable device link creation for pin control
>> c6045b4e3cad pinctrl: stmfx: enable links creations
>> 489b64d66325 pinctrl: stm32: Add links to consumers
>>
>> I am using STM32 as guinea pig for this, consider adding links also
>> from the Tegra pinctrl. I might simply make these pinctrl consumer
>> to producer links default because I think it makes a lot sense.
> IIUC, currently the plan is to resume pinctrl *after* GPIO for Tegra210 [1]. But this
> contradicts to what was traditionally done for older Tegras where pinctrl was always
> resumed first and apparently it won't work well for the GPIO ranges as well. I think this
> and the other patchsets related to suspend-resume still need some more thought.
>
> [1] https://patchwork.kernel.org/patch/11012077/
Park bit was introduced from Tegra210 onwards and during suspend/resume,
requirement of gpio restore prior to pinctrl restore is not required for
prior Tegra210.
Also currently pinctrl suspend/resume implementation for prior Tegra210
is not yet upstreamed but having gpio restore prior to pinmux during
suspend/resume should not cause any issue for prior tegra's as well as
gpio resume restores pins back to same gpio config as they were during
suspend entry.
On 6/29/19 8:46 AM, Dmitry Osipenko wrote:
> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>
>> During suspend, context of all pinctrl registers are stored and
>> on resume they are all restored to have all the pinmux and pad
>> configuration for normal operation.
>>
>> Acked-by: Thierry Reding <[email protected]>
>> Signed-off-by: Sowjanya Komatineni <[email protected]>
>> ---
>> drivers/pinctrl/tegra/pinctrl-tegra.c | 52 ++++++++++++++++++++++++++++++++
>> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
>> drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 +
>> 3 files changed, 56 insertions(+)
>>
>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
>> index 34596b246578..e7c0a1011cba 100644
>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
>> @@ -621,6 +621,43 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
>> }
>> }
>>
>> +static int tegra_pinctrl_suspend(struct device *dev)
>> +{
>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>> + u32 *backup_regs = pmx->backup_regs;
>> + u32 *regs;
>> + unsigned int i, j;
>> +
>> + for (i = 0; i < pmx->nbanks; i++) {
>> + regs = pmx->regs[i];
>> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
>> + *backup_regs++ = readl(regs++);
>> + }
>> +
>> + return pinctrl_force_sleep(pmx->pctl);
>> +}
>> +
>> +static int tegra_pinctrl_resume(struct device *dev)
>> +{
>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>> + u32 *backup_regs = pmx->backup_regs;
>> + u32 *regs;
>> + unsigned int i, j;
>> +
>> + for (i = 0; i < pmx->nbanks; i++) {
>> + regs = pmx->regs[i];
>> + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++)
>> + writel(*backup_regs++, regs++);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +const struct dev_pm_ops tegra_pinctrl_pm = {
>> + .suspend = &tegra_pinctrl_suspend,
>> + .resume = &tegra_pinctrl_resume
>> +};
> Hm, so this are the generic platform-driver suspend-resume OPS here, which is very
> nice! But.. shouldn't pinctrl be resumed before the CLK driver (which is syscore_ops
> in this version of the series)? .. Given that "clock" function may need to be
> selected for some of the pins.
selection of clock functions on some Tegra pins through corresponding
pinmux (like extperiph clks) can happen after clock driver resume as
well where clock source is restored to state during suspend before
selecting clock function on that pin.
13.07.2019 8:31, Sowjanya Komatineni пишет:
>
> On 7/4/19 3:40 AM, Dmitry Osipenko wrote:
>> 04.07.2019 10:31, Linus Walleij пишет:
>>> On Sat, Jun 29, 2019 at 5:58 PM Dmitry Osipenko <[email protected]>
>>> wrote:
>>>
>>>> Oh, also what about GPIO-pinctrl suspend resume ordering .. is it
>>>> okay that pinctrl
>>>> will be resumed after GPIO? Shouldn't a proper pin-muxing be
>>>> selected at first?
>>> Thierry sent some initial patches about this I think. We need to use
>>> device links for this to work properly so he adds support for
>>> linking the pinctrl and GPIO devices through the ranges.
>>>
>>> For links between pin control handles and their consumers, see also:
>>> 036f394dd77f pinctrl: Enable device link creation for pin control
>>> c6045b4e3cad pinctrl: stmfx: enable links creations
>>> 489b64d66325 pinctrl: stm32: Add links to consumers
>>>
>>> I am using STM32 as guinea pig for this, consider adding links also
>>> from the Tegra pinctrl. I might simply make these pinctrl consumer
>>> to producer links default because I think it makes a lot sense.
>> IIUC, currently the plan is to resume pinctrl *after* GPIO for
>> Tegra210 [1]. But this
>> contradicts to what was traditionally done for older Tegras where
>> pinctrl was always
>> resumed first and apparently it won't work well for the GPIO ranges as
>> well. I think this
>> and the other patchsets related to suspend-resume still need some more
>> thought.
>>
>> [1] https://patchwork.kernel.org/patch/11012077/
>
> Park bit was introduced from Tegra210 onwards and during suspend/resume,
> requirement of gpio restore prior to pinctrl restore is not required for
> prior Tegra210.
>
> Also currently pinctrl suspend/resume implementation for prior Tegra210
> is not yet upstreamed but having gpio restore prior to pinmux during
> suspend/resume should not cause any issue for prior tegra's as well as
> gpio resume restores pins back to same gpio config as they were during
> suspend entry.
>
Okay!