In ITLB miss handled the line supposed to clear bits 20-23 on the
L2 ITLB entry is buggy and does indeed nothing, leading to undefined
value which could allow execution when it shouldn't.
Properly do the clearing with the relevant instruction.
Fixes: 74fabcadfd43 ("powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers")
Cc: [email protected]
Signed-off-by: Christophe Leroy <[email protected]>
---
arch/powerpc/kernel/head_8xx.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 9922306ae512..073a651787df 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -256,7 +256,7 @@ InstructionTLBMiss:
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
- rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
+ rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
--
2.25.0
Christophe Leroy <[email protected]> writes:
> In ITLB miss handled the line supposed to clear bits 20-23 on the
> L2 ITLB entry is buggy and does indeed nothing, leading to undefined
> value which could allow execution when it shouldn't.
>
> Properly do the clearing with the relevant instruction.
>
> Fixes: 74fabcadfd43 ("powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers")
> Cc: [email protected]
> Signed-off-by: Christophe Leroy <[email protected]>
> ---
> arch/powerpc/kernel/head_8xx.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
> index 9922306ae512..073a651787df 100644
> --- a/arch/powerpc/kernel/head_8xx.S
> +++ b/arch/powerpc/kernel/head_8xx.S
> @@ -256,7 +256,7 @@ InstructionTLBMiss:
> * set. All other Linux PTE bits control the behavior
> * of the MMU.
> */
> - rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
> + rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
> rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
> ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
> mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
> --
> 2.25.0
Looks a valid change.
rlwimi r10, r10, 0, 0x0f00 means:
r10 = ((r10 << 0) & 0x0f00) | (r10 & ~0x0f00) which ends up being
r10 = r10
On ISA, rlwinm is recommended for clearing high order bits.
rlwinm r10, r10, 0, ~0x0f00 means:
r10 = (r10 << 0) & ~0x0f00
Which does exactly what the comments suggests.
FWIW:
Reviwed-by: Leonardo Bras <[email protected]>
On Sun, 2020-02-09 at 18:14 +0000, Christophe Leroy wrote:
> In ITLB miss handled the line supposed to clear bits 20-23 on the
> L2 ITLB entry is buggy and does indeed nothing, leading to undefined
> value which could allow execution when it shouldn't.
>
> Properly do the clearing with the relevant instruction.
>
> Fixes: 74fabcadfd43 ("powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers")
> Cc: [email protected]
> Signed-off-by: Christophe Leroy <[email protected]>
> ---
> arch/powerpc/kernel/head_8xx.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
> index 9922306ae512..073a651787df 100644
> --- a/arch/powerpc/kernel/head_8xx.S
> +++ b/arch/powerpc/kernel/head_8xx.S
> @@ -256,7 +256,7 @@ InstructionTLBMiss:
> * set. All other Linux PTE bits control the behavior
> * of the MMU.
> */
> - rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
> + rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
> rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
> ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
> mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
Looks a valid change.
rlwimi r10, r10, 0, 0x0f00 means:
r10 = ((r10 << 0) & 0x0f00) | (r10 & ~0x0f00) which ends up being
r10 = r10
On ISA, rlwinm is recommended for clearing high order bits.
rlwinm r10, r10, 0, ~0x0f00 means:
r10 = (r10 << 0) & ~0x0f00
Which does exactly what the comments suggests.
FWIW:
Reviwed-by: Leonardo Bras <[email protected]>
Le 15/02/2020 à 07:28, Leonardo Bras a écrit :
> On Sun, 2020-02-09 at 18:14 +0000, Christophe Leroy wrote:
>> In ITLB miss handled the line supposed to clear bits 20-23 on the
>> L2 ITLB entry is buggy and does indeed nothing, leading to undefined
>> value which could allow execution when it shouldn't.
>>
>> Properly do the clearing with the relevant instruction.
>>
>> Fixes: 74fabcadfd43 ("powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers")
>> Cc: [email protected]
>> Signed-off-by: Christophe Leroy <[email protected]>
>> ---
>> arch/powerpc/kernel/head_8xx.S | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
>> index 9922306ae512..073a651787df 100644
>> --- a/arch/powerpc/kernel/head_8xx.S
>> +++ b/arch/powerpc/kernel/head_8xx.S
>> @@ -256,7 +256,7 @@ InstructionTLBMiss:
>> * set. All other Linux PTE bits control the behavior
>> * of the MMU.
>> */
>> - rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
>> + rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
>> rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
>> ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
>> mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
>
> Looks a valid change.
> rlwimi r10, r10, 0, 0x0f00 means:
> r10 = ((r10 << 0) & 0x0f00) | (r10 & ~0x0f00) which ends up being
> r10 = r10
>
> On ISA, rlwinm is recommended for clearing high order bits.
> rlwinm r10, r10, 0, ~0x0f00 means:
> r10 = (r10 << 0) & ~0x0f00
>
> Which does exactly what the comments suggests.
>
> FWIW:
> Reviwed-by: Leonardo Bras <[email protected]>
>
I guess you mean
Reviewed-by: Leonardo Bras <[email protected]>
On Sat, 2020-02-15 at 11:17 +0100, Christophe Leroy wrote:
>
> Le 15/02/2020 à 07:28, Leonardo Bras a écrit :
> > On Sun, 2020-02-09 at 18:14 +0000, Christophe Leroy wrote:
> > > In ITLB miss handled the line supposed to clear bits 20-23 on the
> > > L2 ITLB entry is buggy and does indeed nothing, leading to undefined
> > > value which could allow execution when it shouldn't.
> > >
> > > Properly do the clearing with the relevant instruction.
> > >
> > > Fixes: 74fabcadfd43 ("powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers")
> > > Cc: [email protected]
> > > Signed-off-by: Christophe Leroy <[email protected]>
> > > ---
> > > arch/powerpc/kernel/head_8xx.S | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
> > > index 9922306ae512..073a651787df 100644
> > > --- a/arch/powerpc/kernel/head_8xx.S
> > > +++ b/arch/powerpc/kernel/head_8xx.S
> > > @@ -256,7 +256,7 @@ InstructionTLBMiss:
> > > * set. All other Linux PTE bits control the behavior
> > > * of the MMU.
> > > */
> > > - rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
> > > + rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
> > > rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
> > > ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
> > > mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
> >
> > Looks a valid change.
> > rlwimi r10, r10, 0, 0x0f00 means:
> > r10 = ((r10 << 0) & 0x0f00) | (r10 & ~0x0f00) which ends up being
> > r10 = r10
> >
> > On ISA, rlwinm is recommended for clearing high order bits.
> > rlwinm r10, r10, 0, ~0x0f00 means:
> > r10 = (r10 << 0) & ~0x0f00
> >
> > Which does exactly what the comments suggests.
> >
> > FWIW:
> > Reviwed-by: Leonardo Bras <[email protected]>
> >
>
> I guess you mean
>
> Reviewed-by: Leonardo Bras <[email protected]>
Yes, sorry for the typo.
On Sun, 2020-02-09 at 18:14:42 UTC, Christophe Leroy wrote:
> In ITLB miss handled the line supposed to clear bits 20-23 on the
> L2 ITLB entry is buggy and does indeed nothing, leading to undefined
> value which could allow execution when it shouldn't.
>
> Properly do the clearing with the relevant instruction.
>
> Fixes: 74fabcadfd43 ("powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers")
> Cc: [email protected]
> Signed-off-by: Christophe Leroy <[email protected]>
Applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/a4031afb9d10d97f4d0285844abbc0ab04245304
cheers
On Tue, 2020-02-11 at 01:28 -0300, Leonardo Bras wrote:
> Looks a valid change.
> rlwimi r10, r10, 0, 0x0f00 means:
> r10 = ((r10 << 0) & 0x0f00) | (r10 & ~0x0f00) which ends up being
> r10 = r10
>
> On ISA, rlwinm is recommended for clearing high order bits.
> rlwinm r10, r10, 0, ~0x0f00 means:
> r10 = (r10 << 0) & ~0x0f00
>
> Which does exactly what the comments suggests.
>
> FWIW:
> Reviwed-by: Leonardo Bras <[email protected]>
Sorry, I just realized the above was not very clear on my part.
What I meant to say was:
I think your change is correct, as it correctly fixes this line.
I would suggest adding the text bellow to your commit message, making
it easier to understand why rlwimi is not the right instruction clear
bytes 20-23, and why rlwinm is.
The current instruction can be translated to C as:
rlwimi r10, r10, 0, 0x0f00
r10 = ((r10 << 0) & 0x0f00) | (r10 & ~0x0f00) ->
r10 = (r10 & 0x0f00) | (r10 & ~0x0f00) ->
r10 = r10
The new proposed instruction can be translated to C as:
rlwinm r10, r10, 0, ~0x0f00 ->
r10 = (r10 << 0) & ~0x0f00
Which clears bits 20-23 as comment on code states.
Best regards,
Leonardo Bras