Arnd Bergmann <[email protected]> writes:
> From: Arnd Bergmann <[email protected]>
>
> The integrated assembler in clang does not understand the xscale
> specific mra/mar instructions:
>
> arch/arm/mach-pxa/pxa27x.c:136:15: error: unsupported
> architectural extension: xscale
> asm volatile(".arch_extension xscale\n\t"
> arch/arm/mach-pxa/pxa27x.c:136:40: error: invalid instruction,
> did you mean: mcr, mla, mrc, mrs, msr?
> mra r2, r3, acc0
>
> Since these are coprocessor features, the same can be expressed
> using
> mrrc/mcrr, so use that for builds with IAS.
Ok Arnd, but "mrrc" is an ARMv6 instruction if I'm not mistaken.
Yet PXA27X is an ARMv5 XScale instruction set IP.
Is that patch correct therefore, or is it just to make clang happy
even if it's
not correct ?
Cheers.
--
Robert
On Sat, Dec 17, 2022, at 21:45, Robert Jarzmik wrote:
> Arnd Bergmann <[email protected]> writes:
>
>> From: Arnd Bergmann <[email protected]>
>>
>> The integrated assembler in clang does not understand the xscale
>> specific mra/mar instructions:
>>
>> arch/arm/mach-pxa/pxa27x.c:136:15: error: unsupported
>> architectural extension: xscale
>> asm volatile(".arch_extension xscale\n\t"
>> arch/arm/mach-pxa/pxa27x.c:136:40: error: invalid instruction,
>> did you mean: mcr, mla, mrc, mrs, msr?
>> mra r2, r3, acc0
>>
>> Since these are coprocessor features, the same can be expressed
>> using
>> mrrc/mcrr, so use that for builds with IAS.
> Ok Arnd, but "mrrc" is an ARMv6 instruction if I'm not mistaken.
> Yet PXA27X is an ARMv5 XScale instruction set IP.
>
> Is that patch correct therefore, or is it just to make clang happy
> even if it's not correct ?
According to
https://developer.arm.com/documentation/dui0231/b/arm-instruction-reference/coprocessor-instructions/mrrc-and-mrrc2?lang=en
"MRRC is available in ARMv6 and above, and E variants of ARMv5
excluding xP variants". I'm not entire sure what "xP variants"
means, but we do build for ARMv5E, so I think this is actually
correct.
Arnd