Since the merge of the Mali dt bindings at [1], add support for Mali clocks
and DT node.
The Mali is clocked by two identical clock paths behind a glitch free mux
to safely change frequency while running.
So these clocks must be added to the meson-gxbb clock controller.
Changes since v3 at [7] :
- Removed CLK_IGNORE_UNUSED on mali clocks
Changes since v2 at [5] :
- Rebased on v2 Audio Clocks patchset from Jerome Brunet at [6]
- Marked parents names list as static
- Reworded patch 3 commit message
Changes since v1 at [2] :
- Remove GP0 fixes, this will pushed later, for base frequency it can depend on fclk_div3
- Add GXL support
- rebase on clk-next and jbrunet's patchset at [3] and [4]
- get rid of composite clocks, this adds more clocks IDs and exposes 2 more clocks
[7] http://lkml.kernel.org/r/[email protected]
[6] http://lkml.kernel.org/r/[email protected]
[5] http://lkml.kernel.org/r/[email protected]
[4] http://lkml.kernel.org/r/[email protected]
[3] http://lkml.kernel.org/r/[email protected]
[2] http://lkml.kernel.org/r/[email protected]
[1] http://lkml.kernel.org/r/b098c4fa9fce88361cca20417978734d0e1b5cca.1485939041.git-series.maxime.ripard@free-electrons.com
Neil Armstrong (3):
clk: meson-gxbb: Add MALI clock IDS
clk: meson-gxbb: Add MALI clocks
ARM64: dts: meson-gx: Add MALI nodes for GXBB and GXL
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 37 ++++++
arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi | 43 +++++++
arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 1 +
drivers/clk/meson/gxbb.c | 139 +++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 +-
include/dt-bindings/clock/gxbb-clkc.h | 5 +
7 files changed, 234 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
--
1.9.1
The same MALI-450 MP3 GPU is present in the GXBB and GXL SoCs.
The node is simply added in the meson-gxbb.dtsi file.
For GXL, since a lot is shared with the GXM that has a MALI-T820 IP, this
patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific
dtsi files.
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 37 ++++++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi | 43 ++++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 1 +
4 files changed, 82 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 04b3324..0617a3d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -478,6 +478,43 @@
};
};
+&apb {
+ mali: gpu@c0000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0xc0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_MALI_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <666666666>,
+ <0>; /* Do Nothing */
+ };
+};
+
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
new file mode 100644
index 0000000..f06cc234
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2017 BayLibre SAS
+ * Author: Neil Armstrong <[email protected]>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+&apb {
+ mali: gpu@c0000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0xc0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_MALI_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <666666666>,
+ <0>; /* Do Nothing */
+ };
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
index 615308e..5a90e30 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
@@ -42,6 +42,7 @@
*/
#include "meson-gxl.dtsi"
+#include "meson-gxl-mali.dtsi"
/ {
compatible = "amlogic,s905d", "amlogic,meson-gxl";
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
index 08237ee..0f78d83 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
@@ -42,6 +42,7 @@
*/
#include "meson-gxl.dtsi"
+#include "meson-gxl-mali.dtsi"
/ {
compatible = "amlogic,s905x", "amlogic,meson-gxl";
--
1.9.1
The Mali is clocked by two identical clock paths behind a glitch free mux
to safely change frequency while running.
The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate.
Expose these two clocks trees using generic clocks.
Finally the glitch free mux is added as "mali" clock.
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/clk/meson/gxbb.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 5059c7b..d07dc22 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -634,6 +634,131 @@
},
};
+/*
+ * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
+ * muxed by a glitch-free switch.
+ */
+
+static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
+static const char *gxbb_mali_0_1_parent_names[] = {
+ "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
+ "fclk_div4", "fclk_div3", "fclk_div5"
+};
+
+static struct clk_mux gxbb_mali_0_sel = {
+ .reg = (void *)HHI_MALI_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 9,
+ .table = mux_table_mali_0_1,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_0_sel",
+ .ops = &clk_mux_ops,
+ /*
+ * bits 10:9 selects from 8 possible parents:
+ * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
+ * fclk_div4, fclk_div3, fclk_div5
+ */
+ .parent_names = gxbb_mali_0_1_parent_names,
+ .num_parents = 8,
+ .flags = CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+static struct clk_divider gxbb_mali_0_div = {
+ .reg = (void *)HHI_MALI_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_0_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "mali_0_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+static struct clk_gate gxbb_mali_0 = {
+ .reg = (void *)HHI_MALI_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_0",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "mali_0_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_mux gxbb_mali_1_sel = {
+ .reg = (void *)HHI_MALI_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 25,
+ .table = mux_table_mali_0_1,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_1_sel",
+ .ops = &clk_mux_ops,
+ /*
+ * bits 10:9 selects from 8 possible parents:
+ * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
+ * fclk_div4, fclk_div3, fclk_div5
+ */
+ .parent_names = gxbb_mali_0_1_parent_names,
+ .num_parents = 8,
+ .flags = CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+static struct clk_divider gxbb_mali_1_div = {
+ .reg = (void *)HHI_MALI_CLK_CNTL,
+ .shift = 16,
+ .width = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_1_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "mali_1_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+static struct clk_gate gxbb_mali_1 = {
+ .reg = (void *)HHI_MALI_CLK_CNTL,
+ .bit_idx = 24,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_1",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "mali_1_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 mux_table_mali[] = {0, 1};
+static const char *gxbb_mali_parent_names[] = {
+ "mali_0", "mali_1"
+};
+
+static struct clk_mux gxbb_mali = {
+ .reg = (void *)HHI_MALI_CLK_CNTL,
+ .mask = 1,
+ .shift = 31,
+ .table = mux_table_mali,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mali",
+ .ops = &clk_mux_ops,
+ .parent_names = gxbb_mali_parent_names,
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -827,6 +952,13 @@
[CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
[CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
[CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
+ [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
+ [CLKID_MALI_0] = &gxbb_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
+ [CLKID_MALI_1] = &gxbb_mali_1.hw,
+ [CLKID_MALI] = &gxbb_mali.hw,
},
.num = NR_CLKS,
};
@@ -930,16 +1062,23 @@
&gxbb_emmc_b,
&gxbb_emmc_c,
&gxbb_sar_adc_clk,
+ &gxbb_mali_0,
+ &gxbb_mali_1,
};
static struct clk_mux *const gxbb_clk_muxes[] = {
&gxbb_mpeg_clk_sel,
&gxbb_sar_adc_clk_sel,
+ &gxbb_mali_0_sel,
+ &gxbb_mali_1_sel,
+ &gxbb_mali,
};
static struct clk_divider *const gxbb_clk_dividers[] = {
&gxbb_mpeg_clk_div,
&gxbb_sar_adc_clk_div,
+ &gxbb_mali_0_div,
+ &gxbb_mali_1_div,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
--
1.9.1
Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings.
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/clk/meson/gxbb.h | 9 ++++++++-
include/dt-bindings/clock/gxbb-clkc.h | 5 +++++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 274f587..73efdc3 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -268,8 +268,15 @@
/* CLKID_SAR_ADC_CLK */
/* CLKID_SAR_ADC_SEL */
#define CLKID_SAR_ADC_DIV 99
+/* CLKID_MALI_0_SEL */
+#define CLKID_MALI_0_DIV 101
+/* CLKID_MALI_0 */
+/* CLKID_MALI_1_SEL */
+#define CLKID_MALI_1_DIV 104
+/* CLKID_MALI_1 */
+/* CLKID_MALI */
-#define NR_CLKS 100
+#define NR_CLKS 107
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index f08f06d..ef7d6b7 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -35,5 +35,10 @@
#define CLKID_SD_EMMC_C 96
#define CLKID_SAR_ADC_CLK 97
#define CLKID_SAR_ADC_SEL 98
+#define CLKID_MALI_0_SEL 100
+#define CLKID_MALI_0 102
+#define CLKID_MALI_1_SEL 103
+#define CLKID_MALI_1 105
+#define CLKID_MALI 106
#endif /* __GXBB_CLKC_H */
--
1.9.1
Neil Armstrong <[email protected]> writes:
> The same MALI-450 MP3 GPU is present in the GXBB and GXL SoCs.
>
> The node is simply added in the meson-gxbb.dtsi file.
>
> For GXL, since a lot is shared with the GXM that has a MALI-T820 IP, this
> patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific
> dtsi files.
>
> Signed-off-by: Neil Armstrong <[email protected]>
LGTM, I can apply this when the clk driver changes are merged (feel free
to let me know when that happens, in case I'm not paying attention.)
<bikeshed>
nit: This series (and previous ones) use MALI, but I believe the correct
way is Mali. Could you standarize on that throughout the series?
</bikeshed>
Kevin
> ---
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 37 ++++++++++++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi | 43 ++++++++++++++++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 1 +
> 4 files changed, 82 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> index 04b3324..0617a3d 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> @@ -478,6 +478,43 @@
> };
> };
>
> +&apb {
> + mali: gpu@c0000 {
> + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
> + reg = <0x0 0xc0000 0x0 0x40000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "gp", "gpmmu", "pp", "pmu",
> + "pp0", "ppmmu0", "pp1", "ppmmu1",
> + "pp2", "ppmmu2";
> + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
> + clock-names = "bus", "core";
> +
> + /*
> + * Mali clocking is provided by two identical clock paths
> + * MALI_0 and MALI_1 muxed to a single clock by a glitch
> + * free mux to safely change frequency while running.
> + */
> + assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
> + <&clkc CLKID_MALI_0>,
> + <&clkc CLKID_MALI>; /* Glitch free mux */
> + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
> + <0>, /* Do Nothing */
> + <&clkc CLKID_MALI_0>;
> + assigned-clock-rates = <0>, /* Do Nothing */
> + <666666666>,
> + <0>; /* Do Nothing */
> + };
> +};
> +
> &i2c_A {
> clocks = <&clkc CLKID_I2C>;
> };
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
> new file mode 100644
> index 0000000..f06cc234
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (c) 2017 BayLibre SAS
> + * Author: Neil Armstrong <[email protected]>
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +&apb {
> + mali: gpu@c0000 {
> + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
> + reg = <0x0 0xc0000 0x0 0x40000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "gp", "gpmmu", "pp", "pmu",
> + "pp0", "ppmmu0", "pp1", "ppmmu1",
> + "pp2", "ppmmu2";
> + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
> + clock-names = "bus", "core";
> +
> + /*
> + * Mali clocking is provided by two identical clock paths
> + * MALI_0 and MALI_1 muxed to a single clock by a glitch
> + * free mux to safely change frequency while running.
> + */
> + assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
> + <&clkc CLKID_MALI_0>,
> + <&clkc CLKID_MALI>; /* Glitch free mux */
> + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
> + <0>, /* Do Nothing */
> + <&clkc CLKID_MALI_0>;
> + assigned-clock-rates = <0>, /* Do Nothing */
> + <666666666>,
> + <0>; /* Do Nothing */
> + };
> +};
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
> index 615308e..5a90e30 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
> @@ -42,6 +42,7 @@
> */
>
> #include "meson-gxl.dtsi"
> +#include "meson-gxl-mali.dtsi"
>
> / {
> compatible = "amlogic,s905d", "amlogic,meson-gxl";
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
> index 08237ee..0f78d83 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
> @@ -42,6 +42,7 @@
> */
>
> #include "meson-gxl.dtsi"
> +#include "meson-gxl-mali.dtsi"
>
> / {
> compatible = "amlogic,s905x", "amlogic,meson-gxl";
Quoting Kevin Hilman (2017-03-24 12:20:31)
> Neil Armstrong <[email protected]> writes:
>
> > The same MALI-450 MP3 GPU is present in the GXBB and GXL SoCs.
> >
> > The node is simply added in the meson-gxbb.dtsi file.
> >
> > For GXL, since a lot is shared with the GXM that has a MALI-T820 IP, this
> > patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific
> > dtsi files.
> >
> > Signed-off-by: Neil Armstrong <[email protected]>
>
> LGTM, I can apply this when the clk driver changes are merged (feel free
> to let me know when that happens, in case I'm not paying attention.)
Applied to clk-meson, a stable branch, which has been merged into
clk-next.
Kevin, the dtsi is all yours.
Regards,
Mike
>
> <bikeshed>
> nit: This series (and previous ones) use MALI, but I believe the correct
> way is Mali. Could you standarize on that throughout the series?
> </bikeshed>
>
> Kevin
>
> > ---
> > arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 37 ++++++++++++++++++++
> > arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi | 43 ++++++++++++++++++++++++
> > arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi | 1 +
> > arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 1 +
> > 4 files changed, 82 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > index 04b3324..0617a3d 100644
> > --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > @@ -478,6 +478,43 @@
> > };
> > };
> >
> > +&apb {
> > + mali: gpu@c0000 {
> > + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
> > + reg = <0x0 0xc0000 0x0 0x40000>;
> > + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "gp", "gpmmu", "pp", "pmu",
> > + "pp0", "ppmmu0", "pp1", "ppmmu1",
> > + "pp2", "ppmmu2";
> > + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
> > + clock-names = "bus", "core";
> > +
> > + /*
> > + * Mali clocking is provided by two identical clock paths
> > + * MALI_0 and MALI_1 muxed to a single clock by a glitch
> > + * free mux to safely change frequency while running.
> > + */
> > + assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
> > + <&clkc CLKID_MALI_0>,
> > + <&clkc CLKID_MALI>; /* Glitch free mux */
> > + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
> > + <0>, /* Do Nothing */
> > + <&clkc CLKID_MALI_0>;
> > + assigned-clock-rates = <0>, /* Do Nothing */
> > + <666666666>,
> > + <0>; /* Do Nothing */
> > + };
> > +};
> > +
> > &i2c_A {
> > clocks = <&clkc CLKID_I2C>;
> > };
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
> > new file mode 100644
> > index 0000000..f06cc234
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
> > @@ -0,0 +1,43 @@
> > +/*
> > + * Copyright (c) 2017 BayLibre SAS
> > + * Author: Neil Armstrong <[email protected]>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > + */
> > +
> > +&apb {
> > + mali: gpu@c0000 {
> > + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
> > + reg = <0x0 0xc0000 0x0 0x40000>;
> > + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "gp", "gpmmu", "pp", "pmu",
> > + "pp0", "ppmmu0", "pp1", "ppmmu1",
> > + "pp2", "ppmmu2";
> > + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
> > + clock-names = "bus", "core";
> > +
> > + /*
> > + * Mali clocking is provided by two identical clock paths
> > + * MALI_0 and MALI_1 muxed to a single clock by a glitch
> > + * free mux to safely change frequency while running.
> > + */
> > + assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
> > + <&clkc CLKID_MALI_0>,
> > + <&clkc CLKID_MALI>; /* Glitch free mux */
> > + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
> > + <0>, /* Do Nothing */
> > + <&clkc CLKID_MALI_0>;
> > + assigned-clock-rates = <0>, /* Do Nothing */
> > + <666666666>,
> > + <0>; /* Do Nothing */
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
> > index 615308e..5a90e30 100644
> > --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
> > +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
> > @@ -42,6 +42,7 @@
> > */
> >
> > #include "meson-gxl.dtsi"
> > +#include "meson-gxl-mali.dtsi"
> >
> > / {
> > compatible = "amlogic,s905d", "amlogic,meson-gxl";
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
> > index 08237ee..0f78d83 100644
> > --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
> > +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
> > @@ -42,6 +42,7 @@
> > */
> >
> > #include "meson-gxl.dtsi"
> > +#include "meson-gxl-mali.dtsi"
> >
> > / {
> > compatible = "amlogic,s905x", "amlogic,meson-gxl";
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Michael Turquette <[email protected]> writes:
> Quoting Kevin Hilman (2017-03-24 12:20:31)
>> Neil Armstrong <[email protected]> writes:
>>
>> > The same MALI-450 MP3 GPU is present in the GXBB and GXL SoCs.
>> >
>> > The node is simply added in the meson-gxbb.dtsi file.
>> >
>> > For GXL, since a lot is shared with the GXM that has a MALI-T820 IP, this
>> > patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific
>> > dtsi files.
>> >
>> > Signed-off-by: Neil Armstrong <[email protected]>
>>
>> LGTM, I can apply this when the clk driver changes are merged (feel free
>> to let me know when that happens, in case I'm not paying attention.)
>
> Applied to clk-meson, a stable branch, which has been merged into
> clk-next.
>
> Kevin, the dtsi is all yours.
Thanks, I applied it...
>>
>> <bikeshed>
>> nit: This series (and previous ones) use MALI, but I believe the correct
>> way is Mali. Could you standarize on that throughout the series?
>> </bikeshed>
>>
... after s/MALI/Mali/ in the changelog.
Kevin
On 03/28/2017 04:49 PM, Kevin Hilman wrote:
> Michael Turquette <[email protected]> writes:
>
>> Quoting Kevin Hilman (2017-03-24 12:20:31)
>>> Neil Armstrong <[email protected]> writes:
>>>
>>>> The same MALI-450 MP3 GPU is present in the GXBB and GXL SoCs.
>>>>
>>>> The node is simply added in the meson-gxbb.dtsi file.
>>>>
>>>> For GXL, since a lot is shared with the GXM that has a MALI-T820 IP, this
>>>> patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific
>>>> dtsi files.
>>>>
>>>> Signed-off-by: Neil Armstrong <[email protected]>
>>>
>>> LGTM, I can apply this when the clk driver changes are merged (feel free
>>> to let me know when that happens, in case I'm not paying attention.)
>>
>> Applied to clk-meson, a stable branch, which has been merged into
>> clk-next.
>>
>> Kevin, the dtsi is all yours.
>
> Thanks, I applied it...
>
>>>
>>> <bikeshed>
>>> nit: This series (and previous ones) use MALI, but I believe the correct
>>> way is Mali. Could you standarize on that throughout the series?
>>> </bikeshed>
>>>
>
> ... after s/MALI/Mali/ in the changelog.
>
> Kevin
>
Thanks Kevin,
Neil
On 03/22, Neil Armstrong wrote:
> +/*
> + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
> + * muxed by a glitch-free switch.
> + */
> +
> +static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
> +static const char *gxbb_mali_0_1_parent_names[] = {
const char * const?
> + "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
> + "fclk_div4", "fclk_div3", "fclk_div5"
> +};
> +
[..]
> + },
> +};
> +
> +static u32 mux_table_mali[] = {0, 1};
> +static const char *gxbb_mali_parent_names[] = {
It's a pattern, so I can only suspect something else is going on.
> + "mali_0", "mali_1"
> +};
> +
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project