The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension
but not completely identical, so this series
changes in v6:
- follow Anup's suggestion and hook into the (pending) cpuinfo patch [2]
instead of modifying the core sbi_get_* functions
changes in v5:
- add received Reviews
- fix sbi caching wrt. negative values (Drew)
- add comment about specific c9xx arch- and imp-ids (Conor)
changes in v4:
- add new patch to cache sbi mvendor, march and mimp-ids (Atish)
- errata dependencies in one line (Conor)
- make driver detection conditional on CONFIG_ERRATA_THEAD_PMU too (Atish)
changes in v3:
- improve commit message (Atish, Conor)
- IS_ENABLED and BIT() in errata probe (Conor)
The change depends on my cpufeature/t-head errata probe cleanup series [1].
changes in v2:
- use alternatives for the CSR access
- make the irq num selection a bit nicer
There is of course a matching opensbi-part whose most recent implementation
can be found on [0].
[0] https://patchwork.ozlabs.org/project/opensbi/cover/[email protected]
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/r/[email protected]
Heiko Stuebner (2):
RISC-V: Cache SBI vendor values
drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head
C9xx cores
arch/riscv/Kconfig.erratas | 13 +++++++++++
arch/riscv/errata/thead/errata.c | 19 ++++++++++++++++
arch/riscv/include/asm/errata_list.h | 16 ++++++++++++-
arch/riscv/include/asm/sbi.h | 5 ++++
arch/riscv/kernel/cpu.c | 30 +++++++++++++++++++++---
drivers/perf/riscv_pmu_sbi.c | 34 ++++++++++++++++++++--------
6 files changed, 103 insertions(+), 14 deletions(-)
--
2.35.1
On Tue, 11 Oct 2022 16:18:39 PDT (-0700), [email protected] wrote:
> The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension
> but not completely identical, so this series
The rest of that sentance got dropped, so I put in
The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension
but not completely identical, so this series adds a T-Head PMU errata
that handlen the differences.
but LMK if you had a better version, it's still early so I don't mind
swapping it around.
b4 also got kind of confused here so I had to merge suff manually.
> changes in v6:
> - follow Anup's suggestion and hook into the (pending) cpuinfo patch [2]
> instead of modifying the core sbi_get_* functions
>
> changes in v5:
> - add received Reviews
> - fix sbi caching wrt. negative values (Drew)
> - add comment about specific c9xx arch- and imp-ids (Conor)
>
> changes in v4:
> - add new patch to cache sbi mvendor, march and mimp-ids (Atish)
> - errata dependencies in one line (Conor)
> - make driver detection conditional on CONFIG_ERRATA_THEAD_PMU too (Atish)
>
> changes in v3:
> - improve commit message (Atish, Conor)
> - IS_ENABLED and BIT() in errata probe (Conor)
>
> The change depends on my cpufeature/t-head errata probe cleanup series [1].
>
>
> changes in v2:
> - use alternatives for the CSR access
> - make the irq num selection a bit nicer
>
> There is of course a matching opensbi-part whose most recent implementation
> can be found on [0].
>
>
> [0] https://patchwork.ozlabs.org/project/opensbi/cover/[email protected]
> [1] https://lore.kernel.org/all/[email protected]/
> [2] https://lore.kernel.org/r/[email protected]
>
> Heiko Stuebner (2):
> RISC-V: Cache SBI vendor values
> drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head
> C9xx cores
>
> arch/riscv/Kconfig.erratas | 13 +++++++++++
> arch/riscv/errata/thead/errata.c | 19 ++++++++++++++++
> arch/riscv/include/asm/errata_list.h | 16 ++++++++++++-
> arch/riscv/include/asm/sbi.h | 5 ++++
> arch/riscv/kernel/cpu.c | 30 +++++++++++++++++++++---
> drivers/perf/riscv_pmu_sbi.c | 34 ++++++++++++++++++++--------
> 6 files changed, 103 insertions(+), 14 deletions(-)
Am Donnerstag, 27. Oktober 2022, 07:02:59 CEST schrieb Palmer Dabbelt:
> On Tue, 11 Oct 2022 16:18:39 PDT (-0700), [email protected] wrote:
> > The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension
> > but not completely identical, so this series
>
> The rest of that sentance got dropped, so I put in
>
> The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension
> but not completely identical, so this series adds a T-Head PMU errata
> that handlen the differences.
>
> but LMK if you had a better version, it's still early so I don't mind
> swapping it around.
sounds just fine and sorry for not finishing that sentence on my own.
> b4 also got kind of confused here so I had to merge suff manually.
do you still know what b4 complained about?
My patch workflow is pretty basic (git format-patch + separate
git send-email) so I guess it might be interesting what it was
stumbling on.
Thanks
Heiko
> > changes in v6:
> > - follow Anup's suggestion and hook into the (pending) cpuinfo patch [2]
> > instead of modifying the core sbi_get_* functions
> >
> > changes in v5:
> > - add received Reviews
> > - fix sbi caching wrt. negative values (Drew)
> > - add comment about specific c9xx arch- and imp-ids (Conor)
> >
> > changes in v4:
> > - add new patch to cache sbi mvendor, march and mimp-ids (Atish)
> > - errata dependencies in one line (Conor)
> > - make driver detection conditional on CONFIG_ERRATA_THEAD_PMU too (Atish)
> >
> > changes in v3:
> > - improve commit message (Atish, Conor)
> > - IS_ENABLED and BIT() in errata probe (Conor)
> >
> > The change depends on my cpufeature/t-head errata probe cleanup series [1].
> >
> >
> > changes in v2:
> > - use alternatives for the CSR access
> > - make the irq num selection a bit nicer
> >
> > There is of course a matching opensbi-part whose most recent implementation
> > can be found on [0].
> >
> >
> > [0] https://patchwork.ozlabs.org/project/opensbi/cover/[email protected]
> > [1] https://lore.kernel.org/all/[email protected]/
> > [2] https://lore.kernel.org/r/[email protected]
> >
> > Heiko Stuebner (2):
> > RISC-V: Cache SBI vendor values
> > drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head
> > C9xx cores
> >
> > arch/riscv/Kconfig.erratas | 13 +++++++++++
> > arch/riscv/errata/thead/errata.c | 19 ++++++++++++++++
> > arch/riscv/include/asm/errata_list.h | 16 ++++++++++++-
> > arch/riscv/include/asm/sbi.h | 5 ++++
> > arch/riscv/kernel/cpu.c | 30 +++++++++++++++++++++---
> > drivers/perf/riscv_pmu_sbi.c | 34 ++++++++++++++++++++--------
> > 6 files changed, 103 insertions(+), 14 deletions(-)
>