2023-07-07 16:22:04

by Palmer Dabbelt

[permalink] [raw]
Subject: [GIT PULL] RISC-V Patches for the 6.5 Merge Window, Part 2

merged tag 'riscv-for-linus-6.5-mw1'
The following changes since commit 533925cb760431cb496a8c965cfd765a1a21d37e:

Merge tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2023-06-30 09:37:26 -0700)

are available in the Git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.5-mw2

for you to fetch changes up to e8605e8fdf42642048b7e59141deaf8e4cf06d71:

Merge patch series "riscv: some CMO alternative related clean up" (2023-07-06 10:32:38 -0700)

----------------------------------------------------------------
RISC-V Patches for the 6.5 Merge Window, Part 2

* A bunch of fixes/cleanups from the first part of the merge window,
mostly related to ACPI and vector as those were large.
* Some documentation improvements, mostly related to the new code.
* The "riscv,isa" DT key is deprecated.
* Support for link-time dead code elimination.
* Support for minor fault registration in userfaultd.
* A handful of cleanups around CMO alternatives.

----------------------------------------------------------------
The batch from yesterday morning didn't make it to linux-next, I just screwed
up and forgot to move them off staging in time. They're all fairly small and
still pass my tests, but I don't really like to skip linux-next so I figured
I'd say something.

Aside from that, things look fairly sane for what was a pretty large merge
window. There's one outstanding bug related to mapping symbols that manifests
in some randconfigs, there's a fix out already [1]. That's not a merge window
regression though, so I think it's safe to proceed. There's also a handful of
the normal merge window all{yes,mod}config issues, they have fixes on the lists
as well.

1: https://lore.kernel.org/all/[email protected]/

----------------------------------------------------------------
Andy Chiu (3):
riscv: vector: only enable interrupts in the first-use trap
riscv: vector: clear V-reg in the first-use trap
selftests: Test RISC-V Vector's first-use handler

Ben Dooks (1):
riscv: vdso: include vdso/vsyscall.h for vdso_data

Björn Töpel (1):
riscv: Discard vector state on syscalls

Conor Dooley (2):
RISC-V: drop error print from riscv_hartid_to_cpuid()
dt-bindings: riscv: deprecate riscv,isa

Jisheng Zhang (6):
riscv: move options to keep entries sorted
riscv: vmlinux-xip.lds.S: remove .alternative section
vmlinux.lds.h: use correct .init.data.* section name
riscv: errata: thead: only set cbom size & noncoherent during boot
riscv: mm: mark CBO relate initialization funcs as __init
riscv: mm: mark noncoherent_supported as __ro_after_init

John Hubbard (1):
mm: riscv: fix an unsafe pte read in huge_pte_alloc()

Marc Zyngier (1):
risc-v: Fix order of IPI enablement vs RCU startup

Nick Desaulniers (1):
riscv: disable HAVE_LD_DEAD_CODE_DATA_ELIMINATION for LLD

Palmer Dabbelt (5):
RISC-V: Document that V registers are clobbered on syscalls
RISC-V: Fix up some vector state related build failures
Merge patch series "riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION"
RISC-V: Document the ISA string parsing rules for ACPI
Merge patch series "riscv: some CMO alternative related clean up"

Samuel Holland (1):
riscv: Select HAVE_ARCH_USERFAULTFD_MINOR

Song Shuai (1):
riscv: Enable ARCH_SUSPEND_POSSIBLE for s2idle

Woody Zhang (1):
riscv: move memblock_allow_resize() after linear mapping is ready

Zhangjin Wu (1):
riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION

Documentation/devicetree/bindings/riscv/cpus.yaml | 43 ++--
.../devicetree/bindings/riscv/extensions.yaml | 250 +++++++++++++++++++++
Documentation/riscv/acpi.rst | 10 +
Documentation/riscv/index.rst | 1 +
Documentation/riscv/vector.rst | 8 +
arch/riscv/Kconfig | 18 +-
arch/riscv/errata/thead/errata.c | 7 +-
arch/riscv/include/asm/vector.h | 34 +++
arch/riscv/include/uapi/asm/sigcontext.h | 4 +
arch/riscv/kernel/smp.c | 1 -
arch/riscv/kernel/smpboot.c | 5 +-
arch/riscv/kernel/traps.c | 10 +-
arch/riscv/kernel/vdso.c | 1 +
arch/riscv/kernel/vector.c | 1 +
arch/riscv/kernel/vmlinux-xip.lds.S | 6 -
arch/riscv/kernel/vmlinux.lds.S | 6 +-
arch/riscv/mm/cacheflush.c | 8 +-
arch/riscv/mm/dma-noncoherent.c | 2 +-
arch/riscv/mm/hugetlbpage.c | 6 +-
arch/riscv/mm/init.c | 4 +-
include/asm-generic/vmlinux.lds.h | 2 +-
tools/testing/selftests/riscv/vector/.gitignore | 1 +
tools/testing/selftests/riscv/vector/Makefile | 6 +-
.../selftests/riscv/vector/v_initval_nolibc.c | 68 ++++++
24 files changed, 449 insertions(+), 53 deletions(-)
create mode 100644 Documentation/devicetree/bindings/riscv/extensions.yaml
create mode 100644 Documentation/riscv/acpi.rst
create mode 100644 tools/testing/selftests/riscv/vector/v_initval_nolibc.c


2023-07-07 17:25:27

by pr-tracker-bot

[permalink] [raw]
Subject: Re: [GIT PULL] RISC-V Patches for the 6.5 Merge Window, Part 2

The pull request you sent on Fri, 07 Jul 2023 08:51:13 -0700 (PDT):

> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.5-mw2

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/4f6b6c2b2f86b7878a770736bf478d8a263ff0bc

Thank you!

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