On Tue, 21 Nov 2017 08:57:07 PST (-0800), [email protected] wrote:
> From: Palmer Dabbelt
>> Sent: 20 November 2017 18:58
>>
>> The RISC-V ISA allows for instruction caches that are not coherent WRT
>> stores, even on a single hart. As a result, we need to explicitly flush
>> the instruction cache whenever marking a dirty page as executable in
>> order to preserve the correct system behavior.
>
> Isn't the I-flush only needed if there has been an unmap since the
> previous I-flush?
> Since code is rarely unmapped (exec and driver unload come to mind)
> the I-flush won't be needed very often.
There's nothing in the RISC-V ISA that prevents the instruction cache from
caching read-only (or even unmapped!) pages. Instructions fetched this manner
could never commit, but they could fill up the icache with garbage. I believe
that means we need to flush on dirty->execute, but if I'm wrong I'm happy to
change it.
From 1584695578537912495@xxx Tue Nov 21 16:57:52 +0000 2017
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